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- added reset out

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1154 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-22 19:35:46 +00:00
parent 94665d9c19
commit be1bae5243
3 changed files with 11 additions and 5 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+4 -2
View File
@@ -75,6 +75,7 @@ end sdram_ctrl_frontend64_wb;
architecture struct of sdram_ctrl_frontend64_wb is architecture struct of sdram_ctrl_frontend64_wb is
signal SDRAM_CLK0 : std_logic; signal SDRAM_CLK0 : std_logic;
signal SDRAM_RST0 : std_logic;
signal u_addr : user_addr_t; signal u_addr : user_addr_t;
signal u_tag_in : user_tag_t; signal u_tag_in : user_tag_t;
@@ -165,7 +166,7 @@ begin
) )
PORT MAP PORT MAP
( (
rst => RST_I, rst => SDRAM_RST0,
clk_w => CLK_I, clk_w => CLK_I,
clk_r => SDRAM_CLK0, clk_r => SDRAM_CLK0,
we => write_fifo_we, we => write_fifo_we,
@@ -187,7 +188,7 @@ begin
) )
PORT MAP PORT MAP
( (
rst => RST_I, rst => SDRAM_RST0,
clk_w => SDRAM_CLK0, clk_w => SDRAM_CLK0,
clk_r => CLK_I, clk_r => CLK_I,
we => read_fifo_we, we => read_fifo_we,
@@ -218,6 +219,7 @@ begin
sdram_clk => SDRAM_CLK_I, sdram_clk => SDRAM_CLK_I,
sdram_clk_fb => SDRAM_CLK_FB_I, sdram_clk_fb => SDRAM_CLK_FB_I,
sdram_clk_out => SDRAM_CLK0, sdram_clk_out => SDRAM_CLK0,
sdram_rst_out => SDRAM_RST0,
-- User interface -- User interface
u_data_vld => u_data_vld, u_data_vld => u_data_vld,
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+4 -2
View File
@@ -75,6 +75,7 @@ end sdram_ctrl_frontend_wb;
architecture struct of sdram_ctrl_frontend_wb is architecture struct of sdram_ctrl_frontend_wb is
signal SDRAM_CLK0 : std_logic; signal SDRAM_CLK0 : std_logic;
signal SDRAM_RST0 : std_logic;
signal u_addr : user_addr_t; signal u_addr : user_addr_t;
signal u_tag_in : user_tag_t; signal u_tag_in : user_tag_t;
@@ -165,7 +166,7 @@ begin
) )
PORT MAP PORT MAP
( (
rst => RST_I, rst => SDRAM_RST0,
clk_w => CLK_I, clk_w => CLK_I,
clk_r => SDRAM_CLK0, clk_r => SDRAM_CLK0,
we => write_fifo_we, we => write_fifo_we,
@@ -187,7 +188,7 @@ begin
) )
PORT MAP PORT MAP
( (
rst => RST_I, rst => SDRAM_RST0,
clk_w => SDRAM_CLK0, clk_w => SDRAM_CLK0,
clk_r => CLK_I, clk_r => CLK_I,
we => read_fifo_we, we => read_fifo_we,
@@ -218,6 +219,7 @@ begin
sdram_clk => SDRAM_CLK_I, sdram_clk => SDRAM_CLK_I,
sdram_clk_fb => SDRAM_CLK_FB_I, sdram_clk_fb => SDRAM_CLK_FB_I,
sdram_clk_out => SDRAM_CLK0, sdram_clk_out => SDRAM_CLK0,
sdram_rst_out => SDRAM_RST0,
-- User interface -- User interface
u_data_vld => u_data_vld, u_data_vld => u_data_vld,
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+2
View File
@@ -44,6 +44,7 @@ entity sdram_ctrl_top is
sdram_clk : in STD_LOGIC; sdram_clk : in STD_LOGIC;
sdram_clk_fb : in STD_LOGIC; sdram_clk_fb : in STD_LOGIC;
sdram_clk_out : out STD_LOGIC; sdram_clk_out : out STD_LOGIC;
sdram_rst_out : out STD_LOGIC;
-- User interface -- User interface
u_data_vld : out STD_LOGIC; u_data_vld : out STD_LOGIC;
@@ -118,6 +119,7 @@ architecture rtl of sdram_ctrl_top is
begin begin
sdram_clk_out <= sdram_clk0; sdram_clk_out <= sdram_clk0;
sdram_rst_out <= sdram_rst0;
--------------------------------- ---------------------------------
part_ctrl.cmd <= cmd_ctrl; part_ctrl.cmd <= cmd_ctrl;