From be1bae52437d7cdfc2144610b6eaf020acc5fa3b Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 22 May 2015 19:35:46 +0000 Subject: [PATCH] - added reset out git-svn-id: http://moon:8086/svn/vhdl/trunk@1154 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd | 6 ++++-- lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd | 8 +++++--- lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd | 2 ++ 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd index 197ef82..286dd70 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd @@ -75,6 +75,7 @@ end sdram_ctrl_frontend64_wb; architecture struct of sdram_ctrl_frontend64_wb is signal SDRAM_CLK0 : std_logic; + signal SDRAM_RST0 : std_logic; signal u_addr : user_addr_t; signal u_tag_in : user_tag_t; @@ -165,7 +166,7 @@ begin ) PORT MAP ( - rst => RST_I, + rst => SDRAM_RST0, clk_w => CLK_I, clk_r => SDRAM_CLK0, we => write_fifo_we, @@ -187,7 +188,7 @@ begin ) PORT MAP ( - rst => RST_I, + rst => SDRAM_RST0, clk_w => SDRAM_CLK0, clk_r => CLK_I, we => read_fifo_we, @@ -218,6 +219,7 @@ begin sdram_clk => SDRAM_CLK_I, sdram_clk_fb => SDRAM_CLK_FB_I, sdram_clk_out => SDRAM_CLK0, + sdram_rst_out => SDRAM_RST0, -- User interface u_data_vld => u_data_vld, diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd index 754fad3..51bc89a 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd @@ -75,6 +75,7 @@ end sdram_ctrl_frontend_wb; architecture struct of sdram_ctrl_frontend_wb is signal SDRAM_CLK0 : std_logic; + signal SDRAM_RST0 : std_logic; signal u_addr : user_addr_t; signal u_tag_in : user_tag_t; @@ -165,7 +166,7 @@ begin ) PORT MAP ( - rst => RST_I, + rst => SDRAM_RST0, clk_w => CLK_I, clk_r => SDRAM_CLK0, we => write_fifo_we, @@ -187,7 +188,7 @@ begin ) PORT MAP ( - rst => RST_I, + rst => SDRAM_RST0, clk_w => SDRAM_CLK0, clk_r => CLK_I, we => read_fifo_we, @@ -218,7 +219,8 @@ begin sdram_clk => SDRAM_CLK_I, sdram_clk_fb => SDRAM_CLK_FB_I, sdram_clk_out => SDRAM_CLK0, - + sdram_rst_out => SDRAM_RST0, + -- User interface u_data_vld => u_data_vld, u_data_req_w => u_req_wr, diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd index 07e2b7e..ee53b66 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd @@ -44,6 +44,7 @@ entity sdram_ctrl_top is sdram_clk : in STD_LOGIC; sdram_clk_fb : in STD_LOGIC; sdram_clk_out : out STD_LOGIC; + sdram_rst_out : out STD_LOGIC; -- User interface u_data_vld : out STD_LOGIC; @@ -118,6 +119,7 @@ architecture rtl of sdram_ctrl_top is begin sdram_clk_out <= sdram_clk0; + sdram_rst_out <= sdram_rst0; --------------------------------- part_ctrl.cmd <= cmd_ctrl;