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git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-21 11:37:55 +00:00
parent 73cfd45401
commit bdb8fec295
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projects/dlx/syn/ise/project/dlx_test.fdo
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## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jul 08 02:23:56 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_types.vhdl"
vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_instr.vhdl"
vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/memory.vhdl"
vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx-behavior.vhdl"
vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen.vhdl"
vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/memory-preloaded.vhdl"
vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen-behavior.vhdl"
vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_test-verifier.vhdl"
vsim -t 1ps -lib work dlx_test
do {dlx_test.udo}
view wave
add wave *
view structure
view signals
run 1000ns