jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
20 lines
843 B
Plaintext
20 lines
843 B
Plaintext
## NOTE: Do not edit this file.
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## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jul 08 02:23:56 Westeuropäische Sommerzeit 2006
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##
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vlib work
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vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_types.vhdl"
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vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_instr.vhdl"
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vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/memory.vhdl"
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vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx-behavior.vhdl"
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vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen.vhdl"
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vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/memory-preloaded.vhdl"
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vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen-behavior.vhdl"
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vcom -explicit -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_test-verifier.vhdl"
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vsim -t 1ps -lib work dlx_test
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do {dlx_test.udo}
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view wave
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add wave *
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view structure
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view signals
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run 1000ns
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