- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b

projects/dlx/syn/ise/project/controller.prj

@@ -0,0 +1,5 @@
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_types.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_instr.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/alu_types.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/controller.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/controller-behavior.vhdl"

projects/dlx/syn/ise/project/controller.xst

@@ -0,0 +1,4 @@
+set -tmpdir ./xst/projnav.tmp
+elaborate
+-ifn controller.prj
+-ifmt mixed

projects/dlx/syn/ise/project/controller_vhdl.prj

@@ -0,0 +1,5 @@
+work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_types.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_instr.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\alu_types.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\controller.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\controller-behavior.vhdl"

projects/dlx/syn/ise/project/dlx.fdo

@@ -0,0 +1,14 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jul 08 02:17:03 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_types.vhdl"
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_instr.vhdl"
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx-behavior.vhdl"
+vsim -t 1ps   -lib work dlx
+do {dlx.udo}
+view wave
+add wave *
+view structure
+view signals
+run 1000ns

projects/dlx/syn/ise/project/dlx.lso

@@ -0,0 +1 @@
+work

projects/dlx/syn/ise/project/dlx.prj

@@ -0,0 +1,3 @@
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_types.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_instr.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx-behavior.vhdl"

projects/dlx/syn/ise/project/dlx.udo

@@ -0,0 +1,4 @@
+-- ProjNav VHDL simulation template: dlx.udo
+-- You may edit this file after the line that starts with
+-- '-- START' to customize your simulation
+-- START user-defined simulation commands

projects/dlx/syn/ise/project/dlx.xst

@@ -0,0 +1,55 @@
+set -tmpdir ./xst/projnav.tmp
+set -xsthdpdir ./xst
+run
+-ifn dlx.prj
+-ifmt mixed
+-ofn dlx
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top dlx
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso dlx.lso
+-keep_hierarchy NO
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-mux_extract YES
+-resource_sharing YES
+-use_dsp48 auto
+-iobuf YES
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5

projects/dlx/syn/ise/project/dlx_test.fdo

@@ -0,0 +1,19 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jul 08 02:23:56 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_types.vhdl"
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_instr.vhdl"
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/memory.vhdl"
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx-behavior.vhdl"
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen.vhdl"
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/memory-preloaded.vhdl"
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen-behavior.vhdl"
+vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_test-verifier.vhdl"
+vsim -t 1ps   -lib work dlx_test
+do {dlx_test.udo}
+view wave
+add wave *
+view structure
+view signals
+run 1000ns

projects/dlx/syn/ise/project/dlx_test.lso

@@ -0,0 +1 @@
+work

projects/dlx/syn/ise/project/dlx_test.prj

@@ -0,0 +1,28 @@
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_types.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_instr.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/alu_types.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_plus_one_out_reset.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_plus_one_out.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_out.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_file.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/mux2.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/ir_extender.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/controller.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/alu.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_plus_one_out_reset-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_plus_one_out-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_out-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_file-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/mux2-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/ir_extender-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/controller-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/alu-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/memory.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/memory-file_loaded.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx-rtl.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen-behavior.vhdl"
+vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_test-verifier.vhdl"

projects/dlx/syn/ise/project/dlx_test.xst

@@ -0,0 +1,4 @@
+set -tmpdir ./xst/projnav.tmp
+elaborate
+-ifn dlx_test.prj
+-ifmt mixed

projects/dlx/syn/ise/project/dlx_test_vhdl.prj

@@ -0,0 +1,28 @@
+work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_types.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_instr.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\alu_types.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out_reset.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_out.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_file.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\mux2.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\ir_extender.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\controller.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\alu.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out_reset-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_out-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_file-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\reg-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\mux2-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\ir_extender-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\controller-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\alu-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\memory.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\clock_gen.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\memory-file_loaded.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx-rtl.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\clock_gen-behavior.vhdl"
+work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_test-verifier.vhdl"

projects/dlx/syn/ise/project/prjname.lso

@@ -0,0 +1 @@
+work