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[Xilinx/dpram_2w2r2c_ra]

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- re_a, re_b don't care

git-svn-id: http://moon:8086/svn/vhdl/trunk@1114 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2015-05-17 18:14:42 +00:00
parent bafe1745c5
commit bd3aa8c06e
1 changed files with 93 additions and 93 deletions
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lib/rams/dpram_2w2r2c_ra_xil.vhd
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------------------------------------------------------------------------- -------------------------------------------------------------------------
-- Project: Dual-Port RAM with 1 clock latency for simulation -- Project: Dual-Port RAM with 1 clock latency for simulation
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address -- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
-- Copyright (C) 2007 J. Ahrensfeld -- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or -- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public -- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either -- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version. -- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful, -- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details. -- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public -- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software -- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org -- For questions and ideas, please contact the author at jens@jayfield.org
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ -- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
----------------------------------------------------------------------- -----------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL; use IEEE.numeric_std.ALL;
entity dpram_2w2r2c_ra is entity dpram_2w2r2c_ra is
Generic Generic
( (
addr_width : integer := 3; addr_width : integer := 3;
data_width : integer := 8 data_width : integer := 8
); );
Port Port
( (
clk_a : in STD_LOGIC; clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC; clk_b : in STD_LOGIC;
re_a : in STD_LOGIC; re_a : in STD_LOGIC;
re_b : in STD_LOGIC; re_b : in STD_LOGIC;
we_a : in STD_LOGIC; we_a : in STD_LOGIC;
we_b : in STD_LOGIC; we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0); addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0); addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0); din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0); din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0); dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0) dout_b : out unsigned (data_width-1 downto 0)
); );
end dpram_2w2r2c_ra; end dpram_2w2r2c_ra;
architecture Behavioral of dpram_2w2r2c_ra is architecture Behavioral of dpram_2w2r2c_ra is
constant depth : integer := 2**addr_width; constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0); signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0); signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype; shared variable RAM : RAMtype;
begin begin
dout_a <= RAM(to_integer(addr_a_r)); dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r)); dout_b <= RAM(to_integer(addr_b_r));
process (clk_a) process (clk_a)
begin begin
if clk_a'event and clk_a = '1' then if clk_a'event and clk_a = '1' then
if we_a = '1' then if we_a = '1' then
RAM(to_integer(addr_a)) := din_a; RAM(to_integer(addr_a)) := din_a;
end if; end if;
if re_a = '1' then -- if re_a = '1' then
addr_a_r <= addr_a; addr_a_r <= addr_a;
end if; -- end if;
end if; end if;
end process; end process;
process (clk_b) process (clk_b)
begin begin
if clk_b'event and clk_b = '1' then if clk_b'event and clk_b = '1' then
if we_b = '1' then if we_b = '1' then
RAM(to_integer(addr_b)) := din_b; RAM(to_integer(addr_b)) := din_b;
end if; end if;
if re_b = '1' then -- if re_b = '1' then
addr_b_r <= addr_b; addr_b_r <= addr_b;
end if; -- end if;
end if; end if;
end process; end process;
end Behavioral; end Behavioral;