diff --git a/lib/rams/dpram_2w2r2c_ra_xil.vhd b/lib/rams/dpram_2w2r2c_ra_xil.vhd
index 774c88e..aaedcaf 100644
--- a/lib/rams/dpram_2w2r2c_ra_xil.vhd
+++ b/lib/rams/dpram_2w2r2c_ra_xil.vhd
@@ -1,93 +1,93 @@
--------------------------------------------------------------------------
--- Project: Dual-Port RAM with 1 clock latency for simulation
--- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r2c_ra is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		re_a		: in  STD_LOGIC;
-		re_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r2c_ra;
-
-architecture Behavioral of dpram_2w2r2c_ra is
-
-	constant depth : integer := 2**addr_width;
-	signal addr_a_r : unsigned (addr_width-1 downto 0);
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-	dout_a <= RAM(to_integer(addr_a_r));
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if we_a = '1' then
-		RAM(to_integer(addr_a)) := din_a;
-	end if;
-	if re_a = '1' then
-		addr_a_r	<= addr_a;
-	end if;
-end if;
-end process;
-
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if we_b = '1' then
-		RAM(to_integer(addr_b)) := din_b;
-	end if;
-	if re_b = '1' then
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-end Behavioral;
-
+-------------------------------------------------------------------------
+-- Project: Dual-Port RAM with 1 clock latency for simulation
+-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_2w2r2c_ra is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		re_a		: in  STD_LOGIC;
+		re_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_2w2r2c_ra;
+
+architecture Behavioral of dpram_2w2r2c_ra is
+
+	constant depth : integer := 2**addr_width;
+	signal addr_a_r : unsigned (addr_width-1 downto 0);
+	signal addr_b_r : unsigned (addr_width-1 downto 0);
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	shared variable RAM : RAMtype;
+	
+begin
+
+	dout_a <= RAM(to_integer(addr_a_r));
+	dout_b <= RAM(to_integer(addr_b_r));
+
+process (clk_a)
+begin
+if clk_a'event and clk_a = '1' then
+	if we_a = '1' then
+		RAM(to_integer(addr_a)) := din_a;
+	end if;
+--	if re_a = '1' then
+		addr_a_r	<= addr_a;
+--	end if;
+end if;
+end process;
+
+
+process (clk_b)
+begin
+if clk_b'event and clk_b = '1' then
+	if we_b = '1' then
+		RAM(to_integer(addr_b)) := din_b;
+	end if;
+--	if re_b = '1' then
+		addr_b_r	<= addr_b;
+--	end if;
+end if;
+end process;
+
+end Behavioral;
+