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- made time specs in SDRAM_config independent of SDRAM clock

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git-svn-id: http://moon:8086/svn/vhdl/trunk@718 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 12:54:24 +00:00
parent 010edebc97
commit b8a69d571a
4 changed files with 23 additions and 21 deletions
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projects/mips_sys/src/sdram_config.vhd
+8 -8
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@@ -54,18 +54,18 @@ package sdram_config is
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
constant REFRESH_INTERVAL : real := 7.8125; -- us
constant REFRESH_INTERVAL : real := 7.8125E-6; -- [s]
-- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : positive := 2; -- precharge command period
constant TRAS : positive := 5; -- active to precharge delay
constant TRFC : positive := 8; -- auto refresh command period
constant TMRD : positive := 2; -- load mode register command cylce time
constant TRCD : positive := 2; -- active to read or write delay !
constant TWR : positive := 2; -- write recovery time
constant TRP : real := 20.0E-9; -- precharge command period [s]
constant TRAS : real := 45.0E-9; -- active to precharge delay [s]
constant TRFC : real := 75.0E-9; -- auto refresh command period [s]
constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
constant TRCD : real := 20.0E-9; -- active to read or write delay [s]
constant TWR : real := 15.0E-9; -- write recovery time [s]
constant PWR_UP_WAIT : natural := 222; -- µs
constant PWR_UP_WAIT : real := 220.0E-6; -- [s]
subtype user_tag_t is unsigned(3 downto 0);