diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd
index 9fee083..920df2f 100644
--- a/projects/mips_sys/src/mips_sys.vhd
+++ b/projects/mips_sys/src/mips_sys.vhd
@@ -846,7 +846,7 @@ inst_uart_wb_1 : uart_wb
 inst_clockgen : entity work.clockgen
 	GENERIC MAP
 	(
-		clk_in_freq_hz			=> 100E6,
+		clk_in_freq_hz			=> sys_freq,
 		vga_clk_out_freq_hz		=> tsvga.f_pxl_clk,
 		sdr_clk0_out_phaseshift	=> 0,
 		sdr_clk1_out_phaseshift	=> 0
@@ -871,7 +871,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
 	GENERIC MAP
 	(
 		BL					=> BURST_LEN,
-		f_sysclk			=> ddr_frequency_hz,
+		f_sysclk_hz			=> sys_freq,
+		f_sdrclk_hz			=> ddr_frequency_hz,
 		fifo_depth			=> 5
 	)
 	PORT MAP
diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd
index 44749a5..5c78426 100644
--- a/projects/mips_sys/src/mips_sys_sim.vhd
+++ b/projects/mips_sys/src/mips_sys_sim.vhd
@@ -995,9 +995,10 @@ inst_clockgen : entity work.clockgen
 inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
 	GENERIC MAP
 	(
-		BL			=> BURST_LEN,
-		f_sysclk	=> ddr_frequency_hz,
-		fifo_depth	=> 5
+		BL				=> BURST_LEN,
+		f_sysclk_hz		=> ddr_frequency_hz,
+		f_sdrclk_hz		=> sys_freq,
+		fifo_depth		=> 5
 	)
 	PORT MAP
 	(
diff --git a/projects/mips_sys/src/sdram_config.vhd b/projects/mips_sys/src/sdram_config.vhd
index 1bdf8e0..d679457 100644
--- a/projects/mips_sys/src/sdram_config.vhd
+++ b/projects/mips_sys/src/sdram_config.vhd
@@ -54,18 +54,18 @@ package sdram_config is
 	
 	-- DDR-SDR TIMING constants ------------------------------------------------------------------
 	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL : real := 7.8125; -- us
+	constant REFRESH_INTERVAL	: real := 7.8125E-6; -- [s]
 
 	-- These values are for your SDRAM part (see datasheet) 
 	constant TCAS : positive  := 2;   -- CAS latency [clocks]
-	constant TRP  : positive  := 2;   -- precharge command period
-	constant TRAS : positive  := 5;   -- active to precharge delay 
-	constant TRFC : positive  := 8;   -- auto refresh command period
-	constant TMRD : positive  := 2;   -- load mode register command cylce time
-	constant TRCD : positive  := 2;   -- active to read or write delay !
-	constant TWR  : positive  := 2;   -- write recovery time
+	constant TRP  : real		:= 20.0E-9;		-- precharge command period [s]
+	constant TRAS : real		:= 45.0E-9;		-- active to precharge delay [s]
+	constant TRFC : real		:= 75.0E-9;		-- auto refresh command period [s]
+	constant TMRD : positive	:= 2;			-- load mode register command cylce time [clocks]
+	constant TRCD : real		:= 20.0E-9;		-- active to read or write delay [s]
+	constant TWR  : real		:= 15.0E-9;		-- write recovery time [s]
 
-	constant PWR_UP_WAIT : natural := 222; -- µs
+	constant PWR_UP_WAIT		: real := 220.0E-6; -- [s]
 
 	subtype user_tag_t is unsigned(3 downto 0);
 
diff --git a/projects/mips_sys/src/sdram_config_sim.vhd b/projects/mips_sys/src/sdram_config_sim.vhd
index f698b29..ccbfbbb 100644
--- a/projects/mips_sys/src/sdram_config_sim.vhd
+++ b/projects/mips_sys/src/sdram_config_sim.vhd
@@ -54,18 +54,18 @@ package sdram_config is
 	
 	-- DDR-SDR TIMING constants ------------------------------------------------------------------
 	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL : real := 7.8125; -- us
+	constant REFRESH_INTERVAL	: real := 7.8125E-6; -- [s]
 
 	-- These values are for your SDRAM part (see datasheet) 
 	constant TCAS : positive  := 2;   -- CAS latency [clocks]
-	constant TRP  : positive  := 2;   -- precharge command period
-	constant TRAS : positive  := 5;   -- active to precharge delay 
-	constant TRFC : positive  := 8;   -- auto refresh command period
-	constant TMRD : positive  := 2;   -- load mode register command cylce time
-	constant TRCD : positive  := 2;   -- active to read or write delay !
-	constant TWR  : positive  := 2;   -- write recovery time
+	constant TRP  : real		:= 20.0E-9;		-- precharge command period [s]
+	constant TRAS : real		:= 45.0E-9;		-- active to precharge delay [s]
+	constant TRFC : real		:= 75.0E-9;		-- auto refresh command period [s]
+	constant TMRD : positive	:= 2;			-- load mode register command cylce time [clocks]
+	constant TRCD : real		:= 20.0E-9;		-- active to read or write delay [s]
+	constant TWR  : real		:= 15.0E-9;		-- write recovery time [s]
 
-	constant PWR_UP_WAIT : natural := 22; -- µs
+	constant PWR_UP_WAIT		: real := 22.0E-6; -- [s]
 
 	subtype user_tag_t is unsigned(3 downto 0);