- sdram_ctrl_frontend_wb32.vhd.vhd implements J-Bus interface and exports abstract PHY interface
- ctrl_ddr_wb32 wraps sdram_ctrl_frontend_wb32 and adds specific PHY. This is now our new top level file git-svn-id: http://moon:8086/svn/vhdl/trunk@1197 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -18,13 +18,13 @@ vcom -explicit -93 "../src/sdram_ctrl.vhd"
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vcom -explicit -93 "../src/ddr_clk_virtex4.vhd"
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vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
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vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
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vcom -explicit -93 "../src/sdram_ctrl_frontend64_wb.vhd"
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vcom -explicit -93 "../src/ctrl_ddr_wb.vhd"
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vcom -explicit -93 "../src/sdram_ctrl_frontend_wb32.vhd"
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vcom -explicit -93 "../src/ctrl_ddr_wb32.vhd"
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vcom -explicit -93 "../src/mt46v16m16.vhd"
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vcom -explicit -93 "../src/tb_ctrl_ddr_wb.vhd"
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vcom -explicit -93 "../src/tb_ctrl_ddr_wb32.vhd"
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vsim -t 1ps -lib work tb_ctrl_ddr_wb
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do {tb_ctrl_ddr_wb.wdo}
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vsim -t 1ps -lib work tb_ctrl_ddr_wb32
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do {tb_ctrl_ddr_wb32.wdo}
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view wave
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view structure
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view signals
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@@ -1,40 +1,38 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider J-Bus
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/clk_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/rst_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/cyc_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/stb_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/we_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/sel_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/ack_i
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/mrdy_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/dat_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/clk_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/rst_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/cyc_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/stb_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/we_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/sel_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/ack_i
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/mrdy_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/dat_o
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add wave -noupdate -divider SDRAM
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/sdclk
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/sdclk_fb
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_clk_p
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_clk_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_cke
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_cs_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_we_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_ras_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_cas_n
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb/part_ba
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb/part_dm
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb/part_dqs
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/part_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/part_data
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/sdclk
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/sdclk_fb
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_clk_p
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_clk_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_cke
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_cs_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_we_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_ras_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_cas_n
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/part_ba
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/part_dm
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/part_dqs
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/part_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/part_data
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add wave -noupdate -divider Test
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb/sd_cmd
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb/dout_rst
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/sddat
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb/sdsel
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/dout_reg
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb/dout_cnt
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/sd_cmd
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/dout_rst
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/dout_reg
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/dout_cnt
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {189465865 ps} 0}
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configure wave -namecolwidth 150
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@@ -0,0 +1,154 @@
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-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: cpu_embedded using cpu_core and rom
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.fifo_ctrl_pkg.all;
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use work.sdram_config.all;
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use work.sdram_types.all;
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entity ctrl_ddr_wb32 is
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Generic
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(
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BURST_LEN : natural := 2;
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F_SYSCLK : real := 100.0;
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F_SDRCLK : real := 100.0;
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FIFO_DEPTH : integer := 4
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);
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Port
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(
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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SDRAM_CLK_I : in STD_LOGIC;
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SDRAM_CLK_FB_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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-- SDRAM signals
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sd_clk_p : out STD_LOGIC;
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sd_clk_n : out STD_LOGIC;
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sd_cke : out STD_LOGIC;
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sd_cs_n : out STD_LOGIC;
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sd_cas_n : out STD_LOGIC;
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sd_ras_n : out STD_LOGIC;
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sd_we_n : out STD_LOGIC;
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sd_addr : out sdr_addr_t;
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sd_ba : out sdr_ba_t;
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sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
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sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
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sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
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);
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end ctrl_ddr_wb32;
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architecture struct of ctrl_ddr_wb32 is
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signal sdram_clk0 : std_logic;
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signal sdram_rst0 : std_logic;
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signal phy_ctrl : phy_ctrl_t;
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signal phy_in : phy_in_t;
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signal phy_out : phy_out_t;
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begin
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-- DDR SDRAM Controller Core
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sdram_ctrl_frontend_wb32 : entity work.sdram_ctrl_frontend_wb32
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GENERIC MAP
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(
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BURST_LEN => BURST_LEN,
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F_SYSCLK => F_SYSCLK,
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F_SDRCLK => F_SDRCLK,
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FIFO_DEPTH => FIFO_DEPTH
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)
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PORT MAP
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(
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RST_I => RST_I,
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CLK_I => CLK_I,
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SDRAM_RST0 => sdram_rst0,
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SDRAM_CLK0 => sdram_clk0,
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CYC_I => CYC_I,
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STB_I => STB_I,
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SEL_I => SEL_I,
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WE_I => WE_I,
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ACK_O => ACK_O,
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SRDY_O => SRDY_O,
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MRDY_I => MRDY_I,
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ADDR_I => ADDR_I,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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-- PHY signals
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phy_in => phy_in,
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phy_out => phy_out,
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phy_ctrl => phy_ctrl
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);
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-- DDR phy
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inst_sdram_phy : entity work.sdram_phy
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Generic map
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(
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F_SDRCLK => F_SDRCLK
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)
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Port map
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(
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-- Clock interface
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rst => RST_I,
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clk => SDRAM_CLK_I,
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clk_fb => SDRAM_CLK_FB_I,
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clk0_out => sdram_clk0,
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rst0_out => sdram_rst0,
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-- PHY interface
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phy_in => phy_in,
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phy_out => phy_out,
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phy_ctrl => phy_ctrl,
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-- SDRAM part interface
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part_clk_p => sd_clk_p,
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part_clk_n => sd_clk_n,
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part_addr => sd_addr,
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part_ba => sd_ba,
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part_dm => sd_dm,
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part_dqs => sd_dqs,
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part_data => sd_data,
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part_cs_n => sd_cs_n,
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part_we_n => sd_we_n,
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part_cas_n => sd_cas_n,
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part_ras_n => sd_ras_n,
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part_cke => sd_cke
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);
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end architecture struct;
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@@ -29,7 +29,7 @@ use work.fifo_ctrl_pkg.all;
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use work.sdram_config.all;
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use work.sdram_types.all;
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entity sdram_ctrl_frontend_wb is
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entity sdram_ctrl_frontend_wb32 is
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Generic
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(
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BURST_LEN : natural := 2;
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@@ -75,9 +75,9 @@ entity sdram_ctrl_frontend_wb is
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sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
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);
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end sdram_ctrl_frontend_wb;
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end sdram_ctrl_frontend_wb32;
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architecture struct of sdram_ctrl_frontend_wb is
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architecture struct of sdram_ctrl_frontend_wb32 is
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signal u_addr : user_addr_t;
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signal u_tag_in : user_tag_t;
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@@ -28,10 +28,10 @@ use IEEE.numeric_std.ALL;
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use work.sdram_config.all;
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use work.sdram_types.all;
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entity tb_ctrl_ddr_wb is
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entity tb_ctrl_ddr_wb32 is
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end;
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architecture struct of tb_ctrl_ddr_wb is
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architecture struct of tb_ctrl_ddr_wb32 is
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constant CLK_PERIOD : time := 10 ns;
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constant SDCLK_PERIOD : time := 7.5 ns;
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@@ -109,7 +109,7 @@ begin
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sdclk_fb <= part_clk_p after 1 ns;
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-- DDR SDRAM Controller Core
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uut : entity work.ctrl_ddr_wb
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uut : entity work.ctrl_ddr_wb32
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GENERIC MAP
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(
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BURST_LEN => BURST_LEN,
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Reference in New Issue
Block a user