diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo index 7d04c47..32fcdd0 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo @@ -18,13 +18,13 @@ vcom -explicit -93 "../src/sdram_ctrl.vhd" vcom -explicit -93 "../src/ddr_clk_virtex4.vhd" vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/sdram_ctrl_frontend64_wb.vhd" -vcom -explicit -93 "../src/ctrl_ddr_wb.vhd" +vcom -explicit -93 "../src/sdram_ctrl_frontend_wb32.vhd" +vcom -explicit -93 "../src/ctrl_ddr_wb32.vhd" vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_ctrl_ddr_wb.vhd" +vcom -explicit -93 "../src/tb_ctrl_ddr_wb32.vhd" -vsim -t 1ps -lib work tb_ctrl_ddr_wb -do {tb_ctrl_ddr_wb.wdo} +vsim -t 1ps -lib work tb_ctrl_ddr_wb32 +do {tb_ctrl_ddr_wb32.wdo} view wave view structure view signals diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.wdo index 40001c7..f36b7b2 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.wdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.wdo @@ -1,40 +1,38 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -divider J-Bus -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/clk_o -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/rst_o -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/cyc_o -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/stb_o -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/we_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/sel_o -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/ack_i -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/mrdy_o -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/dat_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/clk_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/rst_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/cyc_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/stb_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/we_o +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/sel_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/ack_i +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/mrdy_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/dat_o add wave -noupdate -divider SDRAM -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/sdclk -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/sdclk_fb -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_clk_p -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_clk_n -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_cke -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_cs_n -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_we_n -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_ras_n -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_cas_n -add wave -noupdate -format Literal /tb_ctrl_ddr_wb/part_ba -add wave -noupdate -format Literal /tb_ctrl_ddr_wb/part_dm -add wave -noupdate -format Literal /tb_ctrl_ddr_wb/part_dqs -add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/part_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/part_data +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/sdclk +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/sdclk_fb +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_clk_p +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_clk_n +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_cke +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_cs_n +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_we_n +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_ras_n +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/part_cas_n +add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/part_ba +add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/part_dm +add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/part_dqs +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/part_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/part_data add wave -noupdate -divider Test -add wave -noupdate -format Literal /tb_ctrl_ddr_wb/sd_cmd -add wave -noupdate -format Logic /tb_ctrl_ddr_wb/dout_rst -add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/sddat -add wave -noupdate -format Literal /tb_ctrl_ddr_wb/sdsel -add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/dout_reg -add wave -noupdate -format Literal /tb_ctrl_ddr_wb/dout_cnt +add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/sd_cmd +add wave -noupdate -format Logic /tb_ctrl_ddr_wb32/dout_rst +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb32/dout_reg +add wave -noupdate -format Literal /tb_ctrl_ddr_wb32/dout_cnt TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {189465865 ps} 0} configure wave -namecolwidth 150 diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb32.vhd new file mode 100644 index 0000000..0e11562 --- /dev/null +++ b/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb32.vhd @@ -0,0 +1,154 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: cpu_embedded using cpu_core and rom +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +use work.fifo_ctrl_pkg.all; +use work.sdram_config.all; +use work.sdram_types.all; + +entity ctrl_ddr_wb32 is + Generic + ( + BURST_LEN : natural := 2; + F_SYSCLK : real := 100.0; + F_SDRCLK : real := 100.0; + FIFO_DEPTH : integer := 4 + ); + Port + ( + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + SDRAM_CLK_I : in STD_LOGIC; + SDRAM_CLK_FB_I : in STD_LOGIC; + + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + SRDY_O : out STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + + -- SDRAM signals + sd_clk_p : out STD_LOGIC; + sd_clk_n : out STD_LOGIC; + sd_cke : out STD_LOGIC; + sd_cs_n : out STD_LOGIC; + sd_cas_n : out STD_LOGIC; + sd_ras_n : out STD_LOGIC; + sd_we_n : out STD_LOGIC; + sd_addr : out sdr_addr_t; + sd_ba : out sdr_ba_t; + sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); + sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); + sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) + + ); +end ctrl_ddr_wb32; + +architecture struct of ctrl_ddr_wb32 is + + signal sdram_clk0 : std_logic; + signal sdram_rst0 : std_logic; + + signal phy_ctrl : phy_ctrl_t; + signal phy_in : phy_in_t; + signal phy_out : phy_out_t; +begin + + -- DDR SDRAM Controller Core + sdram_ctrl_frontend_wb32 : entity work.sdram_ctrl_frontend_wb32 + GENERIC MAP + ( + BURST_LEN => BURST_LEN, + F_SYSCLK => F_SYSCLK, + F_SDRCLK => F_SDRCLK, + FIFO_DEPTH => FIFO_DEPTH + ) + PORT MAP + ( + RST_I => RST_I, + CLK_I => CLK_I, + SDRAM_RST0 => sdram_rst0, + SDRAM_CLK0 => sdram_clk0, + + CYC_I => CYC_I, + STB_I => STB_I, + SEL_I => SEL_I, + WE_I => WE_I, + ACK_O => ACK_O, + SRDY_O => SRDY_O, + MRDY_I => MRDY_I, + ADDR_I => ADDR_I, + DAT_I => DAT_I, + DAT_O => DAT_O, + + -- PHY signals + phy_in => phy_in, + phy_out => phy_out, + phy_ctrl => phy_ctrl + + ); + + -- DDR phy + inst_sdram_phy : entity work.sdram_phy + Generic map + ( + F_SDRCLK => F_SDRCLK + ) + Port map + ( + -- Clock interface + rst => RST_I, + clk => SDRAM_CLK_I, + clk_fb => SDRAM_CLK_FB_I, + clk0_out => sdram_clk0, + rst0_out => sdram_rst0, + + -- PHY interface + phy_in => phy_in, + phy_out => phy_out, + phy_ctrl => phy_ctrl, + + -- SDRAM part interface + part_clk_p => sd_clk_p, + part_clk_n => sd_clk_n, + part_addr => sd_addr, + part_ba => sd_ba, + part_dm => sd_dm, + part_dqs => sd_dqs, + part_data => sd_data, + part_cs_n => sd_cs_n, + part_we_n => sd_we_n, + part_cas_n => sd_cas_n, + part_ras_n => sd_ras_n, + part_cke => sd_cke + ); + +end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd index d06b589..b161ef9 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd @@ -29,7 +29,7 @@ use work.fifo_ctrl_pkg.all; use work.sdram_config.all; use work.sdram_types.all; -entity sdram_ctrl_frontend_wb is +entity sdram_ctrl_frontend_wb32 is Generic ( BURST_LEN : natural := 2; @@ -75,9 +75,9 @@ entity sdram_ctrl_frontend_wb is sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) ); -end sdram_ctrl_frontend_wb; +end sdram_ctrl_frontend_wb32; -architecture struct of sdram_ctrl_frontend_wb is +architecture struct of sdram_ctrl_frontend_wb32 is signal u_addr : user_addr_t; signal u_tag_in : user_tag_t; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd index 93bf85f..a2fdb44 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd @@ -28,10 +28,10 @@ use IEEE.numeric_std.ALL; use work.sdram_config.all; use work.sdram_types.all; -entity tb_ctrl_ddr_wb is +entity tb_ctrl_ddr_wb32 is end; -architecture struct of tb_ctrl_ddr_wb is +architecture struct of tb_ctrl_ddr_wb32 is constant CLK_PERIOD : time := 10 ns; constant SDCLK_PERIOD : time := 7.5 ns; @@ -109,7 +109,7 @@ begin sdclk_fb <= part_clk_p after 1 ns; -- DDR SDRAM Controller Core - uut : entity work.ctrl_ddr_wb + uut : entity work.ctrl_ddr_wb32 GENERIC MAP ( BURST_LEN => BURST_LEN,