- renamed

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git-svn-id: http://moon:8086/svn/vhdl/trunk@297 cc03376c-175c-47c8-b038-4cd826a8556b

lib/FIFO/src/sync_fifo_ctrl.vhd

@@ -1,35 +1,34 @@
 -------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The call/return/data stack
-
+-- Project: FIFO, generic FIFOs written in VHDL
+-- Release 1
+--
 -- Copyright (C) 2007 J. Ahrensfeld
-
+--
 -- This library is free software; you can redistribute it and/or
 -- modify it under the terms of the GNU Lesser General Public
 -- License as published by the Free Software Foundation; either
 -- version 2.1 of the License, or (at your option) any later version.
-
+--
 -- This library is distributed in the hope that it will be useful,
 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 -- Lesser General Public License for more details.
-
+--
 -- You should have received a copy of the GNU Lesser General Public
 -- License along with this library; if not, write to the Free Software
 -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
+--
 -- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.2 2008-10-12 18:04:36 Jens Exp $
+--
 -----------------------------------------------------------------------
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.ALL;
 
-entity sync_fifo_ctrl is
-	Generic (
+entity fifo_sync_ctrl is
+	Generic
+	(
 		addr_width : integer := 3;
 		almost_full_thresh : integer := 6;
 		almost_empty_thresh : integer := 2
@@ -49,9 +48,9 @@ entity sync_fifo_ctrl is
 		fifo_afull		: out STD_LOGIC;
 		fifo_aempty		: out STD_LOGIC
 	);
-end sync_fifo_ctrl;
+end fifo_sync_ctrl;
 
-architecture Behavioral of sync_fifo_ctrl is
+architecture Behavioral of fifo_sync_ctrl is
 
 	signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
 	signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);