diff --git a/lib/FIFO/src/async_fifo_ctrl.vhd b/lib/FIFO/src/async_fifo_ctrl.vhd index a7db023..c0fd7b6 100644 --- a/lib/FIFO/src/async_fifo_ctrl.vhd +++ b/lib/FIFO/src/async_fifo_ctrl.vhd @@ -1,27 +1,25 @@ ------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack - +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- -- Copyright (C) 2007 J. Ahrensfeld - +-- -- This library is free software; you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public -- License as published by the Free Software Foundation; either -- version 2.1 of the License, or (at your option) any later version. - +-- -- This library is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- Lesser General Public License for more details. - +-- -- You should have received a copy of the GNU Lesser General Public -- License along with this library; if not, write to the Free Software -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - +-- -- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.2 2008-10-25 11:21:47 Jens Exp $ +-- ----------------------------------------------------------------------- library IEEE; @@ -31,8 +29,9 @@ use IEEE.numeric_std.ALL; LIBRARY WORK; USE WORK.FIFO_CTRL_PKG.ALL; -entity async_fifo_ctrl is - Generic ( +entity fifo_async_ctrl is + Generic + ( addr_width : integer := 3; almost_full_thresh : integer := 6; almost_empty_thresh : integer := 2 @@ -51,9 +50,9 @@ entity async_fifo_ctrl is fifo_afull : out STD_LOGIC; fifo_aempty : out STD_LOGIC ); -end async_fifo_ctrl; +end fifo_async_ctrl; -architecture Behavioral of async_fifo_ctrl is +architecture Behavioral of fifo_async_ctrl is signal gcnt_w : unsigned (addr_width downto 0); signal gcnt2_w : unsigned (addr_width downto 0); @@ -211,11 +210,13 @@ proc_status_almost_empty: end process; inst_gray_counter_w : entity work.gray_counter - generic map ( + generic map + ( width => addr_width+1, init_value => 0 ) - port map ( + port map + ( rst => rst, clk => clk_w, ce => winc, @@ -226,11 +227,13 @@ inst_gray_counter_w : entity work.gray_counter ); inst_gray_counter_r : entity work.gray_counter - generic map ( + generic map + ( width => addr_width+1, init_value => 0 ) - port map ( + port map + ( rst => rst, clk => clk_r, ce => rinc, diff --git a/lib/FIFO/src/fifo_sync_dist.vhd b/lib/FIFO/src/fifo_sync_dist.vhd index 5914cd9..beb89f5 100644 --- a/lib/FIFO/src/fifo_sync_dist.vhd +++ b/lib/FIFO/src/fifo_sync_dist.vhd @@ -72,7 +72,7 @@ begin fifo_afull <= almost_full; fifo_aempty <= almost_empty; - inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl + inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl GENERIC MAP ( addr_width => addr_width, diff --git a/lib/FIFO/src/sync_fifo_ctrl.vhd b/lib/FIFO/src/sync_fifo_ctrl.vhd index c533377..c0f293e 100644 --- a/lib/FIFO/src/sync_fifo_ctrl.vhd +++ b/lib/FIFO/src/sync_fifo_ctrl.vhd @@ -1,35 +1,34 @@ ------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack - +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- -- Copyright (C) 2007 J. Ahrensfeld - +-- -- This library is free software; you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public -- License as published by the Free Software Foundation; either -- version 2.1 of the License, or (at your option) any later version. - +-- -- This library is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- Lesser General Public License for more details. - +-- -- You should have received a copy of the GNU Lesser General Public -- License along with this library; if not, write to the Free Software -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - +-- -- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.2 2008-10-12 18:04:36 Jens Exp $ +-- ----------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; -entity sync_fifo_ctrl is - Generic ( +entity fifo_sync_ctrl is + Generic + ( addr_width : integer := 3; almost_full_thresh : integer := 6; almost_empty_thresh : integer := 2 @@ -49,9 +48,9 @@ entity sync_fifo_ctrl is fifo_afull : out STD_LOGIC; fifo_aempty : out STD_LOGIC ); -end sync_fifo_ctrl; +end fifo_sync_ctrl; -architecture Behavioral of sync_fifo_ctrl is +architecture Behavioral of fifo_sync_ctrl is signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0); signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0); diff --git a/lib/FIFO/src/tb_fifo_async.vhd b/lib/FIFO/src/tb_fifo_async.vhd new file mode 100644 index 0000000..e0c2b62 --- /dev/null +++ b/lib/FIFO/src/tb_fifo_async.vhd @@ -0,0 +1,222 @@ +------------------------------------------------------------------------- +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE STD.TEXTIO.ALL; + +-- LIBRARY WORK; +-- USE.YOURLIB.WHATELSE + +ENTITY tb_fifo_async IS +END tb_fifo_async; + +ARCHITECTURE behavior OF tb_fifo_async IS + + --Constants + constant PERIOD_W : time := 10 ns; + constant PERIOD_R : time := 22.1 ns; + constant ADDR_WIDTH : integer := 3; + constant DATA_WIDTH : integer := 8; + + --Inputs + signal rst : STD_LOGIC := '1'; + signal clk_w : STD_LOGIC := '0'; + signal clk_r : STD_LOGIC := '0'; + signal we : STD_LOGIC := '0'; + signal re : STD_LOGIC := '0'; + signal din : unsigned (7 downto 0); + --Outputs + + signal dout : unsigned (7 downto 0); + signal fifo_full : STD_LOGIC; + signal fifo_empty : STD_LOGIC; + signal fifo_almost_full : STD_LOGIC; + signal fifo_almost_empty : STD_LOGIC; + + signal write_en : STD_LOGIC := '0'; + signal read_en : STD_LOGIC := '0'; + + signal ref_r : unsigned (7 downto 0); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: entity work.fifo_async + GENERIC MAP + ( + addr_width => ADDR_WIDTH, + data_width => DATA_WIDTH, + almost_full_thresh => 6, + almost_empty_thresh => 2 + ) + PORT MAP + ( + rst => rst, + clk_w => clk_w, + clk_r => clk_r, + we => we, + re => re, + data_w => din, + data_r => dout, + fifo_full => fifo_full, + fifo_empty => fifo_empty, + fifo_afull => fifo_almost_full, + fifo_aempty => fifo_almost_empty + + ); + + tb_clk_w : PROCESS + BEGIN + clk_w <= not clk_w; + wait for PERIOD_W/2; + END PROCESS; + + tb_clk_r : PROCESS + BEGIN + clk_r <= not clk_r; + wait for PERIOD_R/2; + END PROCESS; + + tb_write : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + wait for 5*PERIOD_W; + rst <= '0'; + wait for 7*PERIOD_W; + write_en <= '1'; + wait for 25*PERIOD_W; + write_en <= '0'; + wait for 7*PERIOD_W; + write_en <= '1'; + wait for 25*PERIOD_W; + write_en <= '0'; + wait for 7*PERIOD_W; + write_en <= '1'; + wait for 1*PERIOD_W; + write_en <= '0'; + wait for 1*PERIOD_W; + write_en <= '1'; + wait for 1*PERIOD_W; + write_en <= '0'; + wait for 3*PERIOD_W; + write_en <= '1'; + wait for 4*PERIOD_W; + write_en <= '0'; + wait for 17*PERIOD_W; + write_en <= '1'; + wait for 55*PERIOD_W; + write_en <= '0'; + wait for 1*PERIOD_W; + write_en <= '1'; + wait for 1*PERIOD_W; + write_en <= '0'; + wait for 3*PERIOD_W; + write_en <= '1'; + wait for 44*PERIOD_W; + write_en <= '0'; + + wait; + + END PROCESS; + + tb_read : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + wait for 25*PERIOD_R; + read_en <= '1'; + wait for 25*PERIOD_R; + read_en <= '0'; + wait for 25*PERIOD_R; + read_en <= '1'; + wait for 1*PERIOD_R; + read_en <= '0'; + wait for 5*PERIOD_R; + read_en <= '1'; + wait for 1*PERIOD_R; + read_en <= '0'; + wait for 5*PERIOD_R; + read_en <= '1'; + wait for 1*PERIOD_R; + read_en <= '0'; + wait for 5*PERIOD_R; + read_en <= '1'; + wait for 1*PERIOD_R; + read_en <= '0'; + wait for 5*PERIOD_R; + read_en <= '1'; + wait for 1*PERIOD_R; + read_en <= '0'; + wait for 5*PERIOD_R; + read_en <= '1'; + wait for 1*PERIOD_R; + read_en <= '0'; + wait for 5*PERIOD_R; + read_en <= '1'; + wait for 1*PERIOD_R; + read_en <= '0'; + wait for 7*PERIOD_R; + read_en <= '1'; + wait for 15*PERIOD_R; + read_en <= '0'; + wait; + + END PROCESS; + + we <= write_en and not fifo_full; + + tb_w : PROCESS(rst, clk_w) + BEGIN + + if rst = '1' then + din <= (others => '0'); + elsif rising_edge(clk_w) then + if we = '1' then + din <= din + 1; + end if; + end if; + + END PROCESS; + + re <= read_en and not fifo_empty; + + tb_r : PROCESS(rst, clk_r) + BEGIN + + if rst = '1' then + ref_r <= (others => '0'); + elsif rising_edge(clk_r) then + if re = '1' then + assert ref_r = dout report "FIFO read error!" severity failure; + ref_r <= ref_r + 1; + end if; + end if; + + END PROCESS; + +END behavior; \ No newline at end of file diff --git a/lib/FIFO/src/tb_fifo_sync.vhd b/lib/FIFO/src/tb_fifo_sync.vhd new file mode 100644 index 0000000..c25b260 --- /dev/null +++ b/lib/FIFO/src/tb_fifo_sync.vhd @@ -0,0 +1,206 @@ +------------------------------------------------------------------------- +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE STD.TEXTIO.ALL; + +-- LIBRARY WORK; +-- USE.YOURLIB.WHATELSE + +ENTITY tb_fifo_sync IS +END tb_fifo_sync; + +ARCHITECTURE behavior OF tb_fifo_sync IS + + --Constants + constant PERIOD : time := 10 ns; + constant ADDR_WIDTH : integer := 3; + constant DATA_WIDTH : integer := 8; + + --Inputs + signal rst : STD_LOGIC := '1'; + signal clk : STD_LOGIC := '0'; + signal we : STD_LOGIC := '0'; + signal re : STD_LOGIC := '0'; + signal din : unsigned (7 downto 0); + --Outputs + + signal dout : unsigned (7 downto 0); + signal fifo_full : STD_LOGIC; + signal fifo_empty : STD_LOGIC; + signal fifo_almost_full : STD_LOGIC; + signal fifo_almost_empty : STD_LOGIC; + + signal write_en : STD_LOGIC := '0'; + signal read_en : STD_LOGIC := '0'; + + signal ref_r : unsigned (7 downto 0) := (others => '0'); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: entity work.fifo_sync + GENERIC MAP + ( + data_width => DATA_WIDTH, + addr_width => ADDR_WIDTH, + almost_full_thresh => 6, + almost_empty_thresh => 2 + ) + PORT MAP + ( + rst => rst, + clk => clk, + we => we, + re => re, + data_w => din, + data_r => dout, + fifo_full => fifo_full, + fifo_empty => fifo_empty, + fifo_afull => fifo_almost_full, + fifo_aempty => fifo_almost_empty + + ); + + tb_clk : PROCESS + BEGIN + clk <= not clk; + wait for PERIOD/2; + END PROCESS; + + tb_write : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + wait for 5*PERIOD; + rst <= '0'; + wait for 7*PERIOD; + write_en <= '1'; + wait for 25*PERIOD; + write_en <= '0'; + wait for 7*PERIOD; + write_en <= '1'; + wait for 25*PERIOD; + write_en <= '0'; + wait for 7*PERIOD; + write_en <= '1'; + wait for 1*PERIOD; + write_en <= '0'; + wait for 1*PERIOD; + write_en <= '1'; + wait for 1*PERIOD; + write_en <= '0'; + wait for 3*PERIOD; + write_en <= '1'; + wait for 4*PERIOD; + write_en <= '0'; + wait for 17*PERIOD; + write_en <= '1'; + wait for 25*PERIOD; + write_en <= '0'; + + wait; + + END PROCESS; + + tb_read : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + wait for 25*PERIOD; + read_en <= '1'; + wait for 25*PERIOD; + read_en <= '0'; + wait for 25*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 7*PERIOD; + read_en <= '1'; + wait for 20*PERIOD; + read_en <= '0'; + + wait; + + END PROCESS; + + we <= write_en and not fifo_full; + + tb_w : PROCESS(rst, clk) + BEGIN + + if rst = '1' then + din <= (others => '0'); + elsif rising_edge(clk) then + if we = '1' then + din <= din + 1; + end if; + end if; + + END PROCESS; + + re <= read_en and not fifo_empty; + + tb_r : PROCESS(rst, clk) + BEGIN + + if rst = '1' then + ref_r <= (others => '0'); + elsif rising_edge(clk) then + if re = '1' then + assert ref_r = dout report "FIFO read error!" severity failure; + ref_r <= ref_r + 1; + end if; + end if; + + END PROCESS; + +END behavior; \ No newline at end of file