- renamed

Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@297 cc03376c-175c-47c8-b038-4cd826a8556b

lib/FIFO/src/async_fifo_ctrl.vhd

@@ -1,27 +1,25 @@
 -------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The call/return/data stack
-
+-- Project: FIFO, generic FIFOs written in VHDL
+-- Release 1
+--
 -- Copyright (C) 2007 J. Ahrensfeld
-
+--
 -- This library is free software; you can redistribute it and/or
 -- modify it under the terms of the GNU Lesser General Public
 -- License as published by the Free Software Foundation; either
 -- version 2.1 of the License, or (at your option) any later version.
-
+--
 -- This library is distributed in the hope that it will be useful,
 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 -- Lesser General Public License for more details.
-
+--
 -- You should have received a copy of the GNU Lesser General Public
 -- License along with this library; if not, write to the Free Software
 -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
+--
 -- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.2 2008-10-25 11:21:47 Jens Exp $
+--
 -----------------------------------------------------------------------
 
 library IEEE;
@@ -31,8 +29,9 @@ use IEEE.numeric_std.ALL;
 LIBRARY WORK;
 USE WORK.FIFO_CTRL_PKG.ALL;
 
-entity async_fifo_ctrl is
-	Generic (
+entity fifo_async_ctrl is
+	Generic 
+	(
 		addr_width : integer := 3;
 		almost_full_thresh : integer := 6;
 		almost_empty_thresh : integer := 2
@@ -51,9 +50,9 @@ entity async_fifo_ctrl is
 		fifo_afull			: out STD_LOGIC;
 		fifo_aempty			: out STD_LOGIC
 	);
-end async_fifo_ctrl;
+end fifo_async_ctrl;
 
-architecture Behavioral of async_fifo_ctrl is
+architecture Behavioral of fifo_async_ctrl is
 
 	signal gcnt_w		: unsigned (addr_width downto 0);
 	signal gcnt2_w		: unsigned (addr_width downto 0);
@@ -211,11 +210,13 @@ proc_status_almost_empty:
 	end process;
 
 inst_gray_counter_w : entity work.gray_counter
-	generic map (
+	generic map
+	(
 		width => addr_width+1,
 		init_value => 0
 		)
-	port map (
+	port map
+	(
 		rst			=> rst,
 		clk			=> clk_w,
 		ce			=> winc, 
@@ -226,11 +227,13 @@ inst_gray_counter_w : entity work.gray_counter
 	);
 
 inst_gray_counter_r : entity work.gray_counter
-	generic map (
+	generic map
+	(
 		width => addr_width+1,
 		init_value => 0
 		)
-	port map (
+	port map
+	(
 		rst			=> rst,
 		clk			=> clk_r,
 		ce			=> rinc,