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- minor changes to frontend

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- increased POWER_UP wait
- added reset delay

git-svn-id: http://moon:8086/svn/vhdl/trunk@1259 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-29 19:18:52 +00:00
parent ae98d5f2d3
commit b2c5bcb279
3 changed files with 15 additions and 8 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd
+11 -4
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@@ -73,6 +73,8 @@ architecture tech of sdram_phy is
signal locked : std_logic; signal locked : std_logic;
signal error : std_logic; signal error : std_logic;
signal reset_counter : unsigned(7 downto 0) := (others => '1');
signal reset : STD_LOGIC := '1';
type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
signal u_tag_pipe : u_tag_array_t; signal u_tag_pipe : u_tag_array_t;
@@ -109,12 +111,17 @@ inst_sdram_clk : entity work.sdram_clk
locked_out => locked -- DCM locked status locked_out => locked -- DCM locked status
); );
rst0_gen: rst0_gen:
process(locked, clk0) process(locked, clk0)
begin begin
if rst = '1' then if locked = '0' then
rst0 <= '1';
reset_counter <= (others => '1'); reset_counter <= (others => '1');
elsif rising_edge(clk0) then elsif rising_edge(clk0) then
if (reset_counter /= 0) then
reset_counter <= reset_counter - 1;
else
rst0 <= '0';
end if; end if;
end if; end if;
end process; end process;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
+2 -2
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@@ -47,7 +47,7 @@ package sdram_config is
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
constant ENABLE_PRE_ALL : std_logic := '1'; constant ENABLE_PRE_ALL : std_logic := '1';
constant ENABLE_AUTO_PRE : std_logic := '0'; constant ENABLE_AUTO_PRE : std_logic := '0';
constant LMR_BL_CURR : natural := LMR_BL2; constant LMR_BL_CURR : natural := LMR_BL1;
-- DDR-SDR TIMING constants ------------------------------------------------------------------ -- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
@@ -62,7 +62,7 @@ package sdram_config is
constant TRCD : real := 20.0; -- active to read or write delay [ns] constant TRCD : real := 20.0; -- active to read or write delay [ns]
constant TWR : real := 15.0; -- write recovery time [ns] constant TWR : real := 15.0; -- write recovery time [ns]
constant PWR_UP_WAIT : real := 1.0E3; -- [ns] constant PWR_UP_WAIT : real := 200.0E3; -- [ns]
subtype user_tag_t is unsigned(3 downto 0); subtype user_tag_t is unsigned(3 downto 0);
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd
+2 -2
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@@ -218,7 +218,7 @@ begin
addr_fifo_in <= "000" & ADDR_I(22 downto 2); addr_fifo_in <= "000" & ADDR_I(22 downto 2);
tag_fifo_in <= "000" & ADDR_I(2); tag_fifo_in <= "000" & ADDR_I(2);
u_cmd_we <= (not cat_fifo_empty) and (not u_busy); u_cmd_we <= (not cat_fifo_empty);
u_cmd <= cmd_fifo_out; u_cmd <= cmd_fifo_out;
u_addr <= addr_fifo_out; u_addr <= addr_fifo_out;
phy_in.wr_dm <= write_fifo_dm_out; phy_in.wr_dm <= write_fifo_dm_out;
@@ -226,7 +226,7 @@ begin
phy_in.wr_data <= write_fifo_data_out; phy_in.wr_data <= write_fifo_data_out;
write_fifo_re <= phy_out.wr_data_re and (not write_fifo_empty); write_fifo_re <= phy_out.wr_data_re and (not write_fifo_empty);
cat_fifo_re <= u_cmd_we; cat_fifo_re <= u_cmd_we and (not u_busy);
read_fifo_re <= (not read_fifo_empty) and MRDY_I; read_fifo_re <= (not read_fifo_empty) and MRDY_I;
read_fifo_we <= phy_out.rd_data_we; read_fifo_we <= phy_out.rd_data_we;
read_fifo_data_in <= phy_out.rd_data; read_fifo_data_in <= phy_out.rd_data;