- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1324 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,439 @@
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-- Test vectors for the synthesis test for the fixed point math package
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-- This test is designed to test fixed_synth and exercise much of the entity.
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-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
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-- --------------------------------------------------------------------
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-- modification history : Last Modified $Date: 2006-06-08 10:55:54-04 $
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-- Version $Id: test_fixed_synth.vhdl,v 1.1 2006-06-08 10:55:54-04 l435385 Exp $
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-- --------------------------------------------------------------------
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entity test_fixed_synth is
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generic (
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quiet : boolean := false); -- make the simulation quiet
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end entity test_fixed_synth;
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library ieee, ieee_proposed;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee_proposed.fixed_pkg.all;
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architecture testbench of test_fixed_synth is
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procedure report_error (
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constant errmes : in string; -- error message
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actual : in sfixed; -- data from algorithm
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constant expected : in sfixed) is -- reference data
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begin -- function report_error
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assert actual = expected
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report errmes & CR
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& "Actual: " & to_string(actual)
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& " (" & real'image(to_real(actual)) & ")" & CR
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& " /= " & to_string(expected)
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& " (" & real'image(to_real(expected)) & ")"
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severity error;
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return;
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end procedure report_error;
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-- Device under test. Note that all inputs and outputs are std_logic_vector.
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-- This entity can be use both pre and post synthesis.
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component fixed_synth is
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port (
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in1, in2 : in std_logic_vector (15 downto 0); -- inputs
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out1 : out std_logic_vector (15 downto 0); -- output
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cmd : in std_logic_vector (3 downto 0);
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clk, rst_n : in std_ulogic); -- clk and reset
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end component fixed_synth;
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constant clock_period : time := 500 ns; -- clock period
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subtype sfixed7 is sfixed (3 downto -3); -- 7 bit
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subtype sfixed16 is sfixed (7 downto -8); -- 16 bit
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signal stop_clock : boolean := false; -- stop the clock
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signal clk, rst_n : std_ulogic; -- clk and reset
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signal in1slv, in2slv, out1slv : std_logic_vector(15 downto 0);
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signal in1, in2 : sfixed16; -- inputs
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signal out1 : sfixed16; -- output
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signal cmd : std_logic_vector (3 downto 0); -- command string
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begin -- architecture testbench
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-- From fixed point to Std_logic_vector
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in1slv <= to_slv(in1);
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in2slv <= to_slv(in2);
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-- Std_logic_vector to fixed point.
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out1 <= to_sfixed(out1slv, out1'high, out1'low);
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DUT: fixed_synth
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port map (
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in1 => in1slv, -- [in std_logic_vector (15 downto 0)] inputs
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in2 => in2slv, -- [in std_logic_vector (15 downto 0)] inputs
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out1 => out1slv, -- [out std_logic_vector (15 downto 0)] output
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cmd => cmd, -- [in std_logic_vector (2 downto 0)]
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clk => clk, -- [in std_ulogic] clk and reset
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rst_n => rst_n); -- [in std_ulogic] clk and reset
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-- purpose: clock driver
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clkprc: process is
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begin -- process clkprc
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if (not stop_clock) then
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clk <= '0';
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wait for clock_period/2.0;
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clk <= '1';
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wait for clock_period/2.0;
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else
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wait;
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end if;
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end process clkprc;
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-- purpose: reset driver
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reset_proc: process is
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begin -- process reset_proc
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rst_n <= '0';
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wait for clock_period * 2.0;
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rst_n <= '1';
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wait;
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end process reset_proc;
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-- purpose: main test loop
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tester: process is
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begin -- process tester
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cmd <= "0000"; -- add mode
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in1 <= (others => '0');
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in2 <= (others => '0');
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wait for clock_period;
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wait for clock_period;
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wait for clock_period;
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wait for clock_period;
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in1 <= "0000011010000000"; -- 6.5
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in2 <= "0000001100000000"; -- 3
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wait for clock_period;
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cmd <= "0001"; -- subtract mode
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in1 <= "0000011010000000"; -- 6.5
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in2 <= "0000001100000000"; -- 3
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wait for clock_period;
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cmd <= "0010"; -- multiply mode
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in1 <= "0000011010000000"; -- 6.5
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in2 <= "0000001100000000"; -- 3
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wait for clock_period;
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cmd <= "0000"; -- add mode
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in1 <= "0000000010000000"; -- 0.5
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in2 <= "0000000010000000"; -- 0.5
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wait for clock_period;
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in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
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in2 <= "0000001100000000"; -- 3
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wait for clock_period;
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cmd <= "0011"; -- divide
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in1 <= "0000000010000000"; -- 0.5
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in2 <= "0000000010000000"; -- 0.5
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wait for clock_period;
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in1 <= to_sfixed (-0.5, sfixed16'high, sfixed16'low); -- -0.5
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in2 <= "0000000010000000"; -- 0.5
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wait for clock_period;
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cmd <= "0100"; -- unsigned add
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in1 <= "0000011010000000"; -- 6.5
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in2 <= "0000001100000000"; -- 3
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wait for clock_period;
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cmd <= "0101"; -- subtract mode
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in1 <= "0000011010000000"; -- 6.5
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in2 <= "0000001100000000"; -- 3
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wait for clock_period;
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cmd <= "0110"; -- multiply mode
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in1 <= "0000011010000000"; -- 6.5
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in2 <= "0000001100000000"; -- 3
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wait for clock_period;
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cmd <= "0100"; -- add mode
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in1 <= "0000000010000000"; -- 0.5
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in2 <= "0000000010000000"; -- 0.5
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wait for clock_period;
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in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
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in2 <= "0000001100000000"; -- 3
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wait for clock_period;
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cmd <= "0111"; -- divide
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in1 <= "0000000010000000"; -- 0.5
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in2 <= "0000000010000000"; -- 0.5
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wait for clock_period;
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in1 <= to_sfixed (6.5, sfixed16'high, sfixed16'low); -- 6.5
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in2 <= "0000000010000000"; -- 0.5
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wait for clock_period;
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-- resize
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cmd <= "1000";
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in1 <= to_sfixed (5.25, in1);
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in2 <= to_sfixed (-5.25, in2);
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wait for clock_period;
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in1 <= to_sfixed (21.125, in1);
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in2 <= to_sfixed (21.125, in2);
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wait for clock_period;
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in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
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cmd <= "1001"; -- SIGNED
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in1 <= to_sfixed (6.25, in1);
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wait for clock_period;
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in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
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cmd <= "1001"; -- UNSIGNED
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in1 <= to_sfixed (7.25, in1);
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wait for clock_period;
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in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
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cmd <= "1001"; -- SIGNED
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in1 <= to_sfixed (6.25, in1);
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wait for clock_period;
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in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
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cmd <= "1001"; -- UNSIGNED
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in1 <= to_sfixed (7.25, in1);
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wait for clock_period;
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cmd <= "1010";
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in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
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in1 <= to_sfixed (3, in1);
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wait for clock_period;
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cmd <= "1010";
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in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
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in1 <= to_sfixed (5, in1);
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wait for clock_period;
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cmd <= "1010";
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in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
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in1 <= to_sfixed (-5.5, in1);
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wait for clock_period;
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cmd <= "1010";
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in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
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in1 <= to_sfixed (7.25, in1);
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wait for clock_period;
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cmd <= "1010"; -- abs (mod)
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in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
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in1 <= to_sfixed (-42, in1);
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wait for clock_period;
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cmd <= "1011"; -- mod
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in1 <= to_sfixed (6.25, in1);
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in2 <= to_sfixed (6, in2);
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wait for clock_period;
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cmd <= "1100"; -- REM
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in1 <= to_sfixed (6.25, in1);
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in2 <= to_sfixed (6, in2);
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wait for clock_period;
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cmd <= "1101"; -- srl
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in1 <= to_sfixed (5.25, in1);
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in2 <= to_sfixed (-1, in2);
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wait for clock_period;
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cmd <= "1110"; -- sra
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in1 <= to_sfixed (-7.25, in1);
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in2 <= to_sfixed (1, in2);
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wait for clock_period;
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cmd <= "1111"; -- compare
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in1 <= to_sfixed (42, in1);
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in2 <= to_sfixed (42, in1);
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wait for clock_period;
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in1 <= to_sfixed (45, in1);
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in2 <= to_sfixed (90, in1);
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wait for clock_period;
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in1 <= to_sfixed (3.125, in1);
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in2 <= (others => '0');
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wait for clock_period;
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in1 <= "0110111110101111";
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in2 <= "1111111111111111";
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wait for clock_period;
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in1 <= (others => '0');
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in2 <= (others => '0');
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wait for clock_period;
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in1 <= "0000111000000000";
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in2 <= "0000111000000000";
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wait for clock_period;
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in1 <= (others => '1');
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in2 <= (others => '1');
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wait for clock_period;
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wait for clock_period;
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wait for clock_period;
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cmd <= "0000"; -- add mode
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in1 <= (others => '0');
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in2 <= (others => '0');
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wait for clock_period;
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wait for clock_period;
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wait for clock_period;
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wait for clock_period;
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wait for clock_period;
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wait for clock_period;
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wait for clock_period;
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wait for clock_period;
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wait;
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end process tester;
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-- purpose: check the output of the tester
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-- type : combinational
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-- inputs :
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-- outputs:
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checktest: process is
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constant fxzero : sfixed16 := (others => '0'); -- zero
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variable chks16 : sfixed16; -- variable
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variable sm1, sm2 : sfixed7; -- small fixed point
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begin -- process checktest
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wait for clock_period/2.0;
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wait for clock_period;
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wait for clock_period;
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waitloop: while (out1 = fxzero) loop
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wait for clock_period;
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end loop waitloop;
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chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
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report_error ( "3.0 + 6.5 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
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report_error ( "6.5 - 3.0 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
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report_error ( "6.5 * 3.0 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
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report_error ( "0.5 + 0.5 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
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report_error ( "3.14 + 3 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := "0000000100000000";
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report_error ( "0.5/0.5 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed (-1, sfixed16'high, sfixed16'low);
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report_error ( "-0.5/0.5 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
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report_error ( "3.0 + 6.5 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
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report_error ( "6.5 - 3.0 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
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report_error ( "6.5 * 3.0 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
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report_error ( "0.5 + 0.5 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
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report_error ( "3.14 + 3 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := "0000000100000000";
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report_error ( "0.5/0.5 error",
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out1,
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chks16);
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wait for clock_period;
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chks16 := to_sfixed (13, sfixed16'high, sfixed16'low);
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report_error ( "6.5/0.5 error",
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out1,
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chks16);
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wait for clock_period;
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-- resize test
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sm1 := out1 (7 downto 1);
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sm2 := to_sfixed (5.25, sm2);
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report_error ( "resize 1 error", sm1, sm2);
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sm1 := out1 (-1 downto -7);
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sm2 := to_sfixed (-5.25, sm2);
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report_error ( "resize 2 error", sm1, sm2);
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wait for clock_period;
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sm1 := out1 (7 downto 1);
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sm2 := "0101001"; -- wrapped
|
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-- sm2 := to_sfixed (21.125, sm2, 0, false, false); -- wrap, no round
|
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report_error ( "resize 1 error", sm1, sm2);
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sm1 := out1 (-1 downto -7);
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sm2 := "0111111"; -- saturate
|
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report_error ( "resize 2 error", sm1, sm2);
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wait for clock_period;
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-- to_signed and back
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report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
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wait for clock_period;
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-- to_unsigned and back
|
||||
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
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wait for clock_period;
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-- to_integer and back
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report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
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wait for clock_period;
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-- to_integer(ufixed) and back
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report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
|
||||
wait for clock_period;
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report_error ("1/3", out1, to_sfixed (1.0/3.0, out1'high, -7));
|
||||
wait for clock_period;
|
||||
report_error ("unsigned 1/5", out1, to_sfixed (1.0/5.0, out1));
|
||||
wait for clock_period;
|
||||
report_error ("abs (-5.5)", out1, to_sfixed (5.5, out1));
|
||||
wait for clock_period;
|
||||
report_error ("-7.25", out1, to_sfixed (-7.25, out1));
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wait for clock_period;
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report_error ("abs(-42)", out1, to_sfixed (42, out1));
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wait for clock_period;
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report_error ("6.25 mod 6", out1, to_sfixed (0.25, out1));
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wait for clock_period;
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report_error ("6.25 rem 6", out1, to_sfixed (0.25, out1));
|
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wait for clock_period;
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||||
chks16 := "0000101010000000";
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report_error ("5.25 srl -1", out1, chks16);
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wait for clock_period;
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chks16 := "1111110001100000";
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||||
report_error ("-7.25 sra 1", out1, chks16);
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||||
wait for clock_period;
|
||||
-- 7654321012345678
|
||||
chks16 := "0111000000110001";
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||||
assert (std_match (out1, chks16))
|
||||
report "42=42 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
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||||
wait for clock_period;
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||||
chks16 := "------0001010110";
|
||||
assert (std_match (out1, chks16))
|
||||
report "45=90 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
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||||
wait for clock_period;
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||||
chks16 := "------1010101010";
|
||||
assert (std_match (out1, chks16))
|
||||
report "3.125=0 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
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||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
-- 7654321012345678
|
||||
chks16 := "0--1010000101010";
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||||
assert (std_match (out1, chks16))
|
||||
report "pattern1 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
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||||
-- 7654321012345678
|
||||
chks16 := "0001100000110001";
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||||
assert (std_match (out1, chks16))
|
||||
report "zero = zero " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
-- 7654321012345678
|
||||
chks16 := "1111000000110001";
|
||||
assert (std_match (out1, chks16))
|
||||
report "pattern2 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
-- 7654321012345678
|
||||
chks16 := "0111000000110001";
|
||||
assert (std_match (out1, chks16))
|
||||
report "-1 = -1 " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
assert (false) report "Testing complete" severity note;
|
||||
stop_clock <= true;
|
||||
wait;
|
||||
end process checktest;
|
||||
end architecture testbench;
|
||||
Reference in New Issue
Block a user