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[MIPS]

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- removed propagation delays from core source
- default 1kWord I/D-Cache

git-svn-id: http://moon:8086/svn/vhdl/trunk@1081 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-14 16:13:08 +00:00
parent ff20480866
commit b06aab0b3c
9 changed files with 44 additions and 44 deletions
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lib/CPUs/MIPS/sim/ModelSim SE .lnk
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lib/CPUs/MIPS/src/core/mips_alu.vhd
+8 -8
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@@ -56,11 +56,11 @@ architecture Behavioral of alu is
--------------------------------------------------------------------------
begin
eq <= '1' when op1_in = op2_in else '0' after 3 ns;
eq <= '1' when op1_in = op2_in else '0';
sa <= op1_in(op1_in'left);
sb <= op2_in(op2_in'left);
sr <= sum_res(sum_res'left);
z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns;
z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0';
flags.uvf <= (not ctrl.add) and ((sa and (not sb) and (not sr)) or ((not sa) and sb and sr));
flags.ovf <= ctrl.add and ((sa and sb and (not sr)) or ((not sa) and (not sb) and sr));
@@ -80,7 +80,7 @@ proc_op_and:
x1 := op1_in;
x2 := op2_in;
and_res <= (x1 and x2) after 1 ns;
and_res <= (x1 and x2);
end process;
@@ -92,7 +92,7 @@ proc_proc_xor:
x1 := op1_in;
x2 := op2_in;
xor_res <= (x1 xor x2) after 2 ns;
xor_res <= (x1 xor x2);
end process;
@@ -104,7 +104,7 @@ proc_proc_nor:
x1 := op1_in;
x2 := op2_in;
nor_res <= (x1 nor x2) after 1 ns;
nor_res <= (x1 nor x2);
end process;
@@ -116,7 +116,7 @@ proc_proc_or:
x1 := op1_in;
x2 := op2_in;
or_res <= (x1 or x2) after 1 ns;
or_res <= (x1 or x2);
end process;
@@ -175,8 +175,8 @@ alu_addsub:
sum := op1 + op2;
-- Form sum + carry
sum_res <= unsigned(sum(data_width downto 1)) after 4 ns;
c <= sum(sum'left) after 4 ns;
sum_res <= unsigned(sum(data_width downto 1));
c <= sum(sum'left);
end process;
lib/CPUs/MIPS/src/core/mips_bcu.vhd
+2 -2
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@@ -45,8 +45,8 @@ architecture Behavioral of bcu is
--------------------------------------------------------------------------
begin
flags.eq <= '1' when op1_in = op2_in else '0' after 3 ns;
flags.ltz <= op1_in(op1_in'left) after 1 ns;
flags.eq <= '1' when op1_in = op2_in else '0';
flags.ltz <= op1_in(op1_in'left);
--------------------------------------------------------------------------
end Behavioral;
lib/CPUs/MIPS/src/core/mips_biu.vhd
+2 -2
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@@ -231,9 +231,9 @@ read_cyc_register:
SEL_O <= bout_fifo_sel_out;
WE_O <= bout_fifo_we_out;
cpu_imem_rdy <= not icache_busy after 4.5 ns;
cpu_imem_rdy <= not icache_busy;
busy <= CYC_O_dmem_rd or dcache_busy or (write_fifo_full);
cpu_dmem_rdy <= not busy after 4.5 ns;
cpu_dmem_rdy <= not busy;
inst_icache : icache
GENERIC MAP
lib/CPUs/MIPS/src/core/mips_cop.vhd
+1 -1
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@@ -455,7 +455,7 @@ cop_register_read:
end case;
dout <= reg after 2 ns;
dout <= reg;
end process;
lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+25 -25
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@@ -256,9 +256,9 @@ proc_stage_pc:
process(pc)
begin
if pc.branch_take = '1' then
pc.curr <= pc.pc_branch after 2 ns;
pc.curr <= pc.pc_branch;
else
pc.curr <= pc.nxt after 2 ns;
pc.curr <= pc.nxt;
end if;
end process;
@@ -373,12 +373,12 @@ proc_stage_hdu:
raw_b_MEM := reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1';
raw_b_WB := reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1';
hdu.alu_fwd_a_ex <= raw_a_EX after 1 ns;
hdu.alu_fwd_a_mem <= raw_a_MEM after 1 ns;
hdu.alu_fwd_a_wb <= raw_a_WB after 1 ns;
hdu.alu_fwd_b_ex <= raw_b_EX after 1 ns;
hdu.alu_fwd_b_mem <= raw_b_MEM after 1 ns;
hdu.alu_fwd_b_wb <= raw_b_WB after 1 ns;
hdu.alu_fwd_a_ex <= raw_a_EX;
hdu.alu_fwd_a_mem <= raw_a_MEM;
hdu.alu_fwd_a_wb <= raw_a_WB;
hdu.alu_fwd_b_ex <= raw_b_EX;
hdu.alu_fwd_b_mem <= raw_b_MEM;
hdu.alu_fwd_b_wb <= raw_b_WB;
end process;
@@ -397,9 +397,9 @@ proc_stage_fwd_a:
for i in 0 to 31 loop
if data(i) = '1' then
ID_stage.reg_a(i) <= '1' after 2 ns;
ID_stage.reg_a(i) <= '1';
else
ID_stage.reg_a(i) <= '0' after 2 ns;
ID_stage.reg_a(i) <= '0';
end if;
end loop;
@@ -420,9 +420,9 @@ proc_stage_fwd_b:
for i in 0 to 31 loop
if data(i) = '1' then
ID_stage.reg_b(i) <= '1' after 2 ns;
ID_stage.reg_b(i) <= '1';
else
ID_stage.reg_b(i) <= '0' after 2 ns;
ID_stage.reg_b(i) <= '0';
end if;
end loop;
@@ -449,7 +449,7 @@ proc_imm_mux:
end case;
ID_stage.imm <= data after 2 ns;
ID_stage.imm <= data;
end process;
@@ -586,9 +586,9 @@ proc_stage_DMEM_ADDR:
end if;
end process;
dmem_src <= cop_din when EX_stage.ctrl.cop_instr_en = '1' else EX_stage.reg_b;
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns;
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp);
dmem_we <= EX_stage.ctrl.dmem_we;
dmem_dout <= store_shift(dmem_src, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
dmem_dout <= store_shift(dmem_src, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp);
dmem_addr <= EX_stage.va;
EX_stage.events <= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
EX_stage.exc <= event_is_active(EX_stage.events);
@@ -608,19 +608,19 @@ proc_wptr_mux:
reg_wptr := extract_rt(EX_stage.IR);
end case;
EX_stage.wreg_we <= EX_stage.reg_write after 1 ns;
EX_stage.wreg_we <= EX_stage.reg_write;
if reg_wptr = "00000" then
EX_stage.wreg_we <= '0' after 1 ns;
EX_stage.wreg_we <= '0';
end if;
EX_stage.reg_wptr <= reg_wptr after 1 ns;
EX_stage.reg_wptr <= reg_wptr;
case EX_stage.ctrl.wptr_srcsel is
when wptr_src_imm =>
EX_stage.reg_wptr <= reg_wptr after 1 ns;
EX_stage.reg_wptr <= reg_wptr;
when wptr_src_const =>
EX_stage.reg_wptr <= to_unsigned(31, reg_ptr_t'length) after 1 ns;
EX_stage.wreg_we <= '1' after 1 ns;
EX_stage.reg_wptr <= to_unsigned(31, reg_ptr_t'length);
EX_stage.wreg_we <= '1';
when others => null;
end case;
@@ -685,11 +685,11 @@ shifter_sa_mux:
end case;
data_inv := not data + 1;
if ID_stage.ctrl.alu.shift_right = '0' then
EX_stage.shift_ctrl.shamt_rnd <= data_inv after 2 ns;
EX_stage.shift_ctrl.shamt_rnd <= data_inv;
else
EX_stage.shift_ctrl.shamt_rnd <= data after 2 ns;
EX_stage.shift_ctrl.shamt_rnd <= data;
end if;
EX_stage.shift_ctrl.shamt_nrm <= data after 1 ns;
EX_stage.shift_ctrl.shamt_nrm <= data;
EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right;
EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith;
end if;
@@ -813,7 +813,7 @@ proc_stage_MEM_mux:
data(31 downto 24) := temp2(31 downto 24);
end if;
end if;
MEM_stage.data <= data after 1 ns;
MEM_stage.data <= data;
end process;
lib/CPUs/MIPS/src/core/mips_reg.vhd
+3 -3
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@@ -55,6 +55,9 @@ architecture Behavioral of reg_dual is
begin
dout_a <= reg_mem(to_integer(rptr_a));
dout_b <= reg_mem(to_integer(rptr_b));
reg_in:
process(clk_w)
begin
@@ -65,8 +68,5 @@ reg_in:
end if;
end process;
dout_a <= reg_mem(to_integer(rptr_a)) after 2 ns;
dout_b <= reg_mem(to_integer(rptr_b)) after 2 ns;
end Behavioral;
lib/CPUs/MIPS/src/core/mips_shifter.vhd
+1 -1
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@@ -110,7 +110,7 @@ proc_fill_neu:
end if;
end process;
dout <= dout_filled after 5 ns;
dout <= dout_filled;
--------------------------------------------------------------------------
end Behavioral;
lib/CPUs/MIPS/src/core/mips_top.vhd
+2 -2
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@@ -31,9 +31,9 @@ use work.mips_types.all;
entity mips_top is
Generic
(
icache_size : natural := 8192; -- words
icache_size : natural := 1024; -- words
icache_line : natural := 8; -- words
dcache_size : natural := 4096; -- words
dcache_size : natural := 1024; -- words
dcache_line : natural := 8 -- words
);
Port