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This commit was manufactured by cvs2svn to create tag 'MIPS_R12'.

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git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R12@934 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2011-07-24 08:18:46 +00:00
parent faa81b57e9
commit aef784643a
396 changed files with 4562 additions and 83217 deletions
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projects/mips_sys/ise101/mips_sys/mips_sys.par
-201
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@@ -1,201 +0,0 @@
Release 10.1.03 par K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
JUPITER:: Tue Mar 09 13:07:50 2010
par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
mips_sys.pcf
Constraints file: mips_sys.pcf.
Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE.
"mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
The STEPPING level for this design is ES.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.68 2008-07-25".
Device Utilization Summary:
Number of BSCANs 1 out of 4 25%
Number of BUFGs 12 out of 32 37%
Number of DCM_ADVs 4 out of 8 50%
Number of ILOGICs 99 out of 448 22%
Number of External IOBs 226 out of 448 50%
Number of LOCed IOBs 226 out of 226 100%
Number of OLOGICs 182 out of 448 40%
Number of RAMB16s 51 out of 192 26%
Number of Slices 5907 out of 15360 38%
Number of SLICEMs 543 out of 7680 7%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 14 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting Router
Phase 1: 47928 unrouted; REAL time: 16 secs
Phase 2: 40960 unrouted; REAL time: 17 secs
Phase 3: 15655 unrouted; REAL time: 24 secs
Phase 4: 15655 unrouted; (245197) REAL time: 24 secs
Phase 5: 16281 unrouted; (4341) REAL time: 27 secs
Phase 6: 16339 unrouted; (710) REAL time: 28 secs
Phase 7: 0 unrouted; (9891) REAL time: 53 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 8: 0 unrouted; (9891) REAL time: 1 mins 4 secs
Phase 9: 0 unrouted; (5549) REAL time: 1 mins 14 secs
Phase 10: 0 unrouted; (5549) REAL time: 1 mins 21 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 11: 0 unrouted; (5549) REAL time: 2 mins 23 secs
Phase 12: 0 unrouted; (1304) REAL time: 2 mins 58 secs
Phase 13: 0 unrouted; (1304) REAL time: 3 mins 2 secs
Phase 14: 0 unrouted; (1304) REAL time: 3 mins 7 secs
Total REAL time to Router completion: 3 mins 9 secs
Total CPU time to Router completion: 3 mins 3 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| cpu_clk |BUFGCTRL_X0Y12| No | 1610 | 0.400 | 4.025 |
+---------------------+--------------+------+------+------------+-------------+
| CLK_O | BUFGCTRL_X0Y2| No | 2256 | 0.541 | 3.930 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_clk1 | BUFGCTRL_X0Y0| No | 76 | 0.190 | 3.686 |
+---------------------+--------------+------+------+------------+-------------+
| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.408 | 3.881 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk0 |BUFGCTRL_X0Y31| No | 227 | 0.492 | 3.933 |
+---------------------+--------------+------+------+------------+-------------+
|sys_ac97_bit_clk_IBU | | | | | |
| F | BUFGCTRL_X0Y8| No | 251 | 0.428 | 3.823 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 55 | 0.205 | 3.675 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270 |BUFGCTRL_X0Y16| No | 68 | 0.158 | 3.932 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.044 | 3.631 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 1304
WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and select
the "Timing Improvement Wizard" link for suggestions to correct each problem.
Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
ensure the best options are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
* TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | -0.293ns| 10.193ns| 9| 1107
HIGH 50% | HOLD | 0.365ns| | 0| 0
------------------------------------------------------------------------------------------------------
* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.197ns| 10.294ns| 1| 197
ns HIGH 50% | HOLD | 0.346ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.170ns| 7.330ns| 0| 0
7.5 ns HIGH 50% | HOLD | 0.513ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.386ns| 7.614ns| 0| 0
s HIGH 50% | HOLD | 0.514ns| | 0| 0
------------------------------------------------------------------------------------------------------
NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 36.650ns| 6.700ns| 0| 0
ns HIGH 50% | HOLD | 0.518ns| | 0| 0
------------------------------------------------------------------------------------------------------
TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 74.716ns| 5.284ns| 0| 0
ns HIGH 50% | HOLD | 0.802ns| | 0| 0
------------------------------------------------------------------------------------------------------
PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.594ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.138ns| N/A| 0
------------------------------------------------------------------------------------------------------
2 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 3 mins 18 secs
Total CPU time to PAR completion: 3 mins 9 secs
Peak Memory Usage: 428 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 10 errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 1
Writing design to file mips_sys.ncd
PAR done!
projects/mips_sys/ise101/mips_sys/mips_sys.prj
+1
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@@ -15,6 +15,7 @@ vhdl work "../../../../lib/uart/kcuart_rx.vhd"
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
projects/mips_sys/ise101/mips_sys/mips_sys.syr
-5227
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File diff suppressed because it is too large Load Diff
projects/mips_sys/ise101/mips_sys/mips_sys.twr
-1177
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File diff suppressed because it is too large Load Diff
projects/mips_sys/ise101/mips_sys/mips_sys.ut
-33
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@@ -1,33 +0,0 @@
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g InitPin:Pullup
-g CsPin:Pullup
-g DinPin:Pullup
-g BusyPin:Pullup
-g RdWrPin:Pullup
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCIUpdateMode:AsRequired
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Match_cycle:Auto
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
projects/mips_sys/ise101/mips_sys/mips_sys.xst
-62
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@@ -1,62 +0,0 @@
set -tmpdir "W:/vhdl/projects/mips_sys/ise101/mips_sys/xst/projnav.tmp"
set -xsthdpdir "W:/vhdl/projects/mips_sys/ise101/mips_sys/xst"
run
-ifn mips_sys.prj
-ifmt mixed
-ofn mips_sys
-ofmt NGC
-p xc4vsx35-10-ff668
-top mips_sys
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso mips_sys.lso
-keep_hierarchy NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing NO
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing Yes
-move_first_stage YES
-move_last_stage YES
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob true
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp
-1792
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File diff suppressed because it is too large Load Diff
projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
+1
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@@ -15,6 +15,7 @@ vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
-77
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@@ -31,10 +31,6 @@ NET "vga_clk" TNM_NET = "vga_clk";
TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %;
TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
NET "cpu_clk" TNM_NET = "cpu_clk";
TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
#TIMESPEC "TS_unrelate_CPU" = FROM sys_clk TO cpu_clk TIG;
NET "sys_clk_in" LOC = "AE14";
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET "sys_rst_n_in" LOC = "D6";
@@ -53,16 +49,6 @@ NET "RST_O" TIG;
#INST inst_clockgen/inst_DCM_BASE_0 LOC = DCM_ADV_X0Y4;
#INST inst_clockgen/inst_DCM_BASE_1 LOC = DCM_ADV_X0Y3;
# ---------------------------------------------------------------------------------
# Floor planning
# ---------------------------------------------------------------------------------
#INST "inst_vga_frontend" AREA_GROUP = "AG_inst_vga_frontend" ;
#AREA_GROUP "AG_inst_vga_frontend" RANGE = SLICE_X8Y191:SLICE_X30Y141 ;
#AREA_GROUP "AG_inst_vga_frontend" RANGE = RAMB16_X0Y18:RAMB16_X0Y23, RAMB16_X1Y18:RAMB16_X1Y23, RAMB16_X2Y18:RAMB16_X2Y23 ;
#INST "inst_sdram_ctrl_frontend_wb" AREA_GROUP = "AG_inst_sdram_ctrl_frontend_wb" ;
#AREA_GROUP "AG_inst_sdram_ctrl_frontend_wb" RANGE = SLICE_X0Y191:SLICE_X7Y141 ;
INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
# GOOD 1
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
@@ -80,13 +66,6 @@ INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ;
AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
# TEMP 4
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y54:SLICE_X39Y0 ;
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
# TEMP 4.1
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y55:SLICE_X39Y0 ;
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
////////////////////////////////////////////////////////////////////////////
// Misc Board Signals
////////////////////////////////////////////////////////////////////////////
@@ -571,59 +550,3 @@ NET sys_ps2_1_data SLEW = SLOW;
NET sys_ps2_1_data DRIVE = 2;
NET sys_ps2_1_data TIG;
#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for Ethernet PHY
#------------------------------------------------------------------------------
# MDC
Net sys_phy_mdc LOC = D1;
Net sys_phy_mdc IOSTANDARD = LVCMOS25;
# MDIO
Net sys_phy_mdio LOC = G4;
Net sys_phy_mdio IOSTANDARD = LVCMOS25;
# /RST
Net sys_phy_rstn LOC = D10;
Net sys_phy_rstn TIG;
# INT
Net sys_phy_int LOC = H4;
Net sys_phy_int TIG;
#### Module Ethernet_MAC constraints
NET "sys_phy_tx_clk" TNM_NET = "phy_tx_clk";
TIMESPEC "TS_phy_tx_clk" = PERIOD "phy_tx_clk" 8.0 ns HIGH 50 %;
NET "sys_phy_rx_clk" TNM_NET = "phy_rx_clk";
TIMESPEC "TS_phy_rx_clk" = PERIOD "phy_rx_clk" 8.0 ns HIGH 50 %;
Net sys_phy_crs LOC = D5;
Net sys_phy_col LOC = E3;
Net sys_phy_tx_clk LOC=C15;
Net sys_phy_tx_en LOC = F4;
Net sys_phy_tx_er LOC=F3;
Net sys_phy_gtx_clk LOC=G10;
Net sys_phy_rx_clk LOC=B15;
Net sys_phy_rx_dv LOC=A9;
Net sys_phy_rx_er LOC=B9;
Net sys_phy_tx<0> LOC=H1;
Net sys_phy_tx<1> LOC=H2;
Net sys_phy_tx<2> LOC=H3;
Net sys_phy_tx<3> LOC=G1;
Net sys_phy_tx<4> LOC=G2;
Net sys_phy_tx<5> LOC=H5;
Net sys_phy_tx<6> LOC=H6;
Net sys_phy_tx<7> LOC=G3;
Net sys_phy_rx<0> LOC=F1;
Net sys_phy_rx<1> LOC=E1;
Net sys_phy_rx<2> LOC=D4;
Net sys_phy_rx<3> LOC=C4;
Net sys_phy_rx<4> LOC=B4;
Net sys_phy_rx<5> LOC=A4;
Net sys_phy_rx<6> LOC=B3;
Net sys_phy_rx<7> LOC=A3;
projects/mips_sys/sim/tb_mips_sys.fdo
+2 -10
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@@ -81,6 +81,7 @@ vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
# SDRAM
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
@@ -92,15 +93,6 @@ vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
# Ethernet MAC
vcom -explicit -93 "../../../lib/emac/src/emac_types.vhd"
vcom -explicit -93 "../../../lib/emac/src/piso.vhd"
vcom -explicit -93 "../../../lib/emac/src/sipo.vhd"
vcom -explicit -93 "../../../lib/emac/src/crc32.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd"
# Clock Generator
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
@@ -113,4 +105,4 @@ do {tb_mips_sys.wdo}
view wave
view structure
view signals
run 10 ms
run 50ms
projects/mips_sys/sim/tb_mips_sys.wdo
+16 -232
View File
@@ -9,21 +9,6 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
add wave -noupdate -format Literal /tb_mips_sys/dip
add wave -noupdate -format Literal /tb_mips_sys/btn
add wave -noupdate -format Literal /tb_mips_sys/led
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int
add wave -noupdate -format Logic /tb_mips_sys/mdi_rx_clk
add wave -noupdate -format Logic /tb_mips_sys/mdi_rx_dv
add wave -noupdate -format Logic /tb_mips_sys/mdi_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/mdi_rx
add wave -noupdate -format Logic /tb_mips_sys/mdi_tx_clk
add wave -noupdate -format Logic /tb_mips_sys/mdi_tx_en
add wave -noupdate -format Logic /tb_mips_sys/mdi_tx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/mdi_tx
add wave -noupdate -format Logic /tb_mips_sys/mdi_gtx_clk
add wave -noupdate -format Logic /tb_mips_sys/mdi_crs
add wave -noupdate -format Logic /tb_mips_sys/mdi_col
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data
add wave -noupdate -format Logic /tb_mips_sys/sys_rx
@@ -59,91 +44,18 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -divider {Clock Gen}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Logic /tb_mips_sys/uut/sdram_clk0
add wave -noupdate -format Logic /tb_mips_sys/uut/sdram_clk270
add wave -noupdate -format Logic /tb_mips_sys/uut/sdram_clk270var
add wave -noupdate -format Logic /tb_mips_sys/uut/vga_clk
add wave -noupdate -format Logic /tb_mips_sys/uut/dcm_lock
add wave -noupdate -divider Arbiter
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
add wave -noupdate -divider {Ethernet MAC}
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mdi_rx_clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mdi_rx_dv
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mdi_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/mdi_rx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mdi_tx_clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mdi_tx_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mdi_tx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/mdi_tx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mdi_gtx_clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mdi_crs
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mdi_col
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/tx_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/tx_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_fifo_empty
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/rx_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/rx_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_trig
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_trig
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_err
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/tx_size
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/rx_size
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/tx_counter
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/rx_counter
add wave -noupdate -divider AC97
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
@@ -202,23 +114,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
add wave -noupdate -divider BUI
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/read_cycle
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/ack
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/dat
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bus_idle
add wave -noupdate -divider USB
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
@@ -270,16 +165,16 @@ add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
add wave -noupdate -divider {CPU DMEM}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
@@ -304,124 +199,13 @@ add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
add wave -noupdate -divider I-Cache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/dat_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cyc_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ctrl
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_busy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/s
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/sn
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_index_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_reg_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out_inv
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/data_ram_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_ram_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rst
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_all
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_req
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_cache_index
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_word_index
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
add wave -noupdate -divider D-Cache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/srdy_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/mrdy_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/dat_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cyc_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ctrl
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_busy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/s
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/sn
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit_inv
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_index_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_reg_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_data_reg
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we2
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_din
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rst
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_all
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_req
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/hit_cache_index
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_hit_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/instant_raw
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_word_index
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {7817800000 ps} 0} {{Cursor 100} {98503600 ps} 0} {{Cursor 3} {12889952362 ps} 0}
WaveRestoreCursors {{Cursor 2} {1804093493 ps} 0} {{Cursor 100} {853399231 ps} 0}
configure wave -namecolwidth 187
configure wave -valuecolwidth 64
configure wave -justifyvalue left
@@ -435,4 +219,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {3858715392 ps} {10323225506 ps}
WaveRestoreZoom {0 ps} {3268461 ns}
projects/mips_sys/src/async_defs_sim.vhd
+28 -28
View File
@@ -31,38 +31,38 @@ package async_defs is
constant ts_flash : async_timespec_t :=
(
T_leadin => 10.0,
T_pulse_rd => 120.0,
T_pulse_wr => 70.0,
T_leadout => 10.0,
T_release => 40.0,
T_pulse_rst => 80.0,
T_pulse_page_rd => 30.0,
can_page_rd => true,
nbits_page_rd => 4,
pol_cs => '1',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
ncyc_leadin => 1,
ncyc_pulse_rd => 12,
ncyc_pulse_wr => 7,
ncyc_leadout => 1,
ncyc_release => 4,
ncyc_pulse_rst => 8,
can_page_rd => true,
nbits_page_rd => 4,
ncyc_pulse_page_rd => 3,
pol_cs => '1',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
);
constant ts_usb : async_timespec_t :=
(
T_leadin => 10.0,
T_pulse_rd => 60.0,
T_pulse_wr => 60.0,
T_leadout => 10.0,
T_release => 80.0,
T_pulse_rst => 80.0,
T_pulse_page_rd => 00.0,
can_page_rd => false,
nbits_page_rd => 0,
pol_cs => '0',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
ncyc_leadin => 1,
ncyc_pulse_rd => 6,
ncyc_pulse_wr => 6,
ncyc_leadout => 1,
ncyc_release => 8,
ncyc_pulse_rst => 8,
can_page_rd => false,
nbits_page_rd => 0,
ncyc_pulse_page_rd => 0,
pol_cs => '0',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
);
----------------------------------------------------------------------------------------------
projects/mips_sys/src/bootloader.ROM.vhd
+1079 -1079
View File
File diff suppressed because it is too large Load Diff
projects/mips_sys/src/bootloader.ROM_ld.vhd
+1079 -1079
View File
File diff suppressed because it is too large Load Diff
projects/mips_sys/src/clockgen_virtex4.vhd
+144 -197
View File
@@ -33,74 +33,102 @@ use UNISIM.vcomponents.all;
entity clockgen is
generic
(
clk_in_freq : real := 100.0;
vga_clk_out_freq : real := 100.0;
sys_clk_out_freq : real := 100.0;
sdr0_clk_out_phaseshift : integer := 0;
sdr1_clk_out_phaseshift : integer := 0
clk_in_freq_hz : integer := 100E6;
vga_clk_out_freq_hz : integer := 0;
sdr_clk0_out_phaseshift : integer := 0;
sdr_clk1_out_phaseshift : integer := 0
);
port
(
-- Clocks and Reset
rst_in : in std_logic; -- external async reset, low active
rst : in std_logic; -- external async reset, low active
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
sys_clk_out : out std_logic;
cpu_clk_out : out std_logic;
vga_clk_out : out std_logic;
sdr0_clk_fb_in : in std_logic; -- feedback clock
sdr0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0°
sdr0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270°
sdr1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys_rst_out : out std_logic -- DCM locked status
sdr_clk0_fb_in : in std_logic; -- feedback clock
sdr_clk0_0_out : out std_logic; -- System clock #0, dcm#0 output 0°
sdr_clk0_270_out : out std_logic; -- System clock #0, dcm#0 output 270°
sdr_clk1_0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr_clk1_270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out : out std_logic; -- DCM locked status
error_out : out std_logic -- indicates DCM Errors
);
end;
architecture tech of clockgen is
signal locked : unsigned(2 downto 0);
signal dcm_rst : unsigned(2 downto 0);
signal vga_clk0 : std_logic;
signal vga_clkfx : std_logic;
signal vga_clk0_bufg : std_logic;
signal sys_clk0 : std_logic;
signal sys_clkfx : std_logic;
signal sys_clk0_bufg : std_logic;
signal sys_clkfx_bufg : std_logic;
signal sdr0_clk0 : std_logic;
signal sdr0_clk270 : std_logic;
signal sdr1_clk0 : std_logic;
signal sdr1_clk270 : std_logic;
signal sdr1_clk0_bufg : std_logic;
signal reset_cnt : unsigned(4 downto 0);
signal reset_pipe0 : unsigned(19 downto 0);
signal reset_pipe1 : unsigned(19 downto 0);
signal reset_pipe2 : unsigned(19 downto 0);
signal vga_fx_lock : std_logic;
signal sys_fx_lock : std_logic;
signal sdr0_lock : std_logic;
signal sdr1_lock : std_logic;
signal dcm0_clk0 : std_logic;
signal dcm0_clk0_bufg : std_logic;
signal dcm0_clkfx : std_logic;
signal dcm1_clk0 : std_logic;
signal dcm1_clk270 : std_logic;
signal dcm1_clk0_bufg : std_logic;
signal dcm1_clk270_bufg : std_logic;
signal dcm2_clk0 : std_logic;
signal dcm2_clk270 : std_logic;
signal dcm2_clk0_bufg : std_logic;
signal dcm2_clk270_bufg : std_logic;
signal dcm0_locked : unsigned(2 downto 0);
signal dcm1_locked : unsigned(2 downto 0);
signal dcm2_locked : unsigned(2 downto 0);
signal cnt_q : unsigned(4 downto 0);
type STATE_TYPE is (s0, s1, s2, s3, s4);
signal state_q : STATE_TYPE;
begin
sdr_clk0_0_out <= dcm1_clk0_bufg;
sdr_clk0_270_out <= dcm1_clk270_bufg;
sdr_clk1_0_out <= dcm2_clk0_bufg;
sdr_clk1_270_out <= dcm2_clk270_bufg;
bufg11: bufg
port map
(
o => dcm1_clk0_bufg,
i => dcm1_clk0
);
bufg12: bufg
port map (
o => dcm1_clk270_bufg,
i => dcm1_clk270
);
bufg13: bufg
port map
(
o => dcm2_clk0_bufg,
i => dcm2_clk0
);
bufg14: bufg
port map (
o => dcm2_clk270_bufg,
i => dcm2_clk270
);
-------------------------------------------------------------------------------------------------------
-- Clock generation
-------------------------------------------------------------------------------------------------------
-- Compnent instantiation
inst_DCM_VGA_FX : DCM_BASE
inst_DCM_BASE_0 : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, vga_clk_out_freq_hz), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, vga_clk_out_freq_hz), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
@@ -111,92 +139,38 @@ begin
)
port map
(
CLK0 => vga_clk0, -- 0 degree DCM CLK ouptput
CLK0 => dcm0_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => vga_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX => dcm0_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => vga_fx_lock, -- DCM LOCK status output
CLKFB => vga_clk0_bufg, -- DCM clock feedback
LOCKED => locked(0), -- DCM LOCK status output
CLKFB => dcm0_clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(0) -- DCM asynchronous reset input
);
BUFG_vga_clk0 : BUFG
BUFG_dcm_clk_fb : BUFG
port map
(
O => vga_clk0_bufg, -- Clock buffer output
I => vga_clk0 -- Clock buffer input
O => dcm0_clk0_bufg, -- Clock buffer output
I => dcm0_clk0 -- Clock buffer input
);
BUFG_vga_clkfx : BUFG
BUFG_clk_out : BUFG
port map
(
O => vga_clk_out, -- Clock buffer output
I => vga_clkfx -- Clock buffer input
I => dcm0_clkfx -- Clock buffer input
);
-- Compnent instantiation
inst_DCM_SYS_FX : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, sys_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, sys_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => sys_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => sys_fx_lock, -- DCM LOCK status output
CLKFB => sys_clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(0) -- DCM asynchronous reset input
);
BUFG_sys_clk0 : BUFG
port map
(
O => sys_clk0_bufg, -- Clock buffer output
I => sys_clk0 -- Clock buffer input
);
BUFG_sys_clkfx : BUFG
port map
(
O => sys_clkfx_bufg, -- Clock buffer output
I => sys_clkfx -- Clock buffer input
);
cpu_clk_out <= sys_clk0_bufg;
sys_clk_out <= sys_clkfx_bufg;
inst_DCM_SDRCLK_0 : DCM_BASE
sys_clk_out <= dcm0_clk0_bufg;
inst_DCM_BASE_1 : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
@@ -204,7 +178,7 @@ inst_DCM_SDRCLK_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -215,40 +189,29 @@ inst_DCM_SDRCLK_0 : DCM_BASE
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => sdr0_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
PHASE_SHIFT => sdr_clk0_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => sdr0_clk0, -- 0 degree DCM CLK ouptput
CLK0 => dcm1_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => sdr0_clk270, -- 270 degree DCM CLK output
CLK270 => dcm1_clk270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => sdr0_lock, -- DCM LOCK status output
CLKFB => sdr0_clk_fb_in, -- DCM clock feedback
CLKIN => sys_clkfx_bufg, -- Clock input (from IBUFG, BUFG or DCM)
LOCKED => locked(1), -- DCM LOCK status output
CLKFB => sdr_clk0_fb_in, -- DCM clock feedback
CLKIN => dcm0_clk0_bufg, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(1) -- DCM asynchronous reset input
);
bufg_sdr0_clk0: bufg
port map
(
o => sdr0_clk0_out,
i => sdr0_clk0
);
bufg_sdr0_clk270: bufg
port map (
o => sdr0_clk270_out,
i => sdr0_clk270
);
inst_DCM_SDRCLK_1 : DCM_BASE
dcm_rst(1) <= not locked(0);
inst_DCM_BASE_2 : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
@@ -256,7 +219,7 @@ bufg_sdr0_clk270: bufg
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -267,95 +230,79 @@ bufg_sdr0_clk270: bufg
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => sdr1_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
PHASE_SHIFT => sdr_clk1_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => sdr1_clk0, -- 0 degree DCM CLK ouptput
CLK0 => dcm2_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => sdr1_clk270, -- 270 degree DCM CLK output
CLK270 => dcm2_clk270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => sdr1_lock, -- DCM LOCK status output
CLKFB => sdr1_clk0_bufg, -- DCM clock feedback
CLKIN => sdr0_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
LOCKED => locked(2), -- DCM LOCK status output
CLKFB => dcm2_clk0_bufg, -- DCM clock feedback
CLKIN => sdr_clk0_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(2) -- DCM asynchronous reset input
);
sdr1_clk0_out <= sdr1_clk0_bufg;
bufg_sdr1_clk0: bufg
port map
(
o => sdr1_clk0_bufg,
i => sdr1_clk0
);
dcm_rst(2) <= not locked(1);
bufg_sdr1_clk270: bufg
port map (
o => sdr1_clk270_out,
i => sdr1_clk270
);
dcm_rst(0) <= reset_pipe0(reset_pipe0'left);
dcm_reset0:
process(rst_in, clk_in)
dcm_fsm:
process(rst, clk_in)
begin
if rst_in = '1' then
reset_pipe0 <= (others => '1');
if rst = '1' then
state_q <= s0;
dcm_rst(0) <= '0';
cnt_q <= "11111";
error_out <= '0';
locked_out <= '0';
dcm0_locked <= (others => '0');
dcm1_locked <= (others => '0');
dcm2_locked <= (others => '0');
elsif rising_edge(clk_in) then
reset_pipe0 <= reset_pipe0(reset_pipe0'left-1 downto 0) & '0';
case state_q is
when s0 =>
state_q <= s1;
when s1 =>
cnt_q <= cnt_q - 1;
if cnt_q = 0 then
dcm_rst(0) <= '1';
state_q <= s2;
end if;
when s2 =>
cnt_q <= cnt_q - 1;
if cnt_q = 0 then
dcm_rst(0) <= '0';
state_q <= s3;
end if;
when s3 =>
if dcm0_locked(2)='1' and dcm1_locked(2)='1' and dcm2_locked(2)='1' then
state_q <= s4;
error_out <= '0';
end if;
when s4 =>
if dcm0_locked(2)='1' and dcm1_locked(2)='1' and dcm2_locked(2)='1' then
locked_out <= '1';
else
error_out <= '1';
end if;
end case;
-- synchronize 'dcm1_locked'
dcm0_locked <= dcm0_locked(1 downto 0) & locked(0);
dcm1_locked <= dcm1_locked(1 downto 0) & locked(1);
dcm2_locked <= dcm2_locked(1 downto 0) & locked(2);
end if;
end process;
dcm_rst(1) <= reset_pipe1(reset_pipe1'left);
dcm_reset1:
process(vga_fx_lock, clk_in)
begin
if vga_fx_lock = '0' then
reset_pipe1 <= (others => '1');
elsif rising_edge(clk_in) then
reset_pipe1 <= reset_pipe1(reset_pipe1'left-1 downto 0) & '0';
end if;
end process;
dcm_rst(2) <= reset_pipe2(reset_pipe2'left);
dcm_reset2:
process(sdr0_lock, clk_in)
begin
if sdr0_lock = '0' then
reset_pipe2 <= (others => '1');
elsif rising_edge(clk_in) then
reset_pipe2 <= reset_pipe2(reset_pipe2'left-1 downto 0) & '0';
end if;
end process;
reset_out_logic:
process(rst_in, clk_in)
begin
if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then
sys_rst_out <= '1';
reset_cnt <= (reset_cnt'left downto reset_cnt'right => '1');
elsif rising_edge(clk_in) then
if reset_cnt /= (reset_cnt'left downto reset_cnt'right => '0') then
reset_cnt <= reset_cnt - 1;
else
sys_rst_out <= '0';
end if;
end if;
end process;
end architecture tech;
projects/mips_sys/src/mips_sys.vhd
+50 -145
View File
@@ -42,9 +42,9 @@ use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq_in : real := 100.0;
sys_freq : real := 100.0;
sdram_phaseshift : integer := 0;
sys_freq : integer := 100E6;
ddr_phaseshift : integer := 0;
ddr_frequency_hz : integer := 100E6;
tsvga : vga_timespec_t := ts_vga_800_600_60
);
@@ -126,23 +126,6 @@ PORT
sys_ps2_1_clk : inout std_logic;
sys_ps2_1_data : inout std_logic;
sys_phy_rstn : out std_logic;
sys_phy_mdc : out std_logic;
sys_phy_mdio : inout std_logic;
sys_phy_int : in std_logic;
sys_phy_rx_clk : in STD_LOGIC;
sys_phy_rx_dv : in STD_LOGIC;
sys_phy_rx_er : in STD_LOGIC;
sys_phy_rx : in unsigned(7 downto 0);
sys_phy_tx_clk : in STD_LOGIC;
sys_phy_tx_en : out STD_LOGIC;
sys_phy_tx_er : out STD_LOGIC;
sys_phy_tx : out unsigned(7 downto 0);
sys_phy_gtx_clk : out STD_LOGIC;
sys_phy_crs : in STD_LOGIC;
sys_phy_col : in STD_LOGIC;
sys_error : out unsigned(1 downto 0) -- indicates Errors
);
@@ -160,7 +143,6 @@ ARCHITECTURE behavior OF mips_sys IS
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
@@ -211,10 +193,9 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb
GENERIC
(
f_sysclk : real := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
PORT
@@ -264,10 +245,6 @@ ARCHITECTURE behavior OF mips_sys IS
END COMPONENT;
COMPONENT gpio_wb
Generic
(
f_sysclk : real := sys_freq
);
PORT
(
CLK_I : in STD_LOGIC;
@@ -284,8 +261,10 @@ ARCHITECTURE behavior OF mips_sys IS
DAT_O : out unsigned(31 downto 0);
INT_TIM_O : out STD_LOGIC;
sys_gpi_0 : in unsigned(31 downto 0);
sys_gpo_0 : out unsigned(31 downto 0)
sys_gpo0 : out unsigned(31 downto 0);
sys_gpo1 : out unsigned(31 downto 0);
sys_gpi0 : in unsigned(31 downto 0);
sys_gpi1 : in unsigned(31 downto 0)
);
END COMPONENT;
@@ -341,14 +320,13 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
signal cpu_clk : std_logic;
signal nmi : std_logic;
signal eb : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal vga_ce : std_logic;
signal dcm_lock : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart0 : std_logic;
@@ -473,24 +451,15 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_O_ps2_1 : std_logic;
signal SDAT_O_ps2_1 : unsigned(31 downto 0);
signal INT_O_emac : std_logic;
signal CYC_I_emac : std_logic;
signal ACK_O_emac : std_logic;
signal SRDY_O_emac : std_logic;
signal SDAT_O_emac : unsigned(31 downto 0);
signal gpi_0 : unsigned(31 downto 0);
signal gpo_0 : unsigned(31 downto 0);
signal ac97_inten : std_logic;
signal usb_inten : std_logic;
signal phy_inten : std_logic;
signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0);
signal gpi1 : unsigned(31 downto 0);
signal debug : unsigned(1 downto 0);
-- DDR SDRAM
constant BURST_LEN : natural := 2;
constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6;
-- attribute rom_style: string;
@@ -498,54 +467,37 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_ps2_0, mem_ps2_1, mem_sdram, mem_vga, mem_ac97, mem_emac);
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_ps2_0, mem_ps2_1, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
attribute KEEP : string;
attribute KEEP of vga_clk : signal is "TRUE";
attribute KEEP of sdram_clk0 : signal is "TRUE";
attribute KEEP of cpu_clk : signal is "TRUE";
attribute KEEP of CLK_O : signal is "TRUE";
attribute KEEP of RST_O : signal is "TRUE";
BEGIN
------------------------------------
-- GPIO_0 bits used for
-- 8.. 0 = O: LED 8..0
-- 11.. 9 = free
-- 12 = O: USB RST
-- 13 = O: USB INTEN
-- 14 = free
-- 15 = O: AC97 INTEN
-- 32..16 = I: DIP 7..0
-- 28..24 = I: BTN 4..0
-- 29 = O: PHY RESET
-- 30 = O: PHY MDC
-- 31 = IO: PHY MDIO
-- GPO1 bits used for
-- 0 : USB reset
-- 1 : USB interrupt enable
-- 2 : AC97 interrupt enable
-- others : reserved
------------------------------------
gpi_0(28 downto 24) <= sys_btn;
gpi_0(23 downto 16) <= sys_dip;
gpi_0(31) <= sys_phy_mdio;
sys_led <= gpo_0(8 downto 0);
sys_usb_rstn <= not gpo_0(12);
usb_inten <= gpo_0(13);
phy_inten <= gpo_0(14);
ac97_inten <= gpo_0(15);
sys_phy_rstn <= not gpo_0(29);
sys_phy_mdc <= gpo_0(30);
sys_phy_mdio <= gpo_0(31);
eb <= sys_dip(7);
gpi0(4 downto 0) <= sys_btn;
gpi1(7 downto 0) <= sys_dip;
sys_led <= gpo0(8 downto 0);
sys_error <= debug;
nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0);
sys_usb_rstn <= not gpo1(0);
sys_flash_byten <= '1';
sys_usb_a <= usb_Addr(3 downto 2);
sys_flash_a <= '0' & flash_addr(24 downto 2) & '0';
flash_page_mode_en <= not mem_mapped_io;
RST_O <= not dcm_lock;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_uart1_tx <= uart1_tx;
sys_uart2_tx <= uart1_tx;
@@ -553,7 +505,6 @@ BEGIN
sys_uart3_tx <= sys_uart3_rx;
sys_vga_clk <= vga_clk;
vga_ce <= not RST_O;
---------------------------------------------------------------
-- Arbiter
@@ -598,7 +549,7 @@ int_sample:
process(CLK_O)
begin
if rising_edge(CLK_O) then
INT <= int_timer & (INT_O_ps2_0 or INT_O_ps2_1 or INT_O_emac) & (INT_O_vga or (ac97_inten and INT_O_ac97)) & (usb_inten and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4);
INT <= int_timer & (INT_O_ps2_0 or INT_O_ps2_1) & (INT_O_vga or (gpo1(2) and INT_O_ac97)) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4);
end if;
end process;
@@ -609,8 +560,6 @@ mem_mux:
mem_mapped_io <= '0';
if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash;
elsif ADDR_O(31 downto 28) = X"1" then
mem_area <= mem_emac;
elsif ADDR_O(31 downto 28) = X"A" then
mem_mapped_io <= '1';
if ADDR_O(27 downto 26) = "00" then
@@ -632,8 +581,6 @@ mem_mux:
mem_area <= mem_vga;
elsif ADDR_O(18 downto 16) = "100" then
mem_area <= mem_ac97;
elsif ADDR_O(18 downto 16) = "101" then
mem_area <= mem_emac;
end if;
elsif ADDR_O(27 downto 26) = "01" then
mem_area <= mem_flash;
@@ -660,7 +607,6 @@ signal_mux:
CYC_I_sdram <= '0';
CYC_I_vga <= '0';
CYC_I_ac97 <= '0';
CYC_I_emac <= '0';
case mem_area is
@@ -697,9 +643,6 @@ signal_mux:
when mem_ac97 =>
CYC_I_ac97 <= CYC_O;
when mem_emac =>
CYC_I_emac <= CYC_O;
when others => null;
end case;
@@ -707,8 +650,8 @@ signal_mux:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_ps2_0 or SRDY_O_ps2_1 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97 or SRDY_O_emac;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_ps2_0 or ACK_O_ps2_1 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97 or ACK_O_emac;
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_ps2_0 or SRDY_O_ps2_1 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_ps2_0 or ACK_O_ps2_1 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
SDAT_O_flash when CYC_I_flash = '1' else
@@ -719,7 +662,6 @@ signal_mux:
SDAT_O_ps2_1 when CYC_I_ps2_1 = '1' else
SDAT_O_vga when CYC_I_vga = '1' else
SDAT_O_ac97 when CYC_I_ac97 = '1' else
SDAT_O_emac when CYC_I_emac = '1' else
SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
------------------------------------------------------------------
@@ -729,7 +671,6 @@ inst_mips_top: mips_top
debug => debug,
eb => eb,
nmi => nmi,
cpu_clk => cpu_clk,
RST_I => RST_O,
CLK_I => CLK_O,
ACK_I => ACK_I_cpu,
@@ -775,10 +716,6 @@ inst_lcd_port: lcd_port
);
inst_gpio_wb : gpio_wb
GENERIC MAP
(
f_sysclk => sys_freq
)
PORT MAP
(
CLK_I => CLK_O,
@@ -795,14 +732,15 @@ inst_gpio_wb : gpio_wb
DAT_O => SDAT_O_gpio,
INT_TIM_O => int_timer,
sys_gpi_0 => gpi_0,
sys_gpo_0 => gpo_0
sys_gpo0 => gpo0,
sys_gpo1 => gpo1,
sys_gpi0 => gpi0,
sys_gpi1 => gpi1
);
inst_flash_port : async_port_wb
GENERIC MAP
(
f_sysclk => sys_freq,
addr_width => 25,
data_width => 32,
byte_sel_width => 1,
@@ -835,7 +773,6 @@ inst_flash_port : async_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk => sys_freq,
addr_width => 4,
data_width => 16,
byte_sel_width => 1,
@@ -909,34 +846,32 @@ inst_uart_wb_1 : uart_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
clk_in_freq_hz => 100E6,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
sdr_clk0_out_phaseshift => 0,
sdr_clk1_out_phaseshift => 0
)
PORT MAP
(
-- Clocks and Reset
rst_in => rst_in, -- external async reset, low active
rst => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_rst_out => RST_O,
sys_clk_out => CLK_O,
vga_clk_out => vga_clk,
cpu_clk_out => cpu_clk,
sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sdr_clk0_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr_clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr_clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr_clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr_clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => dcm_lock, -- DCM locked status
error_out => open
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => sys_freq,
f_sdrclk => sys_freq,
f_sysclk => ddr_frequency_hz,
fifo_depth => 5
)
PORT MAP
@@ -1016,7 +951,7 @@ inst_vga_frontend : vga_frontend64
-- VGA signals
vga_clk_in => vga_clk,
vga_clk_ce => vga_ce,
vga_clk_ce => dcm_lock,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,
@@ -1058,7 +993,7 @@ inst_ac97_wb : entity work.ac97_wb
inst_ps2_wb_0: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk => sys_freq
f_sys_clk_hz => sys_freq
)
PORT MAP
(
@@ -1097,7 +1032,7 @@ inst_ps2_phy_0: entity work.ps2_phy
inst_ps2_wb_1: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk => sys_freq
f_sys_clk_hz => sys_freq
)
PORT MAP
(
@@ -1133,35 +1068,5 @@ inst_ps2_phy_1: entity work.ps2_phy
tx_data => ps2_1_data_tx
);
inst_emac_top_jb : entity work.emac_top_jb
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
INT_O => INT_O_emac,
CYC_I => CYC_I_emac,
STB_I => STB_O,
SEL_I => SEL_O(3 downto 0),
WE_I => WE_O,
ACK_O => ACK_O_emac,
SRDY_O => SRDY_O_emac,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O(31 downto 0),
DAT_O => SDAT_O_emac,
mii_rx_clk => sys_phy_rx_clk,
mii_rx_dv => sys_phy_rx_dv,
mii_rx_er => sys_phy_rx_er,
mii_rx => sys_phy_rx,
mii_tx_clk => sys_phy_tx_clk,
mii_tx_en => sys_phy_tx_en,
mii_tx_er => sys_phy_tx_er,
mii_tx => sys_phy_tx,
mii_gtx_clk => sys_phy_gtx_clk,
mii_crs => sys_phy_crs,
mii_col => sys_phy_col
);
------------------------------------------------------------------
END;
projects/mips_sys/src/mips_sys_sim.vhd
+278 -167
View File
@@ -32,6 +32,7 @@ use UNISIM.vcomponents.all;
library work;
use work.mips_types.all;
--use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
use work.vga_types.all;
@@ -42,9 +43,9 @@ use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq_in : real := 100.0;
sys_freq : real := 100.0;
sdram_phaseshift : integer := 0;
sys_freq : integer := 100E6;
ddr_phaseshift : integer := 0;
ddr_frequency_hz : integer := 100E6;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
@@ -131,23 +132,6 @@ PORT
sys_ps2_clk : inout std_logic;
sys_ps2_data : inout std_logic;
sys_phy_rstn : out std_logic;
sys_phy_mdc : out std_logic;
sys_phy_mdio : inout std_logic;
sys_phy_int : in std_logic;
sys_phy_rx_clk : in STD_LOGIC;
sys_phy_rx_dv : in STD_LOGIC;
sys_phy_rx_er : in STD_LOGIC;
sys_phy_rx : in unsigned(7 downto 0);
sys_phy_tx_clk : in STD_LOGIC;
sys_phy_tx_en : out STD_LOGIC;
sys_phy_tx_er : out STD_LOGIC;
sys_phy_tx : out unsigned(7 downto 0);
sys_phy_gtx_clk : out STD_LOGIC;
sys_phy_crs : in STD_LOGIC;
sys_phy_col : in STD_LOGIC;
sys_error : out unsigned(1 downto 0) -- indicates Errors
);
@@ -159,14 +143,228 @@ END mips_sys;
ARCHITECTURE behavior OF mips_sys IS
signal cpu_clk : std_logic;
COMPONENT mips_top
Port
(
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
DAT_O : out word_t;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0);
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC;
INT : in unsigned (5 downto 0)
);
END COMPONENT;
COMPONENT rom_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT lcd_port
PORT
(
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
lcd_d : inout unsigned(3 downto 0);
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
END COMPONENT;
COMPONENT async_port_wb
GENERIC
(
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
END COMPONENT;
COMPONENT flash_port_wb
GENERIC
(
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
);
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
port_bsyo : out std_logic;
port_bsyi : in std_logic;
port_a : out unsigned(addr_width-1 downto 0);
port_di : in unsigned(data_width-1 downto 0);
port_do : out unsigned(data_width-1 downto 0);
port_d_drv : out STD_LOGIC;
port_wr : out STD_LOGIC;
port_rd : out STD_LOGIC;
flash_cs : out std_logic;
flash_rst : out std_logic
);
END COMPONENT;
COMPONENT uart_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_O : out STD_LOGIC;
ser_rx : in std_logic;
ser_tx : out std_logic
);
END COMPONENT;
COMPONENT gpio_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_TIM_O : out STD_LOGIC;
sys_gpo0 : out unsigned(31 downto 0);
sys_gpo1 : out unsigned(31 downto 0);
sys_gpi0 : in unsigned(31 downto 0);
sys_gpi1 : in unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT vga_frontend64
GENERIC
(
fifo_depth : integer;
fifo_almost_full_thresh : natural;
fifo_almost_empty_thresh : natural;
tsvga : vga_timespec_t
);
PORT
(
-- System signals
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
-- JBUS Master signals
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(7 downto 0);
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
MRDY_O : out STD_LOGIC;
ADDR_O : out unsigned(31 downto 0);
MDAT_I : in unsigned(63 downto 0);
MDAT_O : out unsigned(63 downto 0);
-- JBUS Slave signals
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
SDAT_I : in unsigned(31 downto 0);
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
vga_blank_n : out std_logic;
vga_sync_n : out std_logic;
vga_hsync : out std_logic;
vga_vsync : out std_logic
);
END COMPONENT;
signal nmi : std_logic;
signal eb : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal vga_ce : std_logic;
signal dcm_lock : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart0 : std_logic;
@@ -304,76 +502,45 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_O_ps2 : std_logic;
signal SDAT_O_ps2 : unsigned(31 downto 0);
signal INT_O_emac : std_logic;
signal CYC_I_emac : std_logic;
signal ACK_O_emac : std_logic;
signal SRDY_O_emac : std_logic;
signal SDAT_O_emac : unsigned(31 downto 0);
signal gpi_0 : unsigned(31 downto 0);
signal gpo_0 : unsigned(31 downto 0);
signal ac97_inten : std_logic;
signal usb_inten : std_logic;
signal phy_inten : std_logic;
signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0);
signal gpi1 : unsigned(31 downto 0);
signal debug : unsigned(1 downto 0);
-- DDR SDRAM
constant BURST_LEN : natural := 2;
constant topad : time := 3 ns;
constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6;
constant topad : time := 3 ns;
-- attribute rom_style: string;
-- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_uart2, mem_uart, mem_sdram, mem_vga, mem_ac97, mem_emac);
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_uart2, mem_uart, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
BEGIN
------------------------------------
-- GPIO_0 bits used for
-- 8.. 0 = O: LED 8..0
-- 11.. 9 = free
-- 12 = O: USB RST
-- 13 = O: USB INTEN
-- 14 = free
-- 15 = O: AC97 INTEN
-- 32..16 = I: DIP 7..0
-- 28..24 = I: BTN 4..0
-- 29 = O: PHY RESET
-- 30 = O: PHY MDC
-- 31 = IO: PHY MDIO
------------------------------------
gpi_0(28 downto 24) <= sys_btn;
gpi_0(23 downto 16) <= sys_dip;
gpi_0(31) <= sys_phy_mdio;
sys_led <= gpo_0(8 downto 0);
sys_usb_rstn <= not gpo_0(12);
usb_inten <= gpo_0(13);
phy_inten <= gpo_0(14);
ac97_inten <= gpo_0(15);
sys_phy_rstn <= not gpo_0(29);
sys_phy_mdc <= gpo_0(30);
sys_phy_mdio <= gpo_0(31);
eb <= sys_dip(7);
gpi0(4 downto 0) <= sys_btn;
gpi1(7 downto 0) <= sys_dip;
sys_led <= gpo0(8 downto 0);
sys_error <= debug;
nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
sys_usb_rstn <= not gpo1(0);
sys_flash_byten <= '1';
ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2);
ADDR_I_ssram <= ("0000000000000" & ADDR_O(19 downto 2)) & '0';
eb <= sys_dip(7);
sys_error <= debug;
nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
sys_flash_byten <= '1';
ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2);
ADDR_I_ssram <= ("0000000000000" & ADDR_O(19 downto 2)) & '0';
SDAT_I_sdram <= MDAT_O & MDAT_O;
SEL_I_sdram <= "0000" & SEL_O;
SDAT_I_sdram <= MDAT_O & MDAT_O;
SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
vga_ce <= not RST_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
RST_O <= not dcm_lock;
sys_flash_ssram_out:
process(CLK_O)
@@ -443,7 +610,7 @@ int_sample:
process(CLK_O)
begin
if rising_edge(CLK_O) then
INT <= int_timer & (INT_O_ps2 or INT_O_emac) & (ac97_inten and INT_O_ac97) & (usb_inten and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4);
INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4);
end if;
end process;
@@ -455,8 +622,6 @@ mem_mux:
if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash;
flash_page_mode_en <= '1';
elsif ADDR_O(31 downto 28) = X"1" then
mem_area <= mem_emac;
elsif ADDR_O(31 downto 28) = X"A" then
if ADDR_O(27 downto 26) = "00" then
if ADDR_O(18 downto 16) = "000" then
@@ -475,8 +640,6 @@ mem_mux:
mem_area <= mem_vga;
elsif ADDR_O(18 downto 16) = "100" then
mem_area <= mem_ac97;
elsif ADDR_O(18 downto 16) = "101" then
mem_area <= mem_emac;
end if;
elsif ADDR_O(27 downto 26) = "01" then
mem_area <= mem_flash;
@@ -485,6 +648,8 @@ mem_mux:
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
-- kernel sram
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sdram;
end if;
@@ -505,7 +670,6 @@ signal_mux:
CYC_I_vga <= '0';
CYC_I_ssram <= '0';
CYC_I_ac97 <= '0';
CYC_I_emac <= '0';
case mem_area is
@@ -539,9 +703,6 @@ signal_mux:
when mem_ac97 =>
CYC_I_ac97 <= CYC_O;
when mem_emac =>
CYC_I_emac <= CYC_O;
when mem_ssram =>
CYC_I_ssram <= CYC_O;
@@ -552,8 +713,8 @@ signal_mux:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_uart2 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97 or SRDY_O_emac;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_uart2 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97 or ACK_O_emac;
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_uart2 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_uart2 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else
SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
@@ -564,17 +725,15 @@ signal_mux:
SDAT_O_uart2 when CYC_I_uart2 = '1' else
SDAT_O_vga when CYC_I_vga = '1' else
SDAT_O_ac97 when CYC_I_ac97 = '1' else
SDAT_O_emac when CYC_I_emac = '1' else
SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
------------------------------------------------------------------
inst_mips_top: entity work.mips_top
inst_mips_top: mips_top
PORT MAP
(
debug => debug,
eb => eb,
nmi => nmi,
cpu_clk => cpu_clk,
RST_I => RST_O,
CLK_I => CLK_O,
ACK_I => ACK_I_cpu,
@@ -590,7 +749,7 @@ inst_mips_top: entity work.mips_top
INT => INT
);
inst_rom_wb : entity work.rom_wb
inst_rom_wb : rom_wb
PORT MAP
(
CLK_I => CLK_O,
@@ -605,7 +764,7 @@ inst_rom_wb : entity work.rom_wb
);
inst_lcd_port: entity work.lcd_port
inst_lcd_port: lcd_port
PORT MAP
(
clk => CLK_O,
@@ -619,11 +778,7 @@ inst_lcd_port: entity work.lcd_port
lcd_rw => sys_lcd_rw
);
inst_gpio_wb : entity work.gpio_wb
GENERIC MAP
(
f_sysclk => sys_freq
)
inst_gpio_wb : gpio_wb
PORT MAP
(
CLK_I => CLK_O,
@@ -640,14 +795,15 @@ inst_gpio_wb : entity work.gpio_wb
DAT_O => SDAT_O_gpio,
INT_TIM_O => int_timer,
sys_gpi_0 => gpi_0,
sys_gpo_0 => gpo_0
sys_gpo0 => gpo0,
sys_gpo1 => gpo1,
sys_gpi0 => gpi0,
sys_gpi1 => gpi1
);
inst_flash_port : entity work.flash_port_wb
inst_flash_port : flash_port_wb
GENERIC MAP
(
f_sysclk => sys_freq,
addr_width => 25,
data_width => 32,
async_timespec => ts_flash
@@ -677,10 +833,9 @@ inst_flash_port : entity work.flash_port_wb
flash_rst => flash_rstn
);
inst_usb_port : entity work.async_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk => sys_freq,
addr_width => 2,
data_width => 16,
byte_sel_width => 1,
@@ -710,11 +865,7 @@ inst_usb_port : entity work.async_port_wb
async_rst => open
);
inst_uart_wb_0 : entity work.uart_wb
GENERIC MAP
(
simulate_tx => true
)
inst_uart_wb_0 : uart_wb
PORT MAP
(
CLK_I => CLK_O,
@@ -734,11 +885,7 @@ inst_uart_wb_0 : entity work.uart_wb
ser_tx => sys_uart0_tx
);
inst_uart_wb_1 : entity work.uart_wb
GENERIC MAP
(
simulate_tx => true
)
inst_uart_wb_1 : uart_wb
PORT MAP
(
CLK_I => CLK_O,
@@ -758,11 +905,7 @@ inst_uart_wb_1 : entity work.uart_wb
ser_tx => sys_uart1_tx
);
inst_uart_wb_2 : entity work.uart_wb
GENERIC MAP
(
simulate_tx => true
)
inst_uart_wb_2 : uart_wb
PORT MAP
(
CLK_I => CLK_O,
@@ -827,36 +970,34 @@ inst_ssram_port_wb : entity work.ssram_port_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
clk_in_freq_hz => sys_freq,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
sdr_clk0_out_phaseshift => 0,
sdr_clk1_out_phaseshift => 0
)
PORT MAP
(
-- Clocks and Reset
rst_in => rst_in, -- external async reset, low active
rst => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_rst_out => RST_O,
sys_clk_out => CLK_O,
vga_clk_out => vga_clk,
cpu_clk_out => cpu_clk,
sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sdr_clk0_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr_clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr_clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr_clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr_clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => dcm_lock, -- DCM locked status
error_out => open
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => sys_freq,
f_sdrclk => sys_freq,
fifo_depth => 5
BL => BURST_LEN,
f_sysclk => ddr_frequency_hz,
fifo_depth => 5
)
PORT MAP
(
@@ -894,7 +1035,7 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
);
inst_vga_frontend : entity work.vga_frontend64
inst_vga_frontend : vga_frontend64
GENERIC MAP
(
fifo_depth => 2048,
@@ -934,7 +1075,7 @@ inst_vga_frontend : entity work.vga_frontend64
-- VGA signals
vga_clk_in => vga_clk,
vga_clk_ce => vga_ce,
vga_clk_ce => dcm_lock,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,
@@ -976,7 +1117,7 @@ inst_ac97_wb : entity work.ac97_wb
inst_ps2_wb: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk => sys_freq
f_sys_clk_hz => sys_freq
)
PORT MAP
(
@@ -1012,36 +1153,6 @@ inst_ps2_phy: entity work.ps2_phy
tx_data => ps2_data_tx
);
inst_emac_jb : entity work.emac_top_jb
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
INT_O => INT_O_emac,
CYC_I => CYC_I_emac,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_emac,
SRDY_O => SRDY_O_emac,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_emac,
mii_rx_clk => sys_phy_rx_clk,
mii_rx_dv => sys_phy_rx_dv,
mii_rx_er => sys_phy_rx_er,
mii_rx => sys_phy_rx,
mii_tx_clk => sys_phy_tx_clk,
mii_tx_en => sys_phy_tx_en,
mii_tx_er => sys_phy_tx_er,
mii_tx => sys_phy_tx,
mii_gtx_clk => sys_phy_gtx_clk,
mii_crs => sys_phy_crs,
mii_col => sys_phy_col
);
------------------------------------------------------------------
END;
projects/mips_sys/src/sdram_config.vhd
+9 -9
View File
@@ -54,18 +54,18 @@ package sdram_config is
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
constant REFRESH_INTERVAL : real := 7.8125; -- us
-- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : real := 20.0; -- precharge command period [ns]
constant TRAS : real := 45.0; -- active to precharge delay [ns]
constant TRFC : real := 75.0; -- auto refresh command period [ns]
constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
constant TRCD : real := 20.0; -- active to read or write delay [ns]
constant TWR : real := 15.0; -- write recovery time [ns]
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : positive := 2; -- precharge command period
constant TRAS : positive := 5; -- active to precharge delay
constant TRFC : positive := 8; -- auto refresh command period
constant TMRD : positive := 2; -- load mode register command cylce time
constant TRCD : positive := 2; -- active to read or write delay !
constant TWR : positive := 2; -- write recovery time
constant PWR_UP_WAIT : real := 220.0E3; -- [ns]
constant PWR_UP_WAIT : natural := 222; -- µs
subtype user_tag_t is unsigned(3 downto 0);
projects/mips_sys/src/sdram_config_sim.vhd
+9 -9
View File
@@ -54,18 +54,18 @@ package sdram_config is
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
constant REFRESH_INTERVAL : real := 7.8125; -- us
-- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : real := 20.0; -- precharge command period [ns]
constant TRAS : real := 45.0; -- active to precharge delay [ns]
constant TRFC : real := 75.0; -- auto refresh command period [ns]
constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
constant TRCD : real := 20.0; -- active to read or write delay [ns]
constant TWR : real := 15.0; -- write recovery time [ns]
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : positive := 2; -- precharge command period
constant TRAS : positive := 5; -- active to precharge delay
constant TRFC : positive := 8; -- auto refresh command period
constant TMRD : positive := 2; -- load mode register command cylce time
constant TRCD : positive := 2; -- active to read or write delay !
constant TWR : positive := 2; -- write recovery time
constant PWR_UP_WAIT : real := 22.0E3; -- [ns]
constant PWR_UP_WAIT : natural := 22; -- µs
subtype user_tag_t is unsigned(3 downto 0);
projects/mips_sys/src/sys_types.vhd
+28 -28
View File
@@ -31,38 +31,38 @@ package async_defs is
constant ts_flash : async_timespec_t :=
(
T_leadin => 00.0,
T_pulse_rd => 120.0,
T_pulse_wr => 70.0,
T_leadout => 00.0,
T_release => 40.0,
T_pulse_rst => 80.0,
T_pulse_page_rd => 30.0,
can_page_rd => true,
nbits_page_rd => 4,
pol_cs => '1',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
ncyc_leadin => 0,
ncyc_pulse_rd => 12,
ncyc_pulse_wr => 7,
ncyc_leadout => 0,
ncyc_release => 4,
ncyc_pulse_rst => 8,
can_page_rd => true,
nbits_page_rd => 4,
ncyc_pulse_page_rd => 3,
pol_cs => '1',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
);
constant ts_usb : async_timespec_t :=
(
T_leadin => 10.0,
T_pulse_rd => 60.0,
T_pulse_wr => 60.0,
T_leadout => 10.0,
T_release => 80.0,
T_pulse_rst => 80.0,
T_pulse_page_rd => 00.0,
can_page_rd => false,
nbits_page_rd => 0,
pol_cs => '0',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
ncyc_leadin => 1,
ncyc_pulse_rd => 6,
ncyc_pulse_wr => 6,
ncyc_leadout => 1,
ncyc_release => 8,
ncyc_pulse_rst => 8,
can_page_rd => false,
nbits_page_rd => 0,
ncyc_pulse_page_rd => 0,
pol_cs => '0',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
);
----------------------------------------------------------------------------------------------
projects/mips_sys/src/tb_mips_sys.vhd
+11 -74
View File
@@ -31,7 +31,6 @@ library work;
use work.mips_types.all;
use work.sdram_config.all;
use work.sdram_types.all;
use work.vga_types.all;
ENTITY tb_mips_sys IS
END tb_mips_sys;
@@ -40,8 +39,6 @@ ARCHITECTURE behavior OF tb_mips_sys IS
constant CLK_PERIOD : time := 10 ns;
constant AC97_CLK_PERIOD : time := 83 ns;
constant ETH_CLK_PERIOD : time := 7.7 ns;
constant LOOP_BACK_EN : std_logic := '1';
signal sys_rst_n_in : std_logic := '0';
signal sys_clk_in : std_logic := '1';
signal dip : unsigned(7 downto 0) := (others => '0');
@@ -109,29 +106,11 @@ ARCHITECTURE behavior OF tb_mips_sys IS
SIGNAL sys_ac97_ssync : std_logic;
SIGNAL sys_ac97_sdata_in : std_logic;
SIGNAL sys_ps2_clk : std_logic := 'H';
SIGNAL sys_ps2_data : std_logic := 'H';
SIGNAL sys_phy_rstn : std_logic;
SIGNAL sys_phy_mdc : std_logic;
SIGNAL sys_phy_mdio : std_logic := 'H';
SIGNAL sys_phy_int : std_logic := '0';
SIGNAL sys_phy_rx_clk : STD_LOGIC := '0';
SIGNAL sys_phy_rx_dv : STD_LOGIC := '0';
SIGNAL sys_phy_rx_er : STD_LOGIC := '0';
SIGNAL sys_phy_rx : unsigned(7 downto 0) := (others => '0');
SIGNAL sys_phy_tx_clk : STD_LOGIC := '0';
SIGNAL sys_phy_tx_en : STD_LOGIC;
SIGNAL sys_phy_tx_er : STD_LOGIC;
SIGNAL sys_phy_tx : unsigned(7 downto 0);
SIGNAL sys_phy_gtx_clk : STD_LOGIC;
SIGNAL sys_phy_crs : STD_LOGIC := '0';
SIGNAL sys_phy_col : STD_LOGIC := '0';
SIGNAL sys_ps2_clk : std_logic := 'Z';
SIGNAL sys_ps2_data : std_logic := 'Z';
signal flash_reg : word_t;
signal eth_tx_reg : unsigned(7 downto 0);
type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
signal flash_data : flash_data_t;
@@ -143,13 +122,11 @@ ARCHITECTURE behavior OF tb_mips_sys IS
BEGIN
uut: entity work.mips_sys
GENERIC MAP
(
sys_freq_in => 100.000,
sys_freq => 100.000,
sdram_phaseshift => 0,
tsvga => ts_vga_800_600_72
)
-- GENERIC MAP
-- (
-- ddr_phaseshift => 90,
-- ddr_frequency_hz => 100E6
-- )
PORT MAP
(
sys_rst_n_in => sys_rst_n_in,
@@ -217,33 +194,10 @@ uut: entity work.mips_sys
sys_ps2_clk => sys_ps2_clk,
sys_ps2_data => sys_ps2_data,
sys_phy_rstn => sys_phy_rstn,
sys_phy_mdc => sys_phy_mdc,
sys_phy_mdio => sys_phy_mdio,
sys_phy_int => sys_phy_int,
sys_phy_rx_clk => sys_phy_rx_clk,
sys_phy_rx_dv => sys_phy_rx_dv,
sys_phy_rx_er => sys_phy_rx_er,
sys_phy_rx => sys_phy_rx,
sys_phy_tx_clk => sys_phy_tx_clk,
sys_phy_tx_en => sys_phy_tx_en,
sys_phy_tx_er => sys_phy_tx_er,
sys_phy_tx => sys_phy_tx,
sys_phy_gtx_clk => sys_phy_gtx_clk,
sys_phy_crs => sys_phy_crs,
sys_phy_col => sys_phy_col,
sys_error => sys_error
);
sys_phy_rx <= sys_phy_tx when LOOP_BACK_EN = '1' else X"00";
sys_phy_rx_dv <= sys_phy_tx_en when LOOP_BACK_EN = '1' else '0';
sys_phy_rx_er <= sys_phy_tx_er when LOOP_BACK_EN = '1' else '0';
sys_phy_crs <= '0';
sys_phy_col <= '0';
inst_ssram : entity work.cy7c1354
PORT MAP
(
@@ -300,7 +254,7 @@ i_mt46v16m16_1 : entity work.mt46v16m16
dm => std_logic_vector(sys_sdr_dm_q(3 downto 2))
);
sys_sdr_clk_fb <= sys_sdr_clk_p after 1300 ps;
sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
sys_ssram_clk_fb <= sys_ssram_clk after 0.5 ns;
refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
@@ -313,22 +267,6 @@ CLK_GEN: process
sys_clk_in <= not sys_clk_in;
end process;
ETH_CLK_GEN: process
begin
wait for ETH_CLK_PERIOD/2;
sys_phy_rx_clk <= not sys_phy_rx_clk;
sys_phy_tx_clk <= not sys_phy_tx_clk;
end process;
ETH_TX_REGISTER:
PROCESS(sys_phy_tx_clk)
begin
if rising_edge(sys_phy_tx_clk) then
if (sys_phy_tx_en = '1') then
eth_tx_reg <= sys_phy_tx;
end if;
end if;
end process;
sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out;
@@ -365,7 +303,7 @@ ac97_clk_gen : PROCESS
FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
type file_t is file of integer;
file load_flash : file_t open read_mode is "test_emac_sim.elf.flash.bin";
file load_flash : file_t open read_mode is "test_ac97.flash.bin";
variable instr : integer;
variable index : natural;
variable temp : signed(31 downto 0);
@@ -398,14 +336,13 @@ STIMULUS: process
begin
dip(7) <= '1'; -- EB
btn(0) <= '1';
btn(2) <= '1';
wait for 3*CLK_PERIOD;
sys_rst_n_in <= '1';
btn(0) <= '0';
btn(2) <= '0';
wait for 20000000*CLK_PERIOD;
wait for 200000*CLK_PERIOD;
loop
wait for 251*CLK_PERIOD;