|}\\n"",\n" &
- "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
-
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-
-fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-fprint(RESULT, L,
- "\n----------------------\n" &
- "-- Support for time --\n" &
- "----------------------\n"
- );
-
-fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
- "-- into an integer value (of nanoseconds)\n"
- );
-fprint (RESULT, L, "> wait for 648 ns\n");
-fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
-
-wait for 648 ns;
-
-fprint (RESULT, L, "The time is now %d ns\n", fo(now));
-
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Erroneous calls and error messages --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
- "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L, "-- Unsupported format specifier\n" &
- "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
- "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Things you wouldn't expect to work --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Nested iteration\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
-fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-
-wait;
-
-end process USAGE;
-
-end TB;
diff --git a/lib/PCK_FIO-2002.7/CHANGES b/lib/PCK_FIO-2002.7/CHANGES
deleted file mode 100644
index b755a56..0000000
--- a/lib/PCK_FIO-2002.7/CHANGES
+++ /dev/null
@@ -1,86 +0,0 @@
----- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-Changes from version 1.16 to version 2002.07
-============================================
-
-PCK_FIO is now distributed under the GNU Lesser General Public Licencse
-instead of the ordinary GPL, to better reflect intended usage.
-
-Cosmetic changes in source code to correct some typos in the testbench output.
-A new testbench is also supplied.
-
-The package now uses IEEE.numeric_std as default.
-
-URL http://www.easics.com has been made part of address.
-
-Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993.
-Because of backwards-incompatibility, it has been necessary to supply
-different sets of files for 1987 and 1993.
-
-Split the packages into a separate file for the header and a
-separate file for the body (in compliance with Easics' guidelines).
-
-These changes resulted in the files:
-
-Files for VHDL-1993:
---------------------
- PCK_FIO_1993.vhd : the source code of the header file for the package
- PCK_FIO_1993_BODY.vhd: the source code of the body of the package
- TB_PCK_FIO_1993.vhd: the testbench for the package
-
-Files for VHDL-1987:
---------------------
- PCK_FIO_1987.vhd: the source code of the header file for the package
- PCK_FIO_1987_BODY.vhd: the source code of the body of the package
- TB_PCK_FIO_1987.vhd: the testbench for the package
-
-Updated README and PCK_FIO.html to support these changes.
-
-Adapted package files to support NUL termination of strings.
-fo(Arg: string) now prints the string until the first NUL.
-Several examples of its use are demonstrated in the supplied testbenches.
-
-Made cosmetic changes to code to improve readability.
-
-Acknowledgment
---------------
-These changes have been implemented by Peter Geens.
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.html b/lib/PCK_FIO-2002.7/PCK_FIO.html
deleted file mode 100644
index 6b5fc72..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO.html
+++ /dev/null
@@ -1,339 +0,0 @@
-
-
-
-
-
- VHDL package for formatted file output
-
-
-
-
-
-
-Name
-PCK_FIO - VHDL package for formatted file output
-
-
-
-Contents
-Usage
-
The file output function 'fo'
-
Format specifiers
-
Special characters
-
Things to watch out for
-
Methodology notes
-
Parametrization
-
Test bench
-
Known limitations and problems
-
Author
-
-
-
-Usage
-PCK_FIO is a VHDL package that defines fprint, a function
-for formatted file output.
-After installing the package you can call fprint as follows:
-
fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable.
-The argument Format is the format string, which consists of ``normal''
-substrings which are copied verbatim, and format specifiers, starting with
-'%'.
-A typical format string looks as follows:
-
"Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write
-to the file, embedded in fo function calls. There can be 0 to
-32 of such arguments. The expressions can be of any type for which an fo
-function exists. String expressions can also be called directly.
-
-
-
-The file output function 'fo'
-The fo (file output) functions do the trick. They
-return a tagged string representation that is meaningful to format specifiers.
-Here are some examples:
- fo (signed'("1100")) returns "S:1100"
- fo (unsigned'("1100")) returns "U:1100"
- fo (TRUE) returns "L:T"
- fo (127) returns "I:127"
-The internal behavior of fo is irrelevant to the typical user.
-
-The fo function is currently overloaded as follows:
-
- function fo (Arg: unsigned) return string;
- function fo (Arg: signed) return string;
- function fo (Arg: std_logic_vector) return string;
- function fo (Arg: std_ulogic_vector) return string;
- function fo (Arg: bit_vector) return string;
- function fo (Arg: integer) return string;
- function fo (Arg: std_ulogic) return string;
- function fo (Arg: bit) return string;
- function fo (Arg: boolean) return string;
- function fo (Arg: character) return string;
- function fo (Arg: string) return string;
- function fo (Arg: time) return string;
-
-
To support null-terminated strings, the function fo(Arg:
-string) processes Arg up to the first NUL character,
-if any. If you want the whole string to be outputted you can just enter
-the string as a direct argument in fprint. See also the
-examples in the testbench.
-
-
-
-
-Format specifiers
-The general format of a format specifier is:
- %[-][n]c
-The optional - sign specifies left justified output; default is
-right justified.
-The optional number n specifies a field-width. If it is not specified,
-fprint
-does something reasonable.
-
c is the conversion specifier. Currently the following conversion
-specifiers are supported:
-
--
-r
-
--
-reasonable output format (inspired by Synopsys VSS)
-
-Prints the ``most reasonable'' representation e.g. hex for
-unsigned, signed and other bit-like vectors (not preferred for integers)
-
--
-b
-
--
-bit-oriented output
-
--
-d
-
--
-decimal output
-
--
-s
-
--
-string output (e.g. in combination with 'IMAGE for enum types)
-
--
-q
-
--
-``qualified'' string output (shows internal representation from fo)
-
--
-{}
-
--
-Iteration operator, used as follows:
-
--
-%n{<format-string>}
-
-
In this case, n is the iteration count and is mandatory. Iteration
-can be nested.
-
-
-
-Special characters
-To print a double quote, use '""' in the format string (VHDL
-convention). To print the special characters, '\', and '%',
-escape them with '\'. To prevent '{' and '}'
-from being interpreted as opening and closing brackets in iteration strings,
-escape them with '\'.
-A newline is specified in the format string by '\n'.
-
-
-
-Things to notice
-The fprint function expands into VHDL write and writeline
-commands. As in plain VHDL, nothing will be written to the output file
-until a writeline is given. Therefore, don't forget to include
-'\n'
-commands in the format string, or it ``will not work''.
-The preferred format specifier for integers is, naturally, %d.
-This calls the VHDL write for integers. If you specify a field
-width that is too small, the field will automatically be expanded. If you
-use %r for integers, the field is not expanded automatically, which
-means that some digits are simply thrown away. This may sometimes be useful
-but it is also dangerous. Look at the test bench output for differences
-between %d and %r output.
-
When using the %d format specifier, the VHDL constraints for
-the allowed integer range apply.
-
In VHDL, signed/unsigned types have been standardized only relatively
-recently, in the package IEEE.numeric_std. The lack of a standard
-has caused (and is causing) portability issues. The most popular non-standard
-package that defines signed/unsigned is IEEE.std_logic_arith from
-Synopsys. PCK_FIO works with both packages, but refers to the standard
-package IEEE.numeric_std by default. To use IEEE.std_logic_arith
-instead, replace the reference to IEEE.numeric_std in the source
-code. This needs to be done consistently in a design database (e.g.
-in the PCK_FIO test bench as well).
-
-
-
-Methodology notes
-The obvious application for fprint is in test benches, to produce
-output files that trace the simulation behavior.
-Another interesting application for fprint is to produce info,
-warning and error messages in your models. As it can take arguments, fprint
-is much better suited for this task than VHDL's assert or report
-statements. Actually fprint produces its own (few) warning messages.
-
An advanced usage is the generation of test vectors in a specific format.
-Instead of using the fo functions, you can write your own set
-of functions that return the symbols of a specific test format in a way
-that is understandable to the fprint format specifiers. As an
-example, when a high output value should be represented using the symbol
-'H' it suffices to write a conversion function that returns "B:H" and call
-it in combination with the %b format specifier.
-
-
-
-Parametrization
-Prefix and postfix strings for bit-oriented and hex-oriented output are
-parameterizable in the packages to accommodate different output styles.
-The settings in the distribution are such that hex output is indicated
-by the prefix '0x', while bit output prefix and postfix are empty
-strings.
-You can adapt the output style by modifying the following constants
-in the package header:
-
-- prefix string for hex output
-
-- VHDL style: "X"""
-
-- Verilog style: "h'"
-
-- C style: "0x"
-
constant FIO_h_PRE: string := "0x";
-
-- postfix string for hex output
-
-- VHDL style: """"
-
constant FIO_h_POST: string := "";
-
-- prefix string for bit vector output
-
-- VHDL style: "B"""
-
-- Verilog style: "b'"
-
constant FIO_bv_PRE: string := "";
-
-- postfix string for bit vector output
-
-- VHDL style: """"
-
constant FIO_bv_POST: string := "";
-
-- prefix string for bit output
-
-- VHDL style: "'"
-
-- Verilog style: "b'"
-
constant FIO_b_PRE: string := "";
-
-- postfix string for bit output
-
-- VHDL style: "'"
-
constant FIO_b_POST: string := "";
-
-
-
-Test bench
-Included in the distribution are the files TB_PCK_FIO_1987.vhd and
-TB_PCK_FIO_1993 with a test bench,depending on the standard you're
-running, for the PCK_FIO package. The file PCK_FIO.out.gold contains
-the expected output. If you run the test bench it should produce the file
-PCK_FIO.out
-that should be identical to PCK_FIO.out.gold. The source files
-should be analyzed in a VHDL library EASICS_PACKAGES.
-A good way to understand fprint is to inspect the test bench
-and what it produces.
-
-
-
-Known limitations and problems
-This VHDL package is an implementation of a flexible concept. It is likely
-to be extended and modified in the future. Backward compatibility is not
-guaranteed. Therefore, it is not recommended to give this package the status
-of a company wide standard package (or even worse, a VHDL standard package).
-Rather, it should be linked with a particular project (and it can be regarded
-as a standard package within that project).
-PCK_FIO is available in either standard VHDL Std1076-1987 or standard
-VHDL Std1076-1993. Nevertheless, some simulators/versions have problems
-with the package. The following is an overview of currently known issues:
-
-
-PCK_FIO_1987 and various simulators/versions
-
-
-| Simulator |
-
-PCK_FIO_1987 |
-
-
-
-| Synopsys VSS 3.5 and earlier |
-
-Incorrect (all zero) output in compiled mode |
-
-
-
-| Synopsys VSS 97.01 |
-
-OK |
-
-
-
-| Synopsys VSS/Scirocco 2000.02 |
-
-Incorrect output in compiled mode, interpreted mode works |
-
-
-
-| Mentor quickhdl |
-
-OK |
-
-
-
-| Modeltech modelsim |
-
-OK |
-
-
-
-| Cadence Leapfrog |
-
-Should work with 4.4.1
-
Mysterious problems have been reported - please run the test bench
-and report problems |
-
-
-
-
-
-PCK_FIO_1993 and various simulators/versions
-
-
-| Simulator |
-
-PCK_FIO_1993 |
-
-
-
-| Synopsys VSS/Scirocco 2000.02 |
-
-Compile errors due to improper handling of files by Synopsys |
-
-
-
-| Synopsys VSS/Scirocco 2000.06 |
-
-works fine |
-
-
-
-| Modeltech modelsim 5.4c and higher |
-
-OK |
-
-
-
-Although the package name suggests file IO, it only does file output.
-
-
-
-Author
-Jan Decaluwe
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.out.gold b/lib/PCK_FIO-2002.7/PCK_FIO.out.gold
deleted file mode 100644
index 3fcfe4c..0000000
Binary files a/lib/PCK_FIO-2002.7/PCK_FIO.out.gold and /dev/null differ
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd
deleted file mode 100644
index d4cf8e6..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
----- $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-use STD.TEXTIO.all;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
--- use IEEE.std_logic_arith.all; -- the Synopsys one
-use IEEE.numeric_std.all;
-
-package PCK_FIO is
-
- -- prefix string for hex output
- -- VHDL style: "X"""
- -- Verilog style: "h'"
- -- C style: "0x"
- constant FIO_h_PRE: string := "0x";
-
- -- postfix string for hex output
- -- VHDL style: """"
- constant FIO_h_POST: string := "";
-
- -- prefix string for bit vector output
- -- VHDL style: "B"""
- -- Verilog style: "b'"
- constant FIO_bv_PRE: string := "";
-
- -- postfix string for bit vector output
- -- VHDL style: """"
- constant FIO_bv_POST: string := "";
-
- -- prefix string for bit output
- -- VHDL style: "'"
- -- Verilog style: "b'"
- constant FIO_b_PRE: string := "";
-
- -- postfix string for bit output
- -- VHDL style: "'"
- constant FIO_b_POST: string := "";
-
- -- digit width for the string representation of integers
- constant FIO_d_WIDTH: integer := 10;
-
- -- bit width for the string representation of integers
- constant FIO_b_WIDTH: integer := 32;
-
- -- definition of the NIL string (default value for fprint arguments)
- -- fprint stops consuming arguments at the first NIL argument
- constant FIO_NIL: string := "\";
-
-
- procedure fprint
- (F: out text;
- L: inout line;
- Format: in string;
- A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
- A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
- A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
- A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
- );
-
- function fo (Arg: unsigned) return string;
- function fo (Arg: signed) return string;
- function fo (Arg: std_logic_vector) return string;
- function fo (Arg: std_ulogic_vector) return string;
- function fo (Arg: bit_vector) return string;
- function fo (Arg: integer) return string;
- function fo (Arg: std_ulogic) return string;
- function fo (Arg: bit) return string;
- function fo (Arg: boolean) return string;
- function fo (Arg: character) return string;
- function fo (Arg: string) return string;
- function fo (Arg: time) return string;
-
- procedure FIO_FormatExpand (FMT: inout line;
- Format: in string;
- StartPointer: in positive);
-
-end PCK_FIO;
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd
deleted file mode 100644
index 44e42cf..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd
+++ /dev/null
@@ -1,821 +0,0 @@
----- $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-package body PCK_FIO is
-
- --------------------------
- -- FIO Warnings support --
- --------------------------
-
- procedure FIO_Warning_Fsbla (F: out text;
- L: inout line;
- Format: in string;
- Pointer: in positive) is
- begin
- fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
- "Format specifier beyond last argument\n");
- fprint (F, L, "** in format string: ""%s""\n", Format);
- fprint (F, L, "** ");
- for i in 1 to Pointer-1 loop
- fprint (F, L, "-");
- end loop;
- fprint (F, L, "^\n");
- end FIO_Warning_Fsbla;
-
- procedure FIO_Warning_Ufs (F: out text;
- L: inout line;
- Format: in string;
- Pointer: in positive;
- Char: in character) is
- begin
- fprint (F, L, "\n** Warning: FIO_PrintArg: " &
- "Unexpected format specifier '%r'\n",
- fo(Char));
- fprint (F, L, "** in format string: ""%s""\n", Format) ;
- fprint (F, L, "** ");
- for i in 1 to Pointer-1 loop
- fprint (F, L, "-");
- end loop;
- fprint (F, L, "^\n** Assuming 'q' to proceed: ");
- end FIO_Warning_Ufs;
-
-
- ----------------------------------
- -- bit conversion support --
- ----------------------------------
-
- type T_bit_map is array(bit) of character;
-
- constant C_BIT_MAP: T_bit_map
- := ('0', '1');
-
- ----------------------------------
- -- std_logic conversion support --
- ----------------------------------
-
- type T_std_logic_map is array(std_ulogic) of character;
-
- constant C_STD_LOGIC_MAP: T_std_logic_map
- := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
-
- ------------------------------
- -- Digit conversion support --
- ------------------------------
-
- -- types & constants
-
- subtype S_digit_chars is character range '0' to '9';
- subtype S_digits is integer range 0 to 9 ;
-
- type T_digit_chars_map is array(S_digit_chars) of S_digits;
-
- constant C_DIGIT_CHARS_MAP: T_digit_chars_map
- := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
-
- type T_digits_map is array(S_digits) of S_digit_chars;
-
- constant C_DIGITS_MAP: T_digits_map
- := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
-
-
- --------------------------------
- -- Decimal conversion support --
- --------------------------------
-
- -- unsigned to decimal
-
- function U_To_d (Arg: string) return integer is
- constant Argument: string(Arg'length downto 1) := Arg;
- variable Result: integer := 0;
- begin
- for i in Argument'range loop
- case Argument(i) is when '1' => Result := 2**(i-1) + Result;
- when '0' => null;
- when others => return(-1);
- end case;
- end loop;
- return (Result);
- end U_To_d;
-
- -- signed to decimal
-
- function S_To_d (Arg: string) return integer is
- constant Argument: string(Arg'length downto 1) := Arg;
- variable Result: integer := 0;
- begin
- case Argument(Argument'left) is
- when '1' => Result := - 2**(Argument'left-1);
- when '0' => Result := 0;
- when others => return (integer'low);
- end case;
- for i in Argument'left-1 downto 1 loop
- case Argument(i) is when '1' => Result := 2**(i-1) + Result;
- when '0' => null;
- when others => return(integer'low);
- end case;
- end loop;
- return (Result);
- end S_To_d;
-
- -- string to decimal
-
- function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
- constant Sign: character := Arg(1);
- constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
- variable Char: character;
- variable Result: integer := 0;
- begin
- Result := 0;
- for i in Value'range loop
- Result := Result * 10;
- Char := Value(i);
- if (Char /= ' ') then
- Result := Result + C_DIGIT_CHARS_MAP(Char);
- end if;
- end loop;
- case Sign is when '-' => return(-Result);
- when others => return(Result);
- end case;
- end I_To_d;
-
- -- boolean (0,1) to decimal
-
- function B_To_d (Arg: string(1 to 1)) return integer is
- begin
- case Arg is when "1" => return(1);
- when "0" => return(0);
- when others => return(-1);
- end case;
- end B_To_d;
-
- -- boolean (T,F) to decimal
-
- function L_To_d (Arg: string(1 to 1)) return integer is
- begin
- case Arg is when "T" => return(1);
- when others => return(0);
- end case;
- end L_To_d;
-
-
-
- ----------------------------
- -- Hex conversion support --
- ----------------------------
-
- -- Constants & types
-
- constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
-
- -- Function to return Hex index of a nibble
-
- function U_To_h_Index(Arg: string(4 downto 1)) return integer is
- variable Index: integer := 0;
- begin
- for i in Arg'range loop
- case Arg(i) is when '1' => Index := 2**(i-1) + Index;
- when '0' => null;
- when others => return (17);
- end case;
- end loop;
- return (Index+1);
- end U_To_h_Index;
-
- -- Hex conversion
-
- function U_To_h (Arg: string) return string is
- variable Result: string((Arg'length-1)/4 +1 downto 1);
- variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
- begin
- ExtArg(Arg'length downto 1) := Arg;
- for i in Result'range loop
- Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
- end loop;
- return (FIO_h_PRE & Result & FIO_h_POST);
- end U_To_h;
-
-
-
- ----------------------------
- -- Bit conversion support --
- ----------------------------
-
- function L_To_b (Arg: string(1 to 1)) return string is
- variable Result: string(1 to 1);
- begin
- case Arg is when "T" => Result := "1";
- when others => Result := "0";
- end case;
- return(FIO_b_PRE & Result & FIO_b_POST);
- end L_To_b;
-
-
- function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
- Justified: side;
- Width: integer) return string is
-
- variable IntValue: integer := I_To_d(Arg);
- variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
- variable Sign: character := ' ';
- constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
- variable BitWidth: integer range 0 to FIO_b_WIDTH;
- variable MsPos: integer range 1 to BitValue'length;
- variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
-
- begin
-
- if (IntValue < 0) then
- Sign := '-';
- IntValue := -IntValue;
- end if;
-
- for i in BitValue'reverse_range loop
- BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
- IntValue := IntValue / 2;
- exit when (IntValue = 0);
- end loop;
-
- BitValueExtended := BitValue & Blanks;
-
- if (Width = 0) or (Width > FIO_b_WIDTH+1) then
- BitWidth := FIO_b_WIDTH;
- else
- BitWidth := Width-1;
- end if;
-
- if (Justified = RIGHT) then
- return (FIO_bv_PRE &
- Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
- FIO_bv_POST);
- else
- for i in BitValue'range loop
- if BitValue(i) /= ' ' then
- MSPos := i;
- exit;
- end if;
- end loop;
- return (FIO_bv_PRE &
- Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
- FIO_bv_POST);
- end if;
-
- end I_To_b;
-
-
- -----------------------------------
- -- Reasonable conversion support --
- -----------------------------------
-
- function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
- Justified: side;
- Width: integer) return string is
- constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
- constant Sign: character := Arg(1);
- constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
- variable IntWidth: integer range 0 to FIO_d_WIDTH;
- variable MsPos: integer range 1 to Value'length;
- variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
- begin
- if (Width = 0) or (Width > FIO_d_WIDTH+1) then
- IntWidth := FIO_d_WIDTH;
- else
- IntWidth := Width-1;
- end if;
- if (Justified = RIGHT) then
- return (Sign & Value(Value'length-IntWidth+1 to Value'length));
- else
- for i in Value'range loop
- if Value(i) /= ' ' then
- MSPos := i;
- exit;
- end if;
- end loop;
- return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
- end if;
- end I_To_r;
-
-
- -------------------------------------------
- -- Reasonable output conversion function --
- -------------------------------------------
-
- function ReasonableOutput (Arg: string;
- Justified: side;
- Width: integer) return string is
- constant Argument: string(1 to Arg'length) := Arg;
- constant TypeSpec: string (1 to 2) := Argument(1 to 2);
- constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
- begin
- case TypeSpec is
- when "U:" | "S:" | "V:" =>
- return U_To_h(Value);
- when "I:" =>
- return I_To_r(Value, Justified, Width);
- when "B:" | "L:" | "C:" =>
- return Value;
- when others =>
- return Argument;
- end case;
-
- end ReasonableOutput;
-
-
- ------------------------------------
- -- Bit output conversion function --
- ------------------------------------
-
- function BitOutput (Arg: string;
- Justified: side;
- Width: integer) return string is
- constant Argument: string(1 to Arg'length) := Arg;
- constant TypeSpec: string (1 to 2) := Argument(1 to 2);
- constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
- begin
- case TypeSpec is
- when "U:" | "S:" | "V:" =>
- return (FIO_bv_PRE & Value & FIO_bv_POST);
- when "B:" =>
- -- Value(1 to 1) instead of Value for LeapFrog
- return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
- when "I:" =>
- return I_To_b(Value, Justified, Width);
- when "L:" =>
- -- Value(1 to 1) instead of Value for LeapFrog
- return L_To_b(Value(1 to 1));
- when others =>
- return Argument;
- end case;
-
- end BitOutput;
-
-
- -------------------------------------------
- -- Decimal output conversion function --
- -------------------------------------------
-
- function DecimalOutput (Arg: string) return integer is
- constant Argument: string(1 to Arg'length) := Arg;
- constant TypeSpec: string (1 to 2) := Argument(1 to 2);
- constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
- begin
- case TypeSpec is
- when "U:"| "V:" =>
- return U_To_d(Value);
- when "S:" =>
- return S_To_d(Value);
- when "I:" =>
- return I_To_d(Value);
- when "B:" =>
- return B_To_d(Value);
- when "L:" =>
- return L_To_d(Value);
- when others =>
- return integer'low;
- end case;
-
- end DecimalOutput;
-
-
- ----------------------------
- -- Atomic print functions --
- ----------------------------
-
- -- test for end of format string
-
- function FIO_EOS (Format: in string;
- Pointer: in integer)
- return boolean is
- begin
- return (Pointer > Format'length);
- end FIO_EOS;
-
-
- -- Atomic value print function
-
- procedure FIO_PrintValue (F: out text;
- L: inout line;
- Format: in string;
- Pointer: inout integer;
- Last: in boolean := FALSE) is
- variable Char: character;
- begin
- while (not FIO_EOS(Format, Pointer)) loop
- Char := Format(Pointer);
- case Char is
- when '\' =>
- Pointer := Pointer + 1;
- exit when (FIO_EOS(Format, Pointer));
- Char := Format(Pointer);
- case Char is when 'n' => writeline(F, L);
- when others => write(L, Char);
- end case;
- when '%' =>
- if Last then
- FIO_Warning_Fsbla(F, L, Format, Pointer);
- end if;
- Pointer := Pointer + 1;
- exit;
- when others =>
- write(L, char);
- end case;
- Pointer := Pointer + 1;
- end loop;
- end FIO_PrintValue;
-
-
- ---- Atomic argument print function
-
- procedure FIO_PrintArg (F: out text;
- L: inout line;
- Format: in string;
- Pointer: inout integer;
- Arg: in string) is
- variable Char: character;
- variable Justified: side;
- variable Width: integer;
- begin
-
- FIO_PrintValue(F, L, Format, Pointer);
-
- Justified := RIGHT;
- Width := 0;
- while (not FIO_EOS(Format, Pointer)) loop
- Char := Format(Pointer);
- case Char is
- when '-' =>
- Justified := LEFT;
- Pointer := Pointer + 1;
- when '0' to '9' =>
- Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
- Pointer := Pointer + 1;
- when 'r' =>
- write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
- Pointer := Pointer + 1;
- exit;
- when 'b' =>
- write(L, BitOutput(Arg, Justified, Width), Justified, Width);
- Pointer := Pointer + 1;
- exit;
- when 'd' =>
- write(L, DecimalOutput(Arg), Justified, Width);
- Pointer := Pointer + 1;
- exit;
- when 'q' | 's' =>
- write(L, Arg, Justified, Width);
- Pointer := Pointer + 1;
- exit;
- when others =>
- FIO_Warning_Ufs(F, L, Format, Pointer, Char);
- write(L, Arg, Justified, Width);
- Pointer := Pointer + 1;
- exit;
- end case;
- end loop;
- end FIO_PrintArg;
-
-
- -----------------------------------------------------
- -- The format string iteration expansion procedure --
- -----------------------------------------------------
-
- procedure FIO_FormatExpand (FMT: inout line;
- Format: in string;
- StartPointer: in positive) is
-
- variable Pointer: positive := StartPointer;
- variable TokenStart: positive;
- variable IterStringStart: positive;
- variable IterStringEnd: positive;
- variable IterCount: natural;
- variable OpenBrackets: natural;
- variable L: line;
-
- begin
-
- FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
-
- case Format(Pointer) is
-
- -- look for format specifier
- when '%' =>
-
- -- initialize iteration token search
- TokenStart := Pointer;
- IterCount := 0;
- Pointer := Pointer + 1;
-
- -- start iteration token search
- TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
-
- case Format(Pointer) is
-
- -- read iteration counter
- when '0' to '9' =>
- IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
- Pointer := Pointer + 1;
-
- -- expect open bracket
- when '{' =>
-
- -- initialize iteration string read
- OpenBrackets := 1;
- IterStringStart := Pointer + 1;
- Pointer := Pointer + 1;
- -- quit prematurely when iteration count is 0
- next FORMAT_SEARCH when (IterCount = 0);
-
- -- start iteration string read
- ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
-
- case Format(Pointer) is
- -- keep track of open brackets
- when '{' =>
- OpenBrackets := OpenBrackets + 1;
- Pointer := Pointer + 1;
- -- when closing bracket is found, process iteration string
- when '}' =>
- OpenBrackets := OpenBrackets - 1;
- if (OpenBrackets = 0) then
- IterStringEnd := Pointer-1;
- if (TokenStart /= 1) then
- write(L, Format(1 to TokenStart-1));
- end if;
- for i in 1 to IterCount loop
- write(L, Format(IterStringStart to IterStringEnd));
- end loop;
- if (IterStringEnd /= Format'length) then
- write(L, Format(IterStringEnd+2 to Format'length));
- end if;
- -- call expansion procedure recursively on expanded format
- FIO_FormatExpand(FMT, L.all, TokenStart);
- deallocate(L);
- return;
- end if;
- Pointer := Pointer + 1;
- -- skip escaped characters
- when '\' =>
- Pointer := Pointer + 2;
- -- read iteration string
- when others =>
- Pointer := Pointer + 1;
-
- end case;
-
- end loop ITER_STRING_READ;
-
- -- stop iteration token search when no opening bracket found
- when others =>
- Pointer := Pointer + 1;
- next FORMAT_SEARCH;
-
- end case;
-
- end loop TOKEN_READ;
-
- -- skip escaped characters
- when '\' =>
- Pointer := Pointer + 2;
-
- -- read other characters
- when others =>
- Pointer := Pointer + 1;
-
- end case;
-
- end loop FORMAT_SEARCH;
-
- write(FMT, Format);
- deallocate(L);
-
- end FIO_FormatExpand;
-
-
-
- --------------------------
- -- The fprint procedure --
- --------------------------
-
- procedure fprint
- (F: out text;
- L: inout line;
- Format: in string;
- A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
- A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
- A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
- A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
- ) is
-
- variable Pointer: integer;
- variable FMT: line;
-
- begin
-
- Pointer := 1;
-
- FIO_FormatExpand (FMT, Format, Format'low);
-
- if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
- if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
- if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
- if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
- if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
- if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
- if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
- if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
- if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
- if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
- if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
- if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
- if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
- if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
- if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
- if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
- if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
- if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
- if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
- if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
- if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
- if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
- if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
- if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
- if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
- if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
- if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
- if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
- if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
- if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
- if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
- if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
- end if; end if; end if; end if; end if; end if; end if; end if;
- end if; end if; end if; end if; end if; end if; end if; end if;
- end if; end if; end if; end if; end if; end if; end if; end if;
- end if; end if; end if; end if; end if; end if; end if; end if;
-
- FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
-
- deallocate(FMT);
-
- end fprint;
-
-
- -------------------------------------------
- -- Formatted output conversion functions --
- -------------------------------------------
-
- function fo (Arg: unsigned) return string is
- constant Argument: unsigned(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_STD_LOGIC_MAP(Argument(i));
- end loop;
- return ("U:" & Result);
- end fo;
-
- function fo (Arg: signed) return string is
- constant Argument: signed(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_STD_LOGIC_MAP(Argument(i));
- end loop;
- return ("S:" & Result);
- end fo;
-
- function fo (Arg: std_logic_vector) return string is
- constant Argument: std_logic_vector(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_STD_LOGIC_MAP(Argument(i));
- end loop;
- return ("V:" & Result);
- end fo;
-
- function fo (Arg: std_ulogic_vector) return string is
- constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_STD_LOGIC_MAP(Argument(i));
- end loop;
- return ("V:" & Result);
- end fo;
-
- function fo (Arg: bit_vector) return string is
- constant Argument: bit_vector(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_BIT_MAP(Argument(i));
- end loop;
- return ("V:" & Result);
- end fo;
-
- function fo (Arg: integer) return string is
- variable Argument: integer := Arg;
- variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
- variable Sign: character := ' ';
- begin
- if (Argument < 0) and (Argument /= integer'low) then
- Sign := '-';
- Argument := -Argument;
- end if;
- for i in Result'reverse_range loop
- Result(i) := C_DIGITS_MAP(Argument mod 10);
- Argument := Argument / 10;
- exit when (Argument = 0);
- end loop;
- return ("I:" & Sign & Result);
- end fo;
-
- function fo (Arg: std_ulogic) return string is
- begin
- return ("B:" & C_STD_LOGIC_MAP(Arg));
- end fo;
-
- function fo (Arg: bit) return string is
- begin
- return ("B:" & C_BIT_MAP(Arg));
- end fo;
-
- function fo (Arg: boolean) return string is
- begin
- if (ARG = TRUE) then
- return ("L:T");
- else
- return ("L:F");
- end if;
- end fo;
-
- function fo (Arg: character) return string is
- begin
- return ("C:" & Arg);
- end fo;
-
- -- auxilary function fgets(Arg: string)
- -- gives index until first NUL
- -- reads string from 1 to Arg'length
- function fgets (Arg: string) return integer is
- variable index: integer := Arg'length;
- begin
- for i in 1 to Arg'length loop
- if Arg(i) = NUL then
- index := i - 1;
- exit;
- else
- null;
- end if;
- end loop;
- return index;
- end fgets;
-
- function fo (Arg: string) return string is
- begin
- return Arg(1 to fgets(Arg));
- end fo;
-
- function fo (Arg: time) return string is
- begin
- return fo (integer (Arg / 1 ns));
- end fo;
-
-end PCK_FIO;
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd
deleted file mode 100644
index 9df893e..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd
+++ /dev/null
@@ -1,108 +0,0 @@
----- $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-use STD.TEXTIO.all;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
--- use IEEE.std_logic_arith.all; -- the Synopsys one
-use IEEE.numeric_std.all;
-
-package PCK_FIO is
-
-
- -- prefix string for hex output
- -- VHDL style: "X"""
- -- Verilog style: "h'"
- -- C style: "0x"
- constant FIO_h_PRE: string := "0x";
-
- -- postfix string for hex output
- -- VHDL style: """"
- constant FIO_h_POST: string := "";
-
- -- prefix string for bit vector output
- -- VHDL style: "B"""
- -- Verilog style: "b'"
- constant FIO_bv_PRE: string := "";
-
- -- postfix string for bit vector output
- -- VHDL style: """"
- constant FIO_bv_POST: string := "";
-
- -- prefix string for bit output
- -- VHDL style: "'"
- -- Verilog style: "b'"
- constant FIO_b_PRE: string := "";
-
- -- postfix string for bit output
- -- VHDL style: "'"
- constant FIO_b_POST: string := "";
-
- -- digit width for the string representation of integers
- constant FIO_d_WIDTH: integer := 10;
-
- -- bit width for the string representation of integers
- constant FIO_b_WIDTH: integer := 32;
-
- -- definition of the NIL string (default value for fprint arguments)
- -- fprint stops consuming arguments at the first NIL argument
- constant FIO_NIL: string := "\";
-
- procedure fprint
- (file F: text;
- L: inout line;
- Format: in string;
- A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
- A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
- A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
- A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
- );
-
- function fo (Arg: unsigned) return string;
- function fo (Arg: signed) return string;
- function fo (Arg: std_logic_vector) return string;
- function fo (Arg: std_ulogic_vector) return string;
- function fo (Arg: bit_vector) return string;
- function fo (Arg: integer) return string;
- function fo (Arg: std_ulogic) return string;
- function fo (Arg: bit) return string;
- function fo (Arg: boolean) return string;
- function fo (Arg: character) return string;
- function fo (Arg: string) return string;
- function fo (Arg: time) return string;
-
- procedure FIO_FormatExpand (FMT: inout line;
- Format: in string;
- StartPointer: in positive);
-
-end PCK_FIO;
-
-
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
deleted file mode 100644
index 3d123f0..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
+++ /dev/null
@@ -1,814 +0,0 @@
----- $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
- package body PCK_FIO is
-
- --------------------------
- -- FIO Warnings support --
- --------------------------
-
- procedure FIO_Warning_Fsbla (file F: text;
- L: inout line;
- Format: in string;
- Pointer: in positive) is
- begin
- fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
- "Format specifier beyond last argument\n");
- fprint (F, L, "** in format string: ""%s""\n", Format);
- fprint (F, L, "** ");
- for i in 1 to Pointer-1 loop
- fprint (F, L, "-");
- end loop;
- fprint (F, L, "^\n");
- end FIO_Warning_Fsbla;
-
- procedure FIO_Warning_Ufs (file F: text;
- L: inout line;
- Format: in string;
- Pointer: in positive;
- Char: in character) is
- begin
- fprint (F, L, "\n** Warning: FIO_PrintArg: " &
- "Unexpected format specifier '%r'\n",
- fo(Char));
- fprint (F, L, "** in format string: ""%s""\n", Format) ;
- fprint (F, L, "** ");
- for i in 1 to Pointer-1 loop
- fprint (F, L, "-");
- end loop;
- fprint (F, L, "^\n** Assuming 'q' to proceed: ");
- end FIO_Warning_Ufs;
-
-
- ----------------------------------
- -- bit conversion support --
- ----------------------------------
-
- type T_bit_map is array(bit) of character;
-
- constant C_BIT_MAP: T_bit_map
- := ('0', '1');
-
- ----------------------------------
- -- std_logic conversion support --
- ----------------------------------
-
- type T_std_logic_map is array(std_ulogic) of character;
-
- constant C_STD_LOGIC_MAP: T_std_logic_map
- := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
-
- ------------------------------
- -- Digit conversion support --
- ------------------------------
-
- -- types & constants
-
- subtype S_digit_chars is character range '0' to '9';
- subtype S_digits is integer range 0 to 9 ;
-
- type T_digit_chars_map is array(S_digit_chars) of S_digits;
-
- constant C_DIGIT_CHARS_MAP: T_digit_chars_map
- := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
-
- type T_digits_map is array(S_digits) of S_digit_chars;
-
- constant C_DIGITS_MAP: T_digits_map
- := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
-
-
- --------------------------------
- -- Decimal conversion support --
- --------------------------------
-
- -- unsigned to decimal
-
- function U_To_d (Arg: string) return integer is
- constant Argument: string(Arg'length downto 1) := Arg;
- variable Result: integer := 0;
- begin
- for i in Argument'range loop
- case Argument(i) is when '1' => Result := 2**(i-1) + Result;
- when '0' => null;
- when others => return(-1);
- end case;
- end loop;
- return (Result);
- end U_To_d;
-
- -- signed to decimal
-
- function S_To_d (Arg: string) return integer is
- constant Argument: string(Arg'length downto 1) := Arg;
- variable Result: integer := 0;
- begin
- case Argument(Argument'left) is
- when '1' => Result := - 2**(Argument'left-1);
- when '0' => Result := 0;
- when others => return (integer'low);
- end case;
- for i in Argument'left-1 downto 1 loop
- case Argument(i) is when '1' => Result := 2**(i-1) + Result;
- when '0' => null;
- when others => return(integer'low);
- end case;
- end loop;
- return (Result);
- end S_To_d;
-
- -- string to decimal
-
- function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
- constant Sign: character := Arg(1);
- constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
- variable Char: character;
- variable Result: integer := 0;
- begin
- Result := 0;
- for i in Value'range loop
- Result := Result * 10;
- Char := Value(i);
- if (Char /= ' ') then
- Result := Result + C_DIGIT_CHARS_MAP(Char);
- end if;
- end loop;
- case Sign is when '-' => return(-Result);
- when others => return(Result);
- end case;
- end I_To_d;
-
- -- boolean (0,1) to decimal
-
- function B_To_d (Arg: string(1 to 1)) return integer is
- begin
- case Arg is when "1" => return(1);
- when "0" => return(0);
- when others => return(-1);
- end case;
- end B_To_d;
-
- -- boolean (T,F) to decimal
-
- function L_To_d (Arg: string(1 to 1)) return integer is
- begin
- case Arg is when "T" => return(1);
- when others => return(0);
- end case;
- end L_To_d;
-
-
-
- ----------------------------
- -- Hex conversion support --
- ----------------------------
-
- -- Constants & types
-
- constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
-
- -- Function to return Hex index of a nibble
-
- function U_To_h_Index(Arg: string(4 downto 1)) return integer is
- variable Index: integer := 0;
- begin
- for i in Arg'range loop
- case Arg(i) is when '1' => Index := 2**(i-1) + Index;
- when '0' => null;
- when others => return (17);
- end case;
- end loop;
- return (Index+1);
- end U_To_h_Index;
-
- -- Hex conversion
-
- function U_To_h (Arg: string) return string is
- variable Result: string((Arg'length-1)/4 +1 downto 1);
- variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
- begin
- ExtArg(Arg'length downto 1) := Arg;
- for i in Result'range loop
- Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
- end loop;
- return (FIO_h_PRE & Result & FIO_h_POST);
- end U_To_h;
-
-
-
- ----------------------------
- -- Bit conversion support --
- ----------------------------
-
- function L_To_b (Arg: string(1 to 1)) return string is
- variable Result: string(1 to 1);
- begin
- case Arg is when "T" => Result := "1";
- when others => Result := "0";
- end case;
- return(FIO_b_PRE & Result & FIO_b_POST);
- end L_To_b;
-
-
- function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
- Justified: side;
- Width: integer) return string is
-
- variable IntValue: integer := I_To_d(Arg);
- variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
- variable Sign: character := ' ';
- constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
- variable BitWidth: integer range 0 to FIO_b_WIDTH;
- variable MsPos: integer range 1 to BitValue'length;
- variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
-
- begin
-
- if (IntValue < 0) then
- Sign := '-';
- IntValue := -IntValue;
- end if;
-
- for i in BitValue'reverse_range loop
- BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
- IntValue := IntValue / 2;
- exit when (IntValue = 0);
- end loop;
-
- BitValueExtended := BitValue & Blanks;
-
- if (Width = 0) or (Width > FIO_b_WIDTH+1) then
- BitWidth := FIO_b_WIDTH;
- else
- BitWidth := Width-1;
- end if;
-
- if (Justified = RIGHT) then
- return (FIO_bv_PRE &
- Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
- FIO_bv_POST);
- else
- for i in BitValue'range loop
- if BitValue(i) /= ' ' then
- MSPos := i;
- exit;
- end if;
- end loop;
- return (FIO_bv_PRE &
- Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
- FIO_bv_POST);
- end if;
-
- end I_To_b;
-
-
- -----------------------------------
- -- Reasonable conversion support --
- -----------------------------------
-
- function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
- Justified: side;
- Width: integer) return string is
- constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
- constant Sign: character := Arg(1);
- constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
- variable IntWidth: integer range 0 to FIO_d_WIDTH;
- variable MsPos: integer range 1 to Value'length;
- variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
- begin
- if (Width = 0) or (Width > FIO_d_WIDTH+1) then
- IntWidth := FIO_d_WIDTH;
- else
- IntWidth := Width-1;
- end if;
- if (Justified = RIGHT) then
- return (Sign & Value(Value'length-IntWidth+1 to Value'length));
- else
- for i in Value'range loop
- if Value(i) /= ' ' then
- MSPos := i;
- exit;
- end if;
- end loop;
- return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
- end if;
- end I_To_r;
-
-
- -------------------------------------------
- -- Reasonable output conversion function --
- -------------------------------------------
-
- function ReasonableOutput (Arg: string;
- Justified: side;
- Width: integer) return string is
- constant Argument: string(1 to Arg'length) := Arg;
- constant TypeSpec: string (1 to 2) := Argument(1 to 2);
- constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
- begin
- case TypeSpec is
- when "U:" | "S:" | "V:" =>
- return U_To_h(Value);
- when "I:" =>
- return I_To_r(Value, Justified, Width);
- when "B:" | "L:" | "C:" =>
- return Value;
- when others =>
- return Argument;
- end case;
-
- end ReasonableOutput;
-
-
- ------------------------------------
- -- Bit output conversion function --
- ------------------------------------
-
- function BitOutput (Arg: string;
- Justified: side;
- Width: integer) return string is
- constant Argument: string(1 to Arg'length) := Arg;
- constant TypeSpec: string (1 to 2) := Argument(1 to 2);
- constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
- begin
- case TypeSpec is
- when "U:" | "S:" | "V:" =>
- return (FIO_bv_PRE & Value & FIO_bv_POST);
- when "B:" =>
- -- Value(1 to 1) instead of Value for LeapFrog
- return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
- when "I:" =>
- return I_To_b(Value, Justified, Width);
- when "L:" =>
- -- Value(1 to 1) instead of Value for LeapFrog
- return L_To_b(Value(1 to 1));
- when others =>
- return Argument;
- end case;
-
- end BitOutput;
-
-
- -------------------------------------------
- -- Decimal output conversion function --
- -------------------------------------------
-
- function DecimalOutput (Arg: string) return integer is
- constant Argument: string(1 to Arg'length) := Arg;
- constant TypeSpec: string (1 to 2) := Argument(1 to 2);
- constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
- begin
- case TypeSpec is
- when "U:"| "V:" =>
- return U_To_d(Value);
- when "S:" =>
- return S_To_d(Value);
- when "I:" =>
- return I_To_d(Value);
- when "B:" =>
- return B_To_d(Value);
- when "L:" =>
- return L_To_d(Value);
- when others =>
- return integer'low;
- end case;
-
- end DecimalOutput;
-
-
- ----------------------------
- -- Atomic print functions --
- ----------------------------
-
- -- test for end of format string
-
- function FIO_EOS (Format: in string;
- Pointer: in integer)
- return boolean is
- begin
- return (Pointer > Format'length);
- end FIO_EOS;
-
-
- -- Atomic value print function
-
- procedure FIO_PrintValue (file F: text;
- L: inout line;
- Format: in string;
- Pointer: inout integer;
- Last: in boolean := FALSE) is
- variable Char: character;
- begin
- while (not FIO_EOS(Format, Pointer)) loop
- Char := Format(Pointer);
- case Char is
- when '\' =>
- Pointer := Pointer + 1;
- exit when (FIO_EOS(Format, Pointer));
- Char := Format(Pointer);
- case Char is when 'n' => writeline(F, L);
- when others => write(L, Char);
- end case;
- when '%' =>
- if Last then
- FIO_Warning_Fsbla(F, L, Format, Pointer);
- end if;
- Pointer := Pointer + 1;
- exit;
- when others =>
- write(L, char);
- end case;
- Pointer := Pointer + 1;
- end loop;
- end FIO_PrintValue;
-
-
- ---- Atomic argument print function
-
- procedure FIO_PrintArg (file F: text;
- L: inout line;
- Format: in string;
- Pointer: inout integer;
- Arg: in string) is
- variable Char: character;
- variable Justified: side;
- variable Width: integer;
-
- begin
-
- FIO_PrintValue(F, L, Format, Pointer);
-
- Justified := RIGHT;
- Width := 0;
- while (not FIO_EOS(Format, Pointer)) loop
- Char := Format(Pointer);
- case Char is
- when '-' =>
- Justified := LEFT;
- Pointer := Pointer + 1;
- when '0' to '9' =>
- Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
- Pointer := Pointer + 1;
- when 'r' =>
- write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
- Pointer := Pointer + 1;
- exit;
- when 'b' =>
- write(L, BitOutput(Arg, Justified, Width), Justified, Width);
- Pointer := Pointer + 1;
- exit;
- when 'd' =>
- write(L, DecimalOutput(Arg), Justified, Width);
- Pointer := Pointer + 1;
- exit;
- when 'q' | 's' =>
- write(L, Arg, Justified, Width);
- Pointer := Pointer + 1;
- exit;
- when others =>
- FIO_Warning_Ufs(F, L, Format, Pointer, Char);
- write(L, Arg, Justified, Width);
- Pointer := Pointer + 1;
- exit;
- end case;
- end loop;
- end FIO_PrintArg;
-
-
- -----------------------------------------------------
- -- The format string iteration expansion procedure --
- -----------------------------------------------------
-
- procedure FIO_FormatExpand (FMT: inout line;
- Format: in string;
- StartPointer: in positive) is
-
- variable Pointer: positive := StartPointer;
- variable TokenStart: positive;
- variable IterStringStart: positive;
- variable IterStringEnd: positive;
- variable IterCount: natural;
- variable OpenBrackets: natural;
- variable L: line;
-
- begin
-
- FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
-
- case Format(Pointer) is
-
- -- look for format specifier
- when '%' =>
-
- -- initialize iteration token search
- TokenStart := Pointer;
- IterCount := 0;
- Pointer := Pointer + 1;
-
- -- start iteration token search
- TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
-
- case Format(Pointer) is
-
- -- read iteration counter
- when '0' to '9' =>
- IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
- Pointer := Pointer + 1;
-
- -- expect open bracket
- when '{' =>
-
- -- initialize iteration string read
- OpenBrackets := 1;
- IterStringStart := Pointer + 1;
- Pointer := Pointer + 1;
- -- quit prematurely when iteration count is 0
- next FORMAT_SEARCH when (IterCount = 0);
-
- -- start iteration string read
- ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
-
- case Format(Pointer) is
- -- keep track of open brackets
- when '{' =>
- OpenBrackets := OpenBrackets + 1;
- Pointer := Pointer + 1;
- -- when closing bracket is found, process iteration string
- when '}' =>
- OpenBrackets := OpenBrackets - 1;
- if (OpenBrackets = 0) then
- IterStringEnd := Pointer-1;
- if (TokenStart /= 1) then
- write(L, Format(1 to TokenStart-1));
- end if;
- for i in 1 to IterCount loop
- write(L, Format(IterStringStart to IterStringEnd));
- end loop;
- if (IterStringEnd /= Format'length) then
- write(L, Format(IterStringEnd+2 to Format'length));
- end if;
- -- call expansion procedure recursively on expanded format
- FIO_FormatExpand(FMT, L.all, TokenStart);
- deallocate(L);
- return;
- end if;
- Pointer := Pointer + 1;
- -- skip escaped characters
- when '\' =>
- Pointer := Pointer + 2;
- -- read iteration string
- when others =>
- Pointer := Pointer + 1;
-
- end case;
-
- end loop ITER_STRING_READ;
-
- -- stop iteration token search when no opening bracket found
- when others =>
- Pointer := Pointer + 1;
- next FORMAT_SEARCH;
-
- end case;
-
- end loop TOKEN_READ;
-
- -- skip escaped characters
- when '\' =>
- Pointer := Pointer + 2;
-
- -- read other characters
- when others =>
- Pointer := Pointer + 1;
-
- end case;
-
- end loop FORMAT_SEARCH;
-
- write(FMT, Format);
- deallocate(L);
-
- end FIO_FormatExpand;
-
-
-
- --------------------------
- -- The fprint procedure --
- --------------------------
-
- procedure fprint
- (file F: text;
- L: inout line;
- Format: in string;
- A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
- A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
- A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
- A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
- ) is
-
- variable Pointer: integer;
- variable FMT: line;
-
- begin
-
- Pointer := 1;
-
- FIO_FormatExpand (FMT, Format, Format'low);
-
- if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
- if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
- if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
- if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
- if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
- if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
- if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
- if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
- if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
- if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
- if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
- if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
- if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
- if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
- if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
- if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
- if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
- if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
- if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
- if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
- if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
- if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
- if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
- if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
- if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
- if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
- if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
- if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
- if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
- if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
- if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
- if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
- end if; end if; end if; end if; end if; end if; end if; end if;
- end if; end if; end if; end if; end if; end if; end if; end if;
- end if; end if; end if; end if; end if; end if; end if; end if;
- end if; end if; end if; end if; end if; end if; end if; end if;
-
- FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
-
- deallocate(FMT);
-
- end fprint;
-
-
- -------------------------------------------
- -- Formatted output conversion functions --
- -------------------------------------------
-
- function fo (Arg: unsigned) return string is
- constant Argument: unsigned(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_STD_LOGIC_MAP(Argument(i));
- end loop;
- return ("U:" & Result);
- end fo;
-
- function fo (Arg: signed) return string is
- constant Argument: signed(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_STD_LOGIC_MAP(Argument(i));
- end loop;
- return ("S:" & Result);
- end fo;
-
- function fo (Arg: std_logic_vector) return string is
- constant Argument: std_logic_vector(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_STD_LOGIC_MAP(Argument(i));
- end loop;
- return ("V:" & Result);
- end fo;
-
- function fo (Arg: std_ulogic_vector) return string is
- constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_STD_LOGIC_MAP(Argument(i));
- end loop;
- return ("V:" & Result);
- end fo;
-
- function fo (Arg: bit_vector) return string is
- constant Argument: bit_vector(1 to Arg'length) := Arg;
- variable Result: string(1 to Arg'length);
- begin
- for i in Argument'range loop
- Result(i) := C_BIT_MAP(Argument(i));
- end loop;
- return ("V:" & Result);
- end fo;
-
- function fo (Arg: integer) return string is
- variable Argument: integer := Arg;
- variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
- variable Sign: character := ' ';
- begin
- if (Argument < 0) and (Argument /= integer'low) then
- Sign := '-';
- Argument := -Argument;
- end if;
- for i in Result'reverse_range loop
- Result(i) := C_DIGITS_MAP(Argument mod 10);
- Argument := Argument / 10;
- exit when (Argument = 0);
- end loop;
- return ("I:" & Sign & Result);
- end fo;
-
- function fo (Arg: std_ulogic) return string is
- begin
- return ("B:" & C_STD_LOGIC_MAP(Arg));
- end fo;
-
- function fo (Arg: bit) return string is
- begin
- return ("B:" & C_BIT_MAP(Arg));
- end fo;
-
- function fo (Arg: boolean) return string is
- begin
- if (ARG = TRUE) then
- return ("L:T");
- else
- return ("L:F");
- end if;
- end fo;
-
- function fo (Arg: character) return string is
- begin
- return ("C:" & Arg);
- end fo;
-
- -- auxilary function fgets(Arg :string)
- -- returns index of first NUL in Arg or if no NUL is present just Arg'length
- -- goes through Arg from 1 to Arg'length
- function fgets (Arg: string) return integer is
- variable index: integer := Arg'length;
- begin
- for i in 1 to Arg'length loop
- if Arg(i) = NUL then
- index := i - 1;
- exit;
- else
- null;
- end if;
- end loop;
- return index;
- end fgets;
-
- -- returns the Arg string until the first NUL was encountered
- -- if fo is used on a string with NUL in it it will stop reading the rest
- -- of the string, even if a larger field width has been supplied. fo will
- -- then just pad the remaining characters with blanco's
- function fo (Arg: string) return string is
- begin
- return Arg(1 to fgets(Arg));
- end fo;
-
- function fo (Arg: time) return string is
- begin
- return fo (integer (Arg / 1 ns));
- end fo;
-
-end PCK_FIO;
-
diff --git a/lib/PCK_FIO-2002.7/README b/lib/PCK_FIO-2002.7/README
deleted file mode 100644
index b16c6c5..0000000
--- a/lib/PCK_FIO-2002.7/README
+++ /dev/null
@@ -1,88 +0,0 @@
----- $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-Version 2002.07
-===============
-
-Contents
-========
-
-This distribution contains the following files:
-
- PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package
- PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package
- PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package
- PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package
- TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO
- TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO
- PCK_FIO.out.gold: Certified test bench output
- PCK_FIO.html: Manual for PCK_FIO in html format
- README: This file
-
-
-Installation
-============
-
-VHDL-1987
----------
-To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
-analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library.
-
-To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library.
-
-VHDL-1993
----------
-To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
-analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library.
-
-To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library.
-
-Numeric packages
-----------------
-If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need
-to edit the source code of the package, both header and body, and the test bench
-and replace the package use clause. PCK_FIO works with either of these packages.
-
-Documentation
--------------
-To install the documentation, put the file point PCK_FIO.html in a path of
-your choosing, point your web browser to it, and bookmark it.
-
-
-Installation check
-==================
-
-After installing the test bench, you should run it. The corresponding VHDL
-design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
-
-Simulating the test bench should create a file called PCK_FIO.out. This file
-should be identical to PCK_FIO.out.gold. Any difference indicates a portability
-issue or a simulator non-compliance or bug.
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd
deleted file mode 100644
index 2e18ff4..0000000
--- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd
+++ /dev/null
@@ -1,531 +0,0 @@
----- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
--- use IEEE.std_logic_arith.all; -- the Synopsys one
- use IEEE.numeric_std.all;
-
-use STD.TEXTIO.all;
-
-library EASICS_PACKAGES;
-use EASICS_PACKAGES.PCK_FIO.all;
-
-entity TBE_PCK_FIO is
-
-end TBE_PCK_FIO;
-
-architecture TB of TBE_PCK_FIO is
-
-begin
-
-USAGE: process
-
- file RESULT: text is out "PCK_FIO.out";
- variable L: line;
- variable Pointer: integer;
- variable BoolTrue: boolean := TRUE;
- variable BoolFalse: boolean := FALSE;
- variable IntPos: integer := 5678;
- variable BigIntPos: integer := 12345678;
- variable IntNeg: integer := -8765;
- variable BigIntNeg: integer := -87654321;
- variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
- variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
- variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
- variable SigPos: signed(6 downto 0) := signed'("0010010");
- variable SigNeg: signed(6 downto 0) := signed'("1010010");
- variable BitX: std_logic := 'X';
- variable Bit1: std_logic := '1';
- variable Bit0: std_logic := '0';
-
- variable parameter_1: integer := 1234;
- variable parameter_2: integer := 2345;
- variable parameter_3: integer := 4567;
-
- constant TempString: string :="ABC" & NUL & "DEF";
-begin
-
-fprint(RESULT, L,
- "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
- "-----------------------------------------\n\n" &
- "This is the result of running the PCK_FIO testbench.\n" &
- "This file should be compared with PCK_FIO.out.gold, which is\n" &
- "the reference output. Any difference indicates a portability\n" &
- "issue or a simulator non-compliance or bug.\n\n"
- );
-
-
-fprint(RESULT, L,
- "\n--------------------\n" &
- "-- Basic features --\n" &
- "--------------------\n\n"
- );
-
-fprint(RESULT, L,
- "-- First some auxiliary declarations\n"
- );
-
-fprint(RESULT, L,
- "> file RESULT: text is out ""PCK_FIO.out"";\n" &
- "> variable L: line;\n" &
- "> variable BoolTrue: boolean := TRUE;\n" &
- "> variable BoolFalse: boolean := FALSE;\n" &
- "> variable IntPos: integer := 5678;\n" &
- "> variable BigIntPos: integer := 12345678;\n" &
- "> variable IntNeg: integer := -8765;\n" &
- "> variable BigIntNeg: integer := -87654321;\n" &
- "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
- "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
- "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
- "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
- "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
- "> variable BitX: std_logic := 'X';\n" &
- "> variable Bit1: std_logic := '1';\n" &
- "> variable Bit0: std_logic := '0';\n" &
- "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
-);
-
-
-fprint(RESULT, L,
- "\n\n-- fprint call with no arguments\n" &
- "> fprint(RESULT, L, ""No arguments.\\n"");\n"
- );
-fprint(RESULT, L, "No arguments.\n");
-
-
-fprint(RESULT, L,
- "\n-- Special characters need to be escaped\n" &
- "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
- );
-
-fprint(RESULT, L, "Special characters: \% \\ "" \n");
-
-
-fprint(RESULT, L,
- "\n-- Various format specifiers interprete the same object differently\n" &
- "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
- "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
- "> );\n"
- );
-
-fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
- fo(Uns), fo(Uns), fo(Uns), fo(Uns)
- );
-
-fprint(RESULT, L,
- "\n-- Format string can be shortened by using the iteration specifier\n" &
- "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
- "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
- "> );\n"
- );
-
-fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
- fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
- );
-fprint(RESULT, L,
- "\n-------------------------------\n"&
- "--Testing string manipulation--\n"&
- "-------------------------------\n");
-fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
- & " & NUL & ""DEF""\n");
--- temp_string: string:="ABC"&NUL&"DEF"
--- test for detecting NUL in string
-fprint(RESULT, L, "\n--test for NUL ending in strings\n");
-fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
-fprint(RESULT, L, fo(TempString));
-
--- direct inclusion of string in fprint should give whole string
-fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
-fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
-fprint(RESULT, L, TempString & "\n");
-
--- influence of given width
-
-fprint(RESULT, L, "\n--if there are less characters in the given string then"
- & " in the width fo will\n"&
- "-- pad the remaining with blanco's according to the given justification\n");
-fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
-fprint(RESULT, L, "%5s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
-fprint(RESULT, L, "%-5s",fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
-fprint(RESULT, L, "%9s", TempString);
-fprint(RESULT, L, "\n\n-- if the width is smaller then the number" &
- " of characters in the string fprint\n" &
- "-- will output the string with the minimum of characters needed\n");
-fprint(RESULT, L, "\n--with specified width,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
-fprint(RESULT, L, "%2s",fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
-fprint(RESULT, L, "%4s", TempString);
-
-
-fprint(RESULT, L,
- "\n\n------------------------------------\n" &
- "-- Support for bit-oriented types --\n" &
- "------------------------------------\n"
- );
-
-fprint (RESULT, L, "\n-- Reasonable format\n" &
- "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
- "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
- "> );\n"
- );
-
-
-fprint(RESULT, L, "Reasonable format: %9{%r }\n",
- fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
- fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
- );
-
-fprint (RESULT, L, "\n-- Decimal format\n" &
- "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
- "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
- "> );\n"
- );
-
-
-fprint(RESULT, L, "Decimal format: %9{%d }\n",
- fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
- fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
- );
-
-fprint (RESULT, L, "\n-- Bit format\n" &
- "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
- "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
- "> );\n"
- );
-
-
-fprint(RESULT, L, "Bit format: %9{%b }\n",
- fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
- fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
- );
-
-fprint(RESULT, L,
- "\n\n" &
- "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n"
- );
-
-
-fprint(RESULT, L, "\n" &
- "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
-
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-
-fprint(RESULT, L,
- "\n-------------------------------\n" &
- "-- Support for integer types --\n" &
- "-------------------------------\n"
- );
-
-fprint(RESULT, L,
- "\n\n" &
- "-- Template of the call: ( stands for the format specifier)\n"
- );
-
-
-fprint(RESULT, L, "\n" &
- "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" &
- "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
-
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-
-fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-fprint(RESULT, L,
- "\n----------------------\n" &
- "-- Support for time --\n" &
- "----------------------\n"
- );
-
-fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
- "-- into an integer value (of nanoseconds)\n"
- );
-fprint (RESULT, L, "> wait for 648 ns\n");
-fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
-
-wait for 648 ns;
-
-fprint (RESULT, L, "The time is now %d ns\n", fo(now));
-
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Erroneous calls and error messages --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
- "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L, "-- Unsupported format specifier\n" &
- "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
- "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Things you wouldn't expect to work --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Nested iteration\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
-fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-
-wait;
-
-end process USAGE;
-
-end TB;
-
-
diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd
deleted file mode 100644
index 0386a11..0000000
--- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd
+++ /dev/null
@@ -1,536 +0,0 @@
----- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
--- use IEEE.std_logic_arith.all; -- the Synopsys one
-use IEEE.numeric_std.all;
-
-use STD.TEXTIO.all;
-
-library EASICS_PACKAGES;
-use EASICS_PACKAGES.PCK_FIO.all;
-
-entity TBE_PCK_FIO is
-
-end TBE_PCK_FIO;
-
-architecture TB of TBE_PCK_FIO is
-
-begin
-
-USAGE: process
-
- file RESULT: text open write_mode is "PCK_FIO.out";
- variable L: line;
- variable Pointer: integer;
- variable BoolTrue: boolean := TRUE;
- variable BoolFalse: boolean := FALSE;
- variable IntPos: integer := 5678;
- variable BigIntPos: integer := 12345678;
- variable IntNeg: integer := -8765;
- variable BigIntNeg: integer := -87654321;
- variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
- variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
- variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
- variable SigPos: signed(6 downto 0) := signed'("0010010");
- variable SigNeg: signed(6 downto 0) := signed'("1010010");
- variable BitX: std_logic := 'X';
- variable Bit1: std_logic := '1';
- variable Bit0: std_logic := '0';
-
- variable parameter_1: integer := 1234;
- variable parameter_2: integer := 2345;
- variable parameter_3: integer := 4567;
-
- constant TempString: string :="ABC" & NUL & "DEF";
-begin
-
-fprint(RESULT, L,
- "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
- "-----------------------------------------\n\n" &
- "This is the result of running the PCK_FIO testbench.\n" &
- "This file should be compared with PCK_FIO.out.gold, which is\n" &
- "the reference output. Any difference indicates a portability\n" &
- "issue or a simulator non-compliance or bug.\n\n"
- );
-
-
-fprint(RESULT, L,
- "\n--------------------\n" &
- "-- Basic features --\n" &
- "--------------------\n\n"
- );
-
-fprint(RESULT, L,
- "-- First some auxiliary declarations\n"
- );
-
-fprint(RESULT, L,
- "> file RESULT: text is out ""PCK_FIO.out"";\n" &
- "> variable L: line;\n" &
- "> variable BoolTrue: boolean := TRUE;\n" &
- "> variable BoolFalse: boolean := FALSE;\n" &
- "> variable IntPos: integer := 5678;\n" &
- "> variable BigIntPos: integer := 12345678;\n" &
- "> variable IntNeg: integer := -8765;\n" &
- "> variable BigIntNeg: integer := -87654321;\n" &
- "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
- "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
- "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
- "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
- "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
- "> variable BitX: std_logic := 'X';\n" &
- "> variable Bit1: std_logic := '1';\n" &
- "> variable Bit0: std_logic := '0';\n" &
- "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
-);
-
-
-fprint(RESULT, L,
- "\n\n-- fprint call with no arguments\n" &
- "> fprint(RESULT, L, ""No arguments.\\n"");\n"
- );
-fprint(RESULT, L, "No arguments.\n");
-
-
-fprint(RESULT, L,
- "\n-- Special characters need to be escaped\n" &
- "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
- );
-
-fprint(RESULT, L, "Special characters: \% \\ "" \n");
-
-
-fprint(RESULT, L,
- "\n-- Various format specifiers interprete the same object differently\n" &
- "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
- "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
- "> );\n"
- );
-
-fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
- fo(Uns), fo(Uns), fo(Uns), fo(Uns)
- );
-
-fprint(RESULT, L,
- "\n-- Format string can be shortened by using the iteration specifier\n" &
- "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
- "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
- "> );\n"
- );
-
-fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
- fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
- );
-fprint(RESULT, L,
- "\n-------------------------------\n"&
- "--Testing string manipulation--\n"&
- "-------------------------------\n");
-fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
- & " & NUL & ""DEF""\n");
--- TempString: string:="ABC" & NUL & "DEF"
--- test for detecting NUL in string
-fprint(RESULT, L ,"\n--test for NUL ending in strings\n");
-fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
-fprint(RESULT, L, fo(TempString));
-
--- direct inclusion of string in fprint should give whole string
-fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
-fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
-fprint(RESULT, L, TempString & "\n");
-
--- influence of given width
-
-fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"&
- "-- pad the remaining with blanco's according to the given justification\n");
-fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
-fprint(RESULT, L, "%5s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
-fprint(RESULT, L, "%-5s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
-fprint(RESULT, L, "%9s", TempString);
-fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"&
- "-- will output the string with the minimum of characters needed\n");
-fprint(RESULT, L, "\n--with specified width,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
-fprint(RESULT, L, "%2s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
-fprint(RESULT, L, "%4s", TempString);
-
-fprint(RESULT, L,
- "\n\n------------------------------------\n" &
- "-- Support for bit-oriented types --\n" &
- "------------------------------------\n"
- );
-
-fprint (RESULT, L, "\n-- Reasonable format\n" &
- "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
- "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
- "> );\n"
- );
-
-
-fprint(RESULT, L, "Reasonable format: %9{%r }\n",
- fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
- fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
- );
-
-fprint (RESULT, L, "\n-- Decimal format\n" &
- "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
- "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
- "> );\n"
- );
-
-
-fprint(RESULT, L, "Decimal format: %9{%d }\n",
- fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
- fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
- );
-
-fprint (RESULT, L, "\n-- Bit format\n" &
- "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
- "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
- "> );\n"
- );
-
-
-fprint(RESULT, L, "Bit format: %9{%b }\n",
- fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
- fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
- );
-
-fprint(RESULT, L,
- "\n\n" &
- "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n"
- );
-
-
-fprint(RESULT, L, "\n" &
- "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-
-fprint(RESULT, L,
- "\n-------------------------------\n" &
- "-- Support for integer types --\n" &
- "-------------------------------\n"
- );
-
-fprint(RESULT, L,
- "\n\n" &
- "-- Template of the call: ( stands for the format specifier)\n"
- );
-
-
-fprint(RESULT, L, "\n" &
- "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" &
- "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
-
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-
-fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-fprint(RESULT, L,
- "\n----------------------\n" &
- "-- Support for time --\n" &
- "----------------------\n"
- );
-
-fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
- "-- into an integer value (of nanoseconds)\n"
- );
-fprint (RESULT, L, "> wait for 648 ns\n");
-fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
-
-wait for 648 ns;
-
-fprint (RESULT, L, "The time is now %d ns\n", fo(now));
-
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Erroneous calls and error messages --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
- "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L, "-- Unsupported format specifier\n" &
- "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
- "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Things you wouldn't expect to work --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Nested iteration\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
-fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-
-wait;
-
-end process USAGE;
-
-end TB;
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987
deleted file mode 100644
index c5a4a92..0000000
--- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987
+++ /dev/null
@@ -1,34 +0,0 @@
-### msMakefile generated by vma on Thu Oct 4 17:33:56 CEST 2001
-
-ANALYZER = vcom -quiet -nologo
-ANALYZER_C = vcom -quiet -nologo
-all : \
- bin/tbe_pck_fio/tb.dat \
- bin/tbe_pck_fio/_primary.dat
-
-# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB)
-# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO
-
-bin/tbe_pck_fio/tb.dat \
-bin/tbe_pck_fio/_primary.dat : \
- bin/pck_fio/body.dat \
- bin/pck_fio/_primary.dat \
- TB_PCK_FIO_1987.vhd
- ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1987.vhd
-
-
-# Prerequisites for package body EASICS_PACKAGES.PCK_FIO()
-
-bin/pck_fio/body.dat : \
- bin/pck_fio/_primary.dat \
- PCK_FIO_1987_BODY.vhd
- ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1987_BODY.vhd
-
-
-# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO
-
-bin/pck_fio/_primary.dat : \
- PCK_FIO_1987.vhd
- ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1987.vhd
-
-
diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993
deleted file mode 100644
index 0f9a351..0000000
--- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993
+++ /dev/null
@@ -1,34 +0,0 @@
-### msMakefile generated by vma on Thu Oct 4 17:32:23 CEST 2001
-
-ANALYZER = vcom -quiet -nologo -93
-ANALYZER_C = vcom -quiet -nologo -93
-all : \
- bin/tbe_pck_fio/tb.dat \
- bin/tbe_pck_fio/_primary.dat
-
-# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB)
-# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO
-
-bin/tbe_pck_fio/tb.dat \
-bin/tbe_pck_fio/_primary.dat : \
- bin/pck_fio/body.dat \
- bin/pck_fio/_primary.dat \
- TB_PCK_FIO_1993.vhd
- ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1993.vhd
-
-
-# Prerequisites for package body EASICS_PACKAGES.PCK_FIO()
-
-bin/pck_fio/body.dat : \
- bin/pck_fio/_primary.dat \
- PCK_FIO_1993_BODY.vhd
- ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1993_BODY.vhd
-
-
-# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO
-
-bin/pck_fio/_primary.dat : \
- PCK_FIO_1993.vhd
- ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1993.vhd
-
-
diff --git a/lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd b/lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd
deleted file mode 100644
index 63a59d4..0000000
Binary files a/lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd and /dev/null differ
diff --git a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj b/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj
deleted file mode 100644
index ba54b14..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj
+++ /dev/null
@@ -1,13 +0,0 @@
-vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_config.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\dpram.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo
deleted file mode 100644
index 1f30d78..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl.wdo}
-view wave
-view structure
-view signals
-run 800us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo
deleted file mode 100644
index 4a9d3f1..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo
+++ /dev/null
@@ -1,93 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_full
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_re
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_we
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {14963876 ps} 0}
-configure wave -namecolwidth 184
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {14733925 ps} {15711632 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo
deleted file mode 100644
index 4de7283..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_fifo.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl_fifo
-do {tb_sdr_ctrl_fifo.wdo}
-view wave
-view structure
-view signals
-run 20us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo
deleted file mode 100644
index bd233a2..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo
+++ /dev/null
@@ -1,68 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/rst_out
-add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_we_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_addr
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_busy
-add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_cmd_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_r
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_data_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_w
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_rd
-add wave -noupdate -divider {Read FIFO}
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_re
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/read_fifo_dout
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/was_write
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pr
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pr_next
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pw
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pw_next
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/fifo_full
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/fifo_empty
-add wave -noupdate -divider {Write FIFO}
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_w
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/re
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_full
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pr
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pr_next
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pw
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pw_next
-add wave -noupdate -divider {Command FIFO}
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_w
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/re
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_fifo_sync_ctrl/fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_fifo_sync_ctrl/fifo_full
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {13893123 ps} 0}
-configure wave -namecolwidth 172
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {13879998 ps} {13928553 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo
deleted file mode 100644
index 7d046f8..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_lin_r_rand_w.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_lin_r_rand_w.wdo}
-view wave
-view structure
-view signals
-run 1200us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo
deleted file mode 100644
index 542c24b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo
+++ /dev/null
@@ -1,87 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {21725359 ps} {22204052 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo
deleted file mode 100644
index d3d9e2b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_lin_w_rand_r.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_lin_w_rand_r.wdo}
-view wave
-view structure
-view signals
-run 1200us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo
deleted file mode 100644
index 542c24b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo
+++ /dev/null
@@ -1,87 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {21725359 ps} {22204052 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo
deleted file mode 100644
index 832ec1b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_rand_addr.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_rand_rw.wdo}
-view wave
-view structure
-view signals
-run 1000us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo
deleted file mode 100644
index eb20b08..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo
+++ /dev/null
@@ -1,82 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {60573747 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {60552548 ps} {60600861 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo
deleted file mode 100644
index 0e41aef..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_rand_rw.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_rand_rw.wdo}
-view wave
-view structure
-view signals
-run 10000us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo
deleted file mode 100644
index e3087e6..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo
+++ /dev/null
@@ -1,84 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {16004147 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {15914249 ps} {16324366 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo
deleted file mode 100644
index b3be3ab..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo
+++ /dev/null
@@ -1,28 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_frontend.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdram_ctrl_frontend.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdram_ctrl_frontend
-do {tb_sdram_ctrl_frontend.wdo}
-view wave
-view structure
-view signals
-run 40us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo
deleted file mode 100644
index 5d5538e..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo
+++ /dev/null
@@ -1,48 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/addr
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/busy
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/en
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/r_wn
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/din
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/be
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/dout_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout_reg
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/clk_out
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cs_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_we_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_ras_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cas_n
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_ba
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_data
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_busy
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/sdr_cmd_busy
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/cat_fifo_full
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/write_fifo_full
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/read_fifo_full
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_dm_rd_in
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_dm_rd_out
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_data_vld
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {27802417 ps} 0}
-configure wave -namecolwidth 172
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {27712165 ps} {27944343 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd
deleted file mode 100644
index c924c8c..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd
+++ /dev/null
@@ -1,240 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Clock generator (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library ieee, work;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity clockgen is
- generic
- (
- read_phaseshift : integer := 0;
- frequency_hz : integer := 100E6
- );
- port
- (
- -- Clocks and Reset
- rst : in std_logic; -- external async reset, low active
- clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
- clk_fb_in : in std_logic; -- feedback clock
- read_clk0_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 0°
- read_clk270_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 270°
- sys_clk0_out : out std_logic; -- System clock, dcm#0 output 0°
- sys_clk270_out : out std_logic; -- System clock, dcm#0 output 270°
- locked_out : out std_logic; -- DCM locked status
- error_out : out std_logic -- indicates DCM Errors
- );
-
-end;
-
-architecture tech of clockgen is
-
- constant CLKIN_PER : real := real(1000E6/frequency_hz);
-
- signal locked : unsigned(1 downto 0);
- signal dcm_rst : unsigned(1 downto 0);
- signal read_clk0 : std_logic;
- signal read_clk270 : std_logic;
- signal read_clk0_bufg : std_logic;
- signal read_clk270_bufg : std_logic;
- signal sys_clk0 : std_logic;
- signal sys_clk270 : std_logic;
- signal sys_clk0_bufg : std_logic;
- signal sys_clk270_bufg : std_logic;
- signal dcm1_locked, dcm2_locked : unsigned(2 downto 0);
- signal cnt_q : unsigned(4 downto 0);
-
- type STATE_TYPE is (s0, s1, s2, s3, s4);
- signal state_q : STATE_TYPE;
-
-begin
-
- read_clk0_out <= read_clk0_bufg;
- read_clk270_out <= read_clk270_bufg;
- sys_clk0_out <= sys_clk0_bufg;
- sys_clk270_out <= sys_clk270_bufg;
-
-bufg11: bufg
- port map
- (
- o => sys_clk0_bufg,
- i => sys_clk0
- );
-
-bufg12: bufg
- port map (
- o => sys_clk270_bufg,
- i => sys_clk270
- );
-
-bufg13: bufg
- port map
- (
- o => read_clk0_bufg,
- i => read_clk0
- );
-
-bufg14: bufg
- port map (
- o => read_clk270_bufg,
- i => read_clk270
- );
-
- -------------------------------------------------------------------------------------------------------
- -- Clock generation
- -------------------------------------------------------------------------------------------------------
-
-inst_DCM_BASE_0 : DCM_BASE
- generic map (
- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
- -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
- CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
- CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
- CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
- CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
- DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
- DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
- -- an integer from 0 to 15
- DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
- DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
- FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
- STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
- port map (
- CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput
- CLK180 => open, -- 180 degree DCM CLK output
- CLK270 => sys_clk270, -- 270 degree DCM CLK output
- CLK2X => open, -- 2X DCM CLK output
- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
- CLK90 => open, -- 90 degree DCM CLK output
- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
- CLKFX => open, -- DCM CLK synthesis out (M/D)
- CLKFX180 => open, -- 180 degree CLK synthesis out
- LOCKED => locked(0), -- DCM LOCK status output
- CLKFB => clk_fb_in, -- DCM clock feedback
- CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
- RST => dcm_rst(0) -- DCM asynchronous reset input
- );
-
- inst_DCM_BASE_1 : DCM_BASE
- generic map (
- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
- -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
- CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
- CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
- CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
- CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
- DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
- DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
- -- an integer from 0 to 15
- DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
- DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
- FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
- PHASE_SHIFT => read_phaseshift, -- Amount of fixed phase shift from -255 to 1023
- STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
- port map (
- CLK0 => read_clk0, -- 0 degree DCM CLK ouptput
- CLK180 => open, -- 180 degree DCM CLK output
- CLK270 => read_clk270, -- 270 degree DCM CLK output
- CLK2X => open, -- 2X DCM CLK output
- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
- CLK90 => open, -- 90 degree DCM CLK output
- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
- CLKFX => open, -- DCM CLK synthesis out (M/D)
- CLKFX180 => open, -- 180 degree CLK synthesis out
- LOCKED => locked(1), -- DCM LOCK status output
- CLKFB => read_clk0_bufg, -- DCM clock feedback
- CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
- RST => dcm_rst(1) -- DCM asynchronous reset input
- );
-
- dcm_rst(1) <= not locked(0);
-
-dcm_fsm:
- process(rst, clk_in)
- begin
- if rst = '1' then
- state_q <= s0;
- dcm_rst(0) <= '0';
- cnt_q <= "11111";
- error_out <= '0';
- locked_out <= '0';
- dcm1_locked <= (others => '0');
- dcm2_locked <= (others => '0');
- elsif rising_edge(clk_in) then
- case state_q is
- when s0 =>
- state_q <= s1;
-
- when s1 =>
- cnt_q <= cnt_q - 1;
- if cnt_q = 0 then
- dcm_rst(0) <= '1';
- state_q <= s2;
- end if;
-
- when s2 =>
- cnt_q <= cnt_q - 1;
- if cnt_q = 0 then
- dcm_rst(0) <= '0';
- state_q <= s3;
- end if;
-
- when s3 =>
- if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
- state_q <= s4;
- error_out <= '0';
- end if;
-
- when s4 =>
- if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
- locked_out <= '1';
- else
- error_out <= '1';
- end if;
- end case;
-
- -- synchronize 'dcm1_locked'
- dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
- dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
-
- end if;
- end process;
-
-end architecture tech;
-
-
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd
deleted file mode 100644
index f5ab332..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd
+++ /dev/null
@@ -1,389 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: DDR physical layer (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity ddr_phy is
- Port (
- sys_rst : in STD_LOGIC;
- sys_clk0 : in STD_LOGIC;
- sys_clk270 : in STD_LOGIC;
- u_tag_in : in user_tag_t;
- u_tag_rd : out user_tag_t;
- u_tag_wr : out user_tag_t;
- read_clk : in STD_LOGIC;
- phy_ctrl : in phy_ctrl_t;
- part_ctrl : in part_ctrl_t;
- sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0);
- sdr_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
- sdr_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
- sdr_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0);
- sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0);
- sdr_data_vld : out STD_LOGIC;
- sdr_data_req_w : out STD_LOGIC;
- sdr_data_req_r : out STD_LOGIC;
- part_clk_p : out STD_LOGIC;
- part_clk_n : out STD_LOGIC;
- part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
- part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
- part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0);
- part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0);
- part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0);
- part_cs_n : out STD_LOGIC;
- part_we_n : out STD_LOGIC;
- part_cas_n : out STD_LOGIC;
- part_ras_n : out STD_LOGIC;
- part_cke : out STD_LOGIC
- );
-end ddr_phy;
-
-architecture tech of ddr_phy is
-
- signal dqs_drive : std_logic;
- signal drive : std_logic;
- signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0);
- signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0);
- signal dqs_rst : std_logic;
- signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0);
- signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
- signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
- signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0);
- signal part_ctrl_reg : part_ctrl_t;
- signal we_reg : std_logic;
- signal read_en : std_logic;
-
- type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
- signal u_tag_pipe : u_tag_array_t;
-
- type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0);
- signal dm_out_pipe : dm_out_array_t;
-
-begin
-
-------------------------------------------------------------------------------------------------------------------------------------------------
-utag_pipe:
- process(sys_rst, sys_clk0)
- begin
- if rising_edge(sys_clk0) then
- for i in u_tag_pipe'length-1 downto 1 loop
- u_tag_pipe(i) <= u_tag_pipe(i-1);
- end loop;
- if phy_ctrl.utag_we = '1' then
- u_tag_pipe(0) <= u_tag_in;
- end if;
- end if;
- end process;
-
-dmout_pipe:
- process(sys_rst, sys_clk0)
- begin
- if rising_edge(sys_clk0) then
- for i in dm_out_pipe'length-1 downto 1 loop
- dm_out_pipe(i) <= dm_out_pipe(i-1);
- end loop;
- if phy_ctrl.utag_we = '1' then
- dm_out_pipe(0) <= sdr_dm_rd_in;
- end if;
- end if;
- end process;
-
-WE_REGISTER:
- process(sys_rst, sys_clk0)
- begin
- if sys_rst = '1' then
- we_reg <= '0';
- elsif rising_edge(sys_clk0) then
- we_reg <= phy_ctrl.we;
- end if;
- end process;
-
-DATA_DRIVE_GEN:
- process(sys_clk0)
- begin
- if falling_edge(sys_clk0) then
- dqs_rst <= not we_reg;
- drive <= we_reg;
- end if;
- end process;
-
-DQS_DRIVE_GEN:
- process(sys_clk0)
- variable p : unsigned(1 downto 0);
- begin
- if rising_edge(sys_clk0) then
- if phy_ctrl.drive_en = '1' then
- p := (others => '1');
- else
- p := p(p'left-1 downto 0) & '0';
- end if;
- end if;
- dqs_drive <= p(p'left);
- end process;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- SDRAM Clock
-ODDR_clk_p : ODDR
- generic map
- (
- DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
- INIT => '0', -- Initial value for Q port ('1' or '0')
- SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
- )
- port map (
- Q => part_clk_p, -- 1-bit DDR output
- C => sys_clk0, -- 1-bit clock input
- CE => '1', -- 1-bit clock enable input
- D1 => '1', -- 1-bit data input (positive edge)
- D2 => '0', -- 1-bit data input (negative edge)
- R => '0', -- 1-bit reset input
- S => '0' -- 1-bit set input
- );
-
-ODDR_clk_n : ODDR
- generic map
- (
- DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
- INIT => '0', -- Initial value for Q port ('1' or '0')
- SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
- )
- port map (
- Q => part_clk_n, -- 1-bit DDR output
- C => sys_clk0, -- 1-bit clock input
- CE => '1', -- 1-bit clock enable input
- D1 => '0', -- 1-bit data input (positive edge)
- D2 => '1', -- 1-bit data input (negative edge)
- R => '0', -- 1-bit reset input
- S => '0' -- 1-bit set input
- );
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- Data OUT DDR-FFs
-gen_ddr_data_out:
- for n in 0 to DDR_DATA_WIDTH-1 generate
- begin
- ODDR_data : ODDR
- generic map
- (
- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
- INIT => '0', -- Initial value for Q port ('1' or '0')
- SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
- )
- port map (
- Q => ddr_data_w(n), -- 1-bit DDR output
- C => sys_clk270, -- 1-bit clock input
- CE => '1', -- 1-bit clock enable input
- D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge)
- D2 => sdr_data_w(n), -- 1-bit data input (negative edge)
- R => '0', -- 1-bit reset input
- S => '0' -- 1-bit set input
- );
- end generate gen_ddr_data_out;
-
--- Sample tristate on clock90
- process (sys_clk270)
- begin
- if rising_edge(sys_clk270) then
- for n in 0 to DDR_DATA_WIDTH-1 loop
- drive270(n) <= drive;
- end loop;
- end if;
- end process;
-
--- Output mux
-out_mux_data:
- for n in 0 to DDR_DATA_WIDTH-1 generate
- part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
- end generate;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- Data-mask OUT DDR-FFs
-gen_ddr_dm_out:
- for n in 0 to DDR_DM_WIDTH-1 generate
- begin
- ODDR_dm : ODDR
- generic map
- (
- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
- INIT => '0', -- Initial value for Q port ('1' or '0')
- SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
- )
- port map (
- Q => part_dm(n), -- 1-bit DDR output
- C => sys_clk270, -- 1-bit clock input
- CE => '1', -- 1-bit clock enable input
- D1 => sdr_dm_wr_in(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge)
- D2 => sdr_dm_wr_in(n), -- 1-bit data input (negative edge)
- R => '0', -- 1-bit reset input
- S => '0' -- 1-bit set input
- );
- end generate gen_ddr_dm_out;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- DQS OUT DDR-FFs
-gen_dqs_out:
- for n in 0 to DDR_DQS_WIDTH-1 generate
- begin
- ODDR_dqs : ODDR
- generic map
- (
- DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
- INIT => '0', -- Initial value for Q port ('1' or '0')
- SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
- )
- port map (
- Q => dqs(n), -- 1-bit DDR output
- C => sys_clk0, -- 1-bit clock input
- CE => '1', -- 1-bit clock enable input
- D2 => '0', -- 1-bit data input (positive edge)
- D1 => '1', -- 1-bit data input (negative edge)
- R => dqs_rst, -- 1-bit reset input
- S => '0' -- 1-bit set input
- );
- end generate gen_dqs_out;
-
--- Tristate-Control fuer dqs
- process (sys_clk0) is
- variable zctrl : boolean;
- begin
- if rising_edge(sys_clk0) then
- if dqs_drive = '1' then
- zctrl := false;
- else
- zctrl := true;
- end if;
- if zctrl then
- dqs_zen <= (others => '1');
- else
- dqs_zen <= (others => '0');
- end if;
- end if;
- end process;
-
--- Tristate-Buffer fuer dqs
-gen_out_mux_dqs:
- for n in 0 to DDR_DQS_WIDTH-1 generate
- part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
- end generate gen_out_mux_dqs;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
- process (sys_rst, sys_clk0) is
- begin
- if sys_rst = '1' then
- part_ctrl_reg.cmd <= COMMAND(SD_DESELECT);
- part_ctrl_reg.ba <= (others=>'0');
- part_ctrl_reg.addr <= (others=>'0');
- part_ctrl_reg.cke <= '0';
- elsif rising_edge(sys_clk0) then
- part_ctrl_reg <= part_ctrl;
- end if;
- end process;
-
- process (sys_clk0) is
- begin
- if falling_edge(sys_clk0) then
- part_ras_n <= part_ctrl_reg.cmd.ras_n;
- part_cas_n <= part_ctrl_reg.cmd.cas_n;
- part_we_n <= part_ctrl_reg.cmd.we_n;
- part_cs_n <= part_ctrl_reg.cmd.cs_n;
- part_ba <= part_ctrl_reg.ba;
- part_addr <= part_ctrl_reg.addr;
- part_cke <= part_ctrl_reg.cke;
- end if;
- end process;
-
------------------------------------------------------------------
--- READ DATA Processing
------------------------------------------------------------------
-gen_ddr_data_in:
- for n in 0 to DDR_DATA_WIDTH-1 generate
- begin
- IDDR_data : IDDR
- generic map
- (
- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
- INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
- INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
- SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC"
- )
- port map
- (
- Q1 => data_r(n), -- 1-bit output for positive edge of clock
- Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock
- C => read_clk, -- 1-bit clock input
- CE => read_en, -- 1-bit clock enable input
- D => part_data(n), -- 1-bit DDR data input
- R => '0', -- 1-bit reset
- S => '0' -- 1-bit set
- );
- end generate;
-
-
-data_sample_stage:
- process (sys_clk0)
- begin
- if falling_edge(sys_clk0) then
- data_reg_r <= data_r;
- end if;
- end process;
-
-misc_flags_and_data_out:
- process (sys_rst, sys_clk0)
- variable p : unsigned(3 downto 0);
- begin
- if sys_rst = '1' then
- p := (others => '0');
- read_en <= '0';
- sdr_data_vld <= '0';
- sdr_data_req_w <= '0';
- sdr_data_req_r <= '0';
- elsif rising_edge(sys_clk0) then
- sdr_data_r <= data_reg_r;
- if p(3) = '1' then
- u_tag_rd <= u_tag_pipe(4);
- sdr_dm_rd_out <= dm_out_pipe(4);
- end if;
- if phy_ctrl.we = '1' then
- u_tag_wr <= u_tag_pipe(0);
- end if;
- sdr_data_req_w <= phy_ctrl.we;
- sdr_data_req_r <= phy_ctrl.re;
- sdr_data_vld <= p(3);
- read_en <= p(1);
- if phy_ctrl.re = '1' then
- p := p(p'left-1 downto 0) & '1';
- else
- p := p(p'left-1 downto 0) & '0';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-end tech;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd
deleted file mode 100644
index 02ad3a7..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd
+++ /dev/null
@@ -1,111 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.fifo_ctrl_pkg.all;
-
-entity fifo_sync is
- Generic (
- addr_width : natural := 4;
- data_width : natural := 8;
- almost_full_thresh : integer := 12;
- almost_empty_thresh : integer := 4
- );
- Port
- (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- we : in STD_LOGIC;
- re : in STD_LOGIC;
- fifo_full : out STD_LOGIC;
- fifo_empty : out STD_LOGIC;
- fifo_afull : out STD_LOGIC;
- fifo_aempty : out STD_LOGIC;
- data_w : in unsigned (data_width-1 downto 0);
- data_r : out unsigned (data_width-1 downto 0)
- );
-end fifo_sync;
-
-architecture Behavioral of fifo_sync is
-
- signal mem_we : STD_LOGIC;
- signal ptr_w : unsigned (addr_width-1 downto 0);
- signal ptr_r : unsigned (addr_width-1 downto 0);
- signal full : STD_LOGIC;
- signal empty : STD_LOGIC;
- signal almost_full : STD_LOGIC;
- signal almost_empty : STD_LOGIC;
-
-begin
-
- mem_we <= we;
- fifo_full <= full;
- fifo_empty <= empty;
- fifo_afull <= almost_full;
- fifo_aempty <= almost_empty;
-
- inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
- GENERIC MAP
- (
- addr_width => addr_width,
- almost_full_thresh => almost_full_thresh,
- almost_empty_thresh => almost_empty_thresh
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- we => we,
- re => re,
- ptr_w => ptr_w,
- ptr_r => ptr_r,
- fifo_full => full,
- fifo_empty => empty,
- fifo_afull => almost_full,
- fifo_aempty => almost_empty
-
- );
-
- inst_dpram_1w1r: entity work.dpram_1w1r_dist
- GENERIC MAP (
- addr_width => addr_width,
- data_width => data_width
- )
- PORT MAP(
- clka => clk,
- clkb => clk,
- en_a => '1',
- en_b => '1',
- we_a => mem_we,
- addr_a => ptr_w,
- addr_b => ptr_r,
- din_a => data_w,
- dout_b => data_r
- );
-
-end Behavioral;
-
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd
deleted file mode 100644
index 356bb28..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd
+++ /dev/null
@@ -1,1320 +0,0 @@
------------------------------------------------------------------------------------------
---
--- File Name: MT46V16M16.VHD
--- Version: 2.1
--- Date: January 14th, 2002
--- Model: Behavioral
--- Simulator: NCDesktop - http://www.cadence.com
--- ModelSim PE - http://www.model.com
---
--- Dependencies: None
---
--- Author: Son P. Huynh
--- Email: sphuynh@micron.com
--- Phone: (208) 368-3825
--- Company: Micron Technology, Inc.
--- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
---
--- Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
---
--- Limitation: Doesn't model internal refresh counter
---
--- Note:
---
--- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
--- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
---
--- Copyright (c) 1998 Micron Semiconductor Products, Inc.
--- All rights researved
---
--- Rev Author Date Changes
--- --- ---------------------------- ---------- -------------------------------------
--- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter
--- Micron Technology, Inc.
---
--- 2.0 Son P. Huynh 11/08/2001 - Second release
--- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE
---
------------------------------------------------------------------------------------------
-
-LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- USE IEEE.STD_LOGIC_ARITH.ALL;
-
-ENTITY MT46V16M16 IS
- GENERIC ( -- Timing for -75Z CL2
- tCK : TIME := 7.500 ns;
- tCH : TIME := 3.375 ns; -- 0.45*tCK
- tCL : TIME := 3.375 ns; -- 0.45*tCK
- tDH : TIME := 0.500 ns;
- tDS : TIME := 0.500 ns;
- tIH : TIME := 0.900 ns;
- tIS : TIME := 0.900 ns;
- tMRD : TIME := 15.000 ns;
- tRAS : TIME := 40.000 ns;
- tRAP : TIME := 20.000 ns;
- tRC : TIME := 65.000 ns;
- tRFC : TIME := 75.000 ns;
- tRCD : TIME := 20.000 ns;
- tRP : TIME := 20.000 ns;
- tRRD : TIME := 15.000 ns;
- tWR : TIME := 15.000 ns;
- addr_bits : INTEGER := 13;
- data_bits : INTEGER := 16;
- cols_bits : INTEGER := 9
- );
- PORT (
- Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
- Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
- Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- Clk : IN STD_LOGIC;
- Clk_n : IN STD_LOGIC;
- Cke : IN STD_LOGIC;
- Cs_n : IN STD_LOGIC;
- Ras_n : IN STD_LOGIC;
- Cas_n : IN STD_LOGIC;
- We_n : IN STD_LOGIC;
- Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
- );
-END MT46V16M16;
-
-ARCHITECTURE behave OF MT46V16M16 IS
- -- Array for Read pipeline
- TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
- TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
- -- Array for Write pipeline
- TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
- TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
- -- Array for Auto Precharge
- TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
-
- -- Array for Manual Precharge
- TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
- TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-
- -- Array for Burst Terminate
- TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-
- -- Array for Memory Access
- TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
- TYPE Array_ram_pntr IS ACCESS Array_ram_type;
- TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
-
- -- Data pair
- SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
- SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
-
- -- Mode Register
- SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-
- -- Command Decode Variables
- SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
- SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
-
- -- Burst Length Decode Variables
- SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
-
- -- Cas Latency Decode Variables
- SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
-
- -- Internal Control Signals
- SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
-
- -- System Clock
- SIGNAL Sys_clk : STD_LOGIC := '0';
-
- -- Dqs buffer
- SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-
-BEGIN
- -- Strip the strength
- Cs_in <= To_X01 (Cs_n);
- Ras_in <= To_X01 (Ras_n);
- Cas_in <= To_X01 (Cas_n);
- We_in <= To_X01 (We_n);
-
- -- Commands Decode
- Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
- Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
- Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
- Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1));
- Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
- Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
- Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
- Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
-
- -- Burst Length Decode
- Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
- Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
- Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
- Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-
- -- CAS Latency Decode
- Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4));
- Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
- Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4));
- Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
- Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
-
- -- Dqs buffer
- Dqs <= Dqs_out;
-
- --
- -- System Clock
- --
- int_clk : PROCESS (Clk, Clk_n)
- VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
- begin
- IF Clk = '1' AND Clk_n = '0' THEN
- ClkZ := '1';
- CkeZ := Cke;
- ELSIF Clk = '0' AND Clk_n = '1' THEN
- ClkZ := '0';
- END IF;
- Sys_clk <= CkeZ AND ClkZ;
- END PROCESS;
-
- --
- -- Main Process
- --
- state_register : PROCESS
- -- Precharge Variables
- VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
-
- -- Activate Variables
- VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-
- -- Data IO variables
- VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
-
- -- Internal address mux variables
- VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
- VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
- VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
- VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
- VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-
- -- DLL Reset variables
- VARIABLE DLL_enable : STD_LOGIC := '0';
- VARIABLE DLL_reset : STD_LOGIC := '0';
- VARIABLE DLL_done : STD_LOGIC := '0';
- VARIABLE DLL_count : INTEGER := 0;
-
- -- Timing Check
- VARIABLE MRD_chk : TIME := 0 ns;
- VARIABLE RFC_chk : TIME := 0 ns;
- VARIABLE RRD_chk : TIME := 0 ns;
- VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
- VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
- VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
- VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
- VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
- VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
-
- -- Read pipeline variables
- VARIABLE Read_cmnd : Array_Read_cmnd;
- VARIABLE Read_bank : Array_Read_bank;
- VARIABLE Read_cols : Array_Read_cols;
-
- -- Write pipeline variables
- VARIABLE Write_cmnd : Array_Write_cmnd;
- VARIABLE Write_bank : Array_Write_bank;
- VARIABLE Write_cols : Array_Write_cols;
-
- -- Auto Precharge variables
- VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0');
- VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
- VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 );
-
- -- Manual Precharge variables
- VARIABLE A10_precharge : Array_A10_precharge;
- VARIABLE Bank_precharge : Array_Bank_precharge;
- VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
-
- -- Burst Terminate variable
- VARIABLE Cmnd_bst : Array_Cmnd_bst;
-
- -- Memory Banks
- VARIABLE Bank0 : Array_ram_stor;
- VARIABLE Bank1 : Array_ram_stor;
- VARIABLE Bank2 : Array_ram_stor;
- VARIABLE Bank3 : Array_ram_stor;
-
- -- Burst Counter
- VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
- -- Internal Dqs initialize
- VARIABLE Dqs_int : STD_LOGIC := '0';
-
- -- Data buffer for DM Mask
- VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-
- --
- -- Initialize empty rows
- --
- PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
- VARIABLE i, j : INTEGER := 0;
- BEGIN
- IF Bank = "00" THEN
- IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
- Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access
- FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank0 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- ELSIF Bank = "01" THEN
- IF Bank1 (Row_index) = NULL THEN
- Bank1 (Row_index) := NEW Array_ram_type;
- FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank1 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- ELSIF Bank = "10" THEN
- IF Bank2 (Row_index) = NULL THEN
- Bank2 (Row_index) := NEW Array_ram_type;
- FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank2 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- ELSIF Bank = "11" THEN
- IF Bank3 (Row_index) = NULL THEN
- Bank3 (Row_index) := NEW Array_ram_type;
- FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank3 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- END IF;
- END;
-
- --
- -- Burst Counter
- --
- PROCEDURE Burst_decode IS
- VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
- BEGIN
- -- Advance burst counter
- Burst_counter := Burst_counter + 1;
-
- -- Burst Type
- IF Mode_reg (3) = '0' THEN
- Cols_temp := Cols_addr + 1;
- ELSIF Mode_reg (3) = '1' THEN
- Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
- Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
- Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
- END IF;
-
- -- Burst Length
- IF Burst_length_2 = '1' THEN
- Cols_addr (0) := Cols_temp (0);
- ELSIF Burst_length_4 = '1' THEN
- Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
- ELSIF Burst_length_8 = '1' THEN
- Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
- ELSE
- Cols_addr := Cols_temp;
- END IF;
-
- -- Data counter
- IF Burst_length_2 = '1' THEN
- IF Burst_counter >= 2 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- ELSIF Burst_length_4 = '1' THEN
- IF Burst_counter >= 4 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- ELSIF Burst_length_8 = '1' THEN
- IF Burst_counter >= 8 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- END IF;
- END;
-
- BEGIN
- WAIT ON Sys_clk;
-
- --
- -- Manual Precharge Pipeline
- --
- IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
- -- A10 Precharge Pipeline
- A10_precharge(0) := A10_precharge(1);
- A10_precharge(1) := A10_precharge(2);
- A10_precharge(2) := A10_precharge(3);
- A10_precharge(3) := A10_precharge(4);
- A10_precharge(4) := A10_precharge(5);
- A10_precharge(5) := A10_precharge(6);
- A10_precharge(6) := A10_precharge(7);
- A10_precharge(7) := A10_precharge(8);
- A10_precharge(8) := '0';
-
- -- Bank Precharge Pipeline
- Bank_precharge(0) := Bank_precharge(1);
- Bank_precharge(1) := Bank_precharge(2);
- Bank_precharge(2) := Bank_precharge(3);
- Bank_precharge(3) := Bank_precharge(4);
- Bank_precharge(4) := Bank_precharge(5);
- Bank_precharge(5) := Bank_precharge(6);
- Bank_precharge(6) := Bank_precharge(7);
- Bank_precharge(7) := Bank_precharge(8);
- Bank_precharge(8) := "00";
-
- -- Command Precharge Pipeline
- Cmnd_precharge(0) := Cmnd_precharge(1);
- Cmnd_precharge(1) := Cmnd_precharge(2);
- Cmnd_precharge(2) := Cmnd_precharge(3);
- Cmnd_precharge(3) := Cmnd_precharge(4);
- Cmnd_precharge(4) := Cmnd_precharge(5);
- Cmnd_precharge(5) := Cmnd_precharge(6);
- Cmnd_precharge(6) := Cmnd_precharge(7);
- Cmnd_precharge(7) := Cmnd_precharge(8);
- Cmnd_precharge(8) := '0';
-
- -- Terminate Read if same bank or all banks
- IF ((Cmnd_precharge (0) = '1') AND
- (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
- (Data_out_enable = '1')) THEN
- Data_out_enable := '0';
- END IF;
- END IF;
-
- --
- -- Burst Terminate Pipeline
- --
- IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
- -- Burst Terminate pipeline
- Cmnd_bst (0) := Cmnd_bst (1);
- Cmnd_bst (1) := Cmnd_bst (2);
- Cmnd_bst (2) := Cmnd_bst (3);
- Cmnd_bst (3) := Cmnd_bst (4);
- Cmnd_bst (4) := Cmnd_bst (5);
- Cmnd_bst (5) := Cmnd_bst (6);
- Cmnd_bst (6) := Cmnd_bst (7);
- Cmnd_bst (7) := Cmnd_bst (8);
- Cmnd_bst (8) := '0';
-
- -- Terminate current Read
- IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN
- Data_out_enable := '0';
- END IF;
- END IF;
-
- --
- -- Dq and Dqs Drivers
- --
- IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
- -- Read Command Pipeline
- Read_cmnd (0) := Read_cmnd (1);
- Read_cmnd (1) := Read_cmnd (2);
- Read_cmnd (2) := Read_cmnd (3);
- Read_cmnd (3) := Read_cmnd (4);
- Read_cmnd (4) := Read_cmnd (5);
- Read_cmnd (5) := Read_cmnd (6);
- Read_cmnd (6) := Read_cmnd (7);
- Read_cmnd (7) := Read_cmnd (8);
- Read_cmnd (8) := '0';
-
- -- Read Bank Pipeline
- Read_bank (0) := Read_bank (1);
- Read_bank (1) := Read_bank (2);
- Read_bank (2) := Read_bank (3);
- Read_bank (3) := Read_bank (4);
- Read_bank (4) := Read_bank (5);
- Read_bank (5) := Read_bank (6);
- Read_bank (6) := Read_bank (7);
- Read_bank (7) := Read_bank (8);
- Read_bank (8) := "00";
-
- -- Read Column Pipeline
- Read_cols (0) := Read_cols (1);
- Read_cols (1) := Read_cols (2);
- Read_cols (2) := Read_cols (3);
- Read_cols (3) := Read_cols (4);
- Read_cols (4) := Read_cols (5);
- Read_cols (5) := Read_cols (6);
- Read_cols (6) := Read_cols (7);
- Read_cols (7) := Read_cols (8);
- Read_cols (8) := (OTHERS => '0');
-
- -- Initialize Read command
- IF Read_cmnd (0) = '1' THEN
- Data_out_enable := '1';
- Bank_addr := Read_bank (0);
- Cols_addr := Read_cols (0);
- Cols_brst := Cols_addr (2 DOWNTO 0);
- Burst_counter := (OTHERS => '0');
-
- -- Row address mux
- CASE Bank_addr IS
- WHEN "00" => Rows_addr := B0_row_addr;
- WHEN "01" => Rows_addr := B1_row_addr;
- WHEN "10" => Rows_addr := B2_row_addr;
- WHEN OTHERS => Rows_addr := B3_row_addr;
- END CASE;
- END IF;
-
- -- Toggle Dqs during Read command
- IF Data_out_enable = '1' THEN
- Dqs_int := '0';
- IF Dqs_out = "00" THEN
- Dqs_out <= "11";
- ELSIF Dqs_out = "11" THEN
- Dqs_out <= "00";
- ELSE
- Dqs_out <= "00";
- END IF;
- ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
- Dqs_out <= "ZZ";
- END IF;
-
- -- Initialize Dqs for Read command
- IF Read_cmnd (2) = '1' THEN
- IF Data_out_enable = '0' THEN
- Dqs_int := '1';
- Dqs_out <= "00";
- END IF;
- END IF;
-
- -- Read Latch
- IF Data_out_enable = '1' THEN
- -- Initialize Memory
- Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-
- -- Output Data
- CASE Bank_addr IS
- WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- END CASE;
-
- -- Increase Burst Counter
- Burst_decode;
- ELSE
- Dq <= (OTHERS => 'Z');
- END IF;
- END IF;
-
- --
- -- Write FIFO and DM Mask Logic
- --
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- -- Write command pipeline
- Write_cmnd (0) := Write_cmnd (1);
- Write_cmnd (1) := Write_cmnd (2);
- Write_cmnd (2) := '0';
-
- -- Write command pipeline
- Write_bank (0) := Write_bank (1);
- Write_bank (1) := Write_bank (2);
- Write_bank (2) := "00";
-
- -- Write column pipeline
- Write_cols (0) := Write_cols (1);
- Write_cols (1) := Write_cols (2);
- Write_cols (2) := (OTHERS => '0');
-
- -- Initialize Write command
- IF Write_cmnd (0) = '1' THEN
- Data_in_enable := '1';
- Bank_addr := Write_bank (0);
- Cols_addr := Write_cols (0);
- Cols_brst := Cols_addr (2 DOWNTO 0);
- Burst_counter := (OTHERS => '0');
-
- -- Row address mux
- CASE Bank_addr IS
- WHEN "00" => Rows_addr := B0_row_addr;
- WHEN "01" => Rows_addr := B1_row_addr;
- WHEN "10" => Rows_addr := B2_row_addr;
- WHEN OTHERS => Rows_addr := B3_row_addr;
- END CASE;
- END IF;
-
- -- Write data
- IF Data_in_enable = '1' THEN
- -- Initialize memory
- Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-
- -- Write first data
- IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
- -- Data Buffer
- CASE Bank_addr IS
- WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- END CASE;
-
- -- Perform DM Mask
- IF Dm_pair (0) = '0' THEN
- Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
- END IF;
- IF Dm_pair (1) = '0' THEN
- Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
- END IF;
-
- -- Write Data
- CASE Bank_addr IS
- WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- END CASE;
- END IF;
-
- -- Increase Burst Counter
- Burst_decode;
-
- -- Write second data
- IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
- -- Data Buffer
- CASE Bank_addr IS
- WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- END CASE;
-
- -- Perform DM Mask
- IF Dm_pair (2) = '0' THEN
- Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
- END IF;
- IF Dm_pair (3) = '0' THEN
- Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
- END IF;
-
- -- Write Data
- CASE Bank_addr IS
- WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- END CASE;
- END IF;
-
- -- Increase Burst Counter
- Burst_decode;
-
- -- tWR start and tWTR check
- IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
- CASE Bank_addr IS
- WHEN "00" => WR_chk0 := NOW;
- WHEN "01" => WR_chk1 := NOW;
- WHEN "10" => WR_chk2 := NOW;
- WHEN OTHERS => WR_chk3 := NOW;
- END CASE;
-
- -- tWTR check
- ASSERT (Read_enable = '0')
- REPORT "tWTR violation during Read"
- SEVERITY WARNING;
- END IF;
- END IF;
- END IF;
-
- --
- -- Auto Precharge Calculation
- --
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- -- Precharge counter
- IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
- Count_precharge (0) := Count_precharge (0) + 1;
- END IF;
- IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
- Count_precharge (1) := Count_precharge (1) + 1;
- END IF;
- IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
- Count_precharge (2) := Count_precharge (2) + 1;
- END IF;
- IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
- Count_precharge (3) := Count_precharge (3) + 1;
- END IF;
-
- -- Read with AutoPrecharge Calculation
- -- The device start internal precharge when:
- -- 1. Meet tRAS requirement
- -- 2. BL/2 cycles after command
- IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR
- (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR
- (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
- Pc_b0 := '1';
- Act_b0 := '0';
- RP_chk0 := NOW;
- Read_precharge(0) := '0';
- END IF;
- END IF;
- IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR
- (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR
- (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
- Pc_b1 := '1';
- Act_b1 := '0';
- RP_chk1 := NOW;
- Read_precharge(1) := '0';
- END IF;
- END IF;
- IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR
- (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR
- (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
- Pc_b2 := '1';
- Act_b2 := '0';
- RP_chk2 := NOW;
- Read_precharge(2) := '0';
- END IF;
- END IF;
- IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR
- (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR
- (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
- Pc_b3 := '1';
- Act_b3 := '0';
- RP_chk3 := NOW;
- Read_precharge(3) := '0';
- END IF;
- END IF;
-
- -- Write with AutoPrecharge Calculation
- -- The device start internal precharge when:
- -- 1. Meet tRAS requirement
- -- 2. Two clock after last burst
- -- Since tWR is time base, the model will compensate tRP
- IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
- (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
- (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
- Pc_b0 := '1';
- Act_b0 := '0';
- RP_chk0 := NOW - ((2 * tCK) - tWR);
- Write_precharge(0) := '0';
- END IF;
- END IF;
- IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
- (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
- (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
- Pc_b1 := '1';
- Act_b1 := '0';
- RP_chk1 := NOW - ((2 * tCK) - tWR);
- Write_precharge(1) := '0';
- END IF;
- END IF;
- IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
- (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
- (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
- Pc_b2 := '1';
- Act_b2 := '0';
- RP_chk2 := NOW - ((2 * tCK) - tWR);
- Write_precharge(2) := '0';
- END IF;
- END IF;
- IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
- (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
- (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
- Pc_b3 := '1';
- Act_b3 := '0';
- RP_chk3 := NOW - ((2 * tCK) - tWR);
- Write_precharge(3) := '0';
- END IF;
- END IF;
- END IF;
-
- --
- -- DLL Counter
- --
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- IF (DLL_Reset = '1' AND DLL_done = '0') THEN
- DLL_count := DLL_count + 1;
- IF (DLL_count >= 200) THEN
- DLL_done := '1';
- END IF;
- END IF;
- END IF;
-
- --
- -- Control Logic
- --
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- -- Auto Refresh
- IF Aref_enable = '1' THEN
- -- Auto Refresh to Auto Refresh
- ASSERT (NOW - RFC_chk >= tRFC)
- REPORT "tRFC violation during Auto Refresh"
- SEVERITY WARNING;
-
- -- Precharge to Auto Refresh
- ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
- (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
- REPORT "tRP violation during Auto Refresh"
- SEVERITY WARNING;
-
- -- Precharge to Auto Refresh
- ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
- REPORT "All banks must be Precharge before Auto Refresh"
- SEVERITY WARNING;
-
- -- Record current tRFC time
- RFC_chk := NOW;
- END IF;
-
- -- Extended Load Mode Register
- IF Ext_mode_enable = '1' THEN
- IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
- IF (Addr (0) = '0') THEN
- DLL_enable := '1';
- ELSE
- DLL_enable := '0';
- END IF;
- END IF;
-
- -- Precharge to EMR
- ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
- REPORT "All bank must be Precharged before Extended Mode Register"
- SEVERITY WARNING;
-
- -- Precharge to EMR
- ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
- (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
- REPORT "tRP violation during Extended Load Register"
- SEVERITY WARNING;
-
- -- LMR/EMR to EMR
- ASSERT (NOW - MRD_chk >= tMRD)
- REPORT "tMRD violation during Extended Mode Register"
- SEVERITY WARNING;
-
- -- Record current tMRD time
- MRD_chk := NOW;
- END IF;
-
- -- Load Mode Register
- IF Mode_reg_enable = '1' THEN
- -- Register mode
- Mode_reg <= Addr;
-
- -- DLL Reset
- IF (DLL_enable = '1' AND Addr (8) = '1') THEN
- DLL_reset := '1';
- DLL_done := '0';
- DLL_count := 0;
- ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
- ASSERT (FALSE)
- REPORT "DLL is ENABLE: DLL RESET is require"
- SEVERITY WARNING;
- ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
- ASSERT (FALSE)
- REPORT "DLL is DISABLE: DLL RESET will be ignored"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge to LMR
- ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
- REPORT "All bank must be Precharged before Load Mode Register"
- SEVERITY WARNING;
-
- -- Precharge to EMR
- ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
- (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
- REPORT "tRP violation during Load Mode Register"
- SEVERITY WARNING;
-
- -- LMR/ELMR to LMR
- ASSERT (NOW - MRD_chk >= tMRD)
- REPORT "tMRD violation during Load Mode Register"
- SEVERITY WARNING;
-
- -- Check for invalid Burst Length
- ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2
- (Addr (2 DOWNTO 0) = "010") OR -- BL = 4
- (Addr (2 DOWNTO 0) = "011")) -- BL = 8
- REPORT "Invalid Burst Length during Load Mode Register"
- SEVERITY WARNING;
-
- -- Check for invalid CAS Latency
- ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0
- (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5
- REPORT "Invalid CAS Latency during Load Mode Register"
- SEVERITY WARNING;
-
- -- Record current tMRD time
- MRD_chk := NOW;
- END IF;
-
- -- Active Block (latch Bank and Row Address)
- IF Active_enable = '1' THEN
- -- Activate an OPEN bank can corrupt data
- ASSERT ((Ba = "00" AND Act_b0 = '0') OR
- (Ba = "01" AND Act_b1 = '0') OR
- (Ba = "10" AND Act_b2 = '0') OR
- (Ba = "11" AND Act_b3 = '0'))
- REPORT "Bank is already activated - data can be corrupted"
- SEVERITY WARNING;
-
- -- Activate Bank 0
- IF Ba = "00" AND Pc_b0 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk0 >= tRC)
- REPORT "tRC violation during Activate Bank 0"
- SEVERITY WARNING;
-
- -- Precharge to Active
- ASSERT (NOW - RP_chk0 >= tRP)
- REPORT "tRP violation during Activate Bank 0"
- SEVERITY WARNING;
-
- -- Record Variables for checking violation
- Act_b0 := '1';
- Pc_b0 := '0';
- B0_row_addr := Addr;
- RC_chk0 := NOW;
- RCD_chk0 := NOW;
- RAS_chk0 := NOW;
- RAP_chk0 := NOW;
- END IF;
-
- -- Activate Bank 1
- IF Ba = "01" AND Pc_b1 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk1 >= tRC)
- REPORT "tRC violation during Activate Bank 1"
- SEVERITY WARNING;
-
- -- Precharge to Active
- ASSERT (NOW - RP_chk1 >= tRP)
- REPORT "tRP violation during Activate Bank 1"
- SEVERITY WARNING;
-
- -- Record Variables for checking violation
- Act_b1 := '1';
- Pc_b1 := '0';
- B1_row_addr := Addr;
- RC_chk1 := NOW;
- RCD_chk1 := NOW;
- RAS_chk1 := NOW;
- RAP_chk1 := NOW;
- END IF;
-
- -- Activate Bank 2
- IF Ba = "10" AND Pc_b2 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk2 >= tRC)
- REPORT "tRC violation during Activate Bank 2"
- SEVERITY WARNING;
-
- -- Precharge to Active
- ASSERT (NOW - RP_chk2 >= tRP)
- REPORT "tRP violation during Activate Bank 2"
- SEVERITY WARNING;
-
- -- Record Variables for checking violation
- Act_b2 := '1';
- Pc_b2 := '0';
- B2_row_addr := Addr;
- RC_chk2 := NOW;
- RCD_chk2 := NOW;
- RAS_chk2 := NOW;
- RAP_chk2 := NOW;
- END IF;
-
- -- Activate Bank 3
- IF Ba = "11" AND Pc_b3 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk3 >= tRC)
- REPORT "tRC violation during Activate Bank 3"
- SEVERITY WARNING;
-
- -- Precharge to Active
- ASSERT (NOW - RP_chk3 >= tRP)
- REPORT "tRP violation during Activate Bank 3"
- SEVERITY WARNING;
-
- -- Record Variables for checking violation
- Act_b3 := '1';
- Pc_b3 := '0';
- B3_row_addr := Addr;
- RC_chk3 := NOW;
- RCD_chk3 := NOW;
- RAS_chk3 := NOW;
- RAP_chk3 := NOW;
- END IF;
-
- -- Activate Bank A to Activate Bank B
- IF (Prev_bank /= Ba) THEN
- ASSERT (NOW - RRD_chk >= tRRD)
- REPORT "tRRD violation during Activate"
- SEVERITY WARNING;
- END IF;
-
- -- AutoRefresh to Activate
- ASSERT (NOW - RFC_chk >= tRFC)
- REPORT "tRFC violation during Activate"
- SEVERITY WARNING;
-
- -- Record Variables for Checking Violation
- RRD_chk := NOW;
- Prev_bank := Ba;
- END IF;
-
- -- Precharge Block - Consider NOP if bank already precharged or in process of precharging
- IF Prech_enable = '1' THEN
- -- EMR or LMR to Precharge
- ASSERT (NOW - MRD_chk >= tMRD)
- REPORT "tMRD violation during Precharge"
- SEVERITY WARNING;
-
- -- Precharge Bank 0
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
- Act_b0 := '0';
- Pc_b0 := '1';
- RP_chk0 := NOW;
-
- -- Activate to Precharge bank 0
- ASSERT (NOW - RAS_chk0 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chk0 >= tWR)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge Bank 1
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
- Act_b1 := '0';
- Pc_b1 := '1';
- RP_chk1 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk1 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chk1 >= tWR)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge Bank 2
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
- Act_b2 := '0';
- Pc_b2 := '1';
- RP_chk2 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk2 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chk2 >= tWR)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge Bank 3
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
- Act_b3 := '0';
- Pc_b3 := '1';
- RP_chk3 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk3 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chk3 >= tWR)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Pipeline for READ
- IF CAS_latency_15 = '1' THEN
- A10_precharge (3) := Addr(10);
- Bank_precharge (3) := Ba;
- Cmnd_precharge (3) := '1';
- ELSIF CAS_latency_2 = '1' THEN
- A10_precharge (4) := Addr(10);
- Bank_precharge (4) := Ba;
- Cmnd_precharge (4) := '1';
- ELSIF CAS_latency_25 = '1' THEN
- A10_precharge (5) := Addr(10);
- Bank_precharge (5) := Ba;
- Cmnd_precharge (5) := '1';
- ELSIF CAS_latency_3 = '1' THEN
- A10_precharge (6) := Addr(10);
- Bank_precharge (6) := Ba;
- Cmnd_precharge (6) := '1';
- ELSIF CAS_latency_4 = '1' THEN
- A10_precharge (8) := Addr(10);
- Bank_precharge (8) := Ba;
- Cmnd_precharge (8) := '1';
- END IF;
- END IF;
-
- -- Burst Terminate
- IF Burst_term = '1' THEN
- -- Pipeline for Read
- IF CAS_latency_15 = '1' THEN
- Cmnd_bst (3) := '1';
- ELSIF CAS_latency_2 = '1' THEN
- Cmnd_bst (4) := '1';
- ELSIF CAS_latency_25 = '1' THEN
- Cmnd_bst (5) := '1';
- ELSIF CAS_latency_3 = '1' THEN
- Cmnd_bst (6) := '1';
- ELSIF CAS_latency_4 = '1' THEN
- Cmnd_bst (8) := '1';
- END IF;
-
- -- Terminate Write
- ASSERT (Data_in_enable = '0')
- REPORT "It's illegal to Burst Terminate a Write"
- SEVERITY WARNING;
-
- -- Terminate Read with Auto Precharge
- ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
- Read_precharge (2) = '0' AND Read_precharge (3) = '0')
- REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Read Command
- IF Read_enable = '1' THEN
- -- CAS Latency Pipeline
- IF Cas_latency_15 = '1' THEN
- Read_cmnd (3) := '1';
- Read_bank (3) := Ba;
- Read_cols (3) := Addr (8 DOWNTO 0);
- ELSIF Cas_latency_2 = '1' THEN
- Read_cmnd (4) := '1';
- Read_bank (4) := Ba;
- Read_cols (4) := Addr (8 DOWNTO 0);
- ELSIF Cas_latency_25 = '1' THEN
- Read_cmnd (5) := '1';
- Read_bank (5) := Ba;
- Read_cols (5) := Addr (8 DOWNTO 0);
- ELSIF Cas_latency_3 = '1' THEN
- Read_cmnd (6) := '1';
- Read_bank (6) := Ba;
- Read_cols (6) := Addr (8 DOWNTO 0);
- ELSIF Cas_latency_4 = '1' THEN
- Read_cmnd (8) := '1';
- Read_bank (8) := Ba;
- Read_cols (8) := Addr (8 DOWNTO 0);
- END IF;
-
- -- Write to Read: Terminate Write Immediately
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- END IF;
-
- -- Interrupting a Read with Auto Precharge (same bank only)
- ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
- REPORT "It's illegal to interrupt a Read with Auto Precharge"
- SEVERITY WARNING;
-
- -- Activate to Read
- ASSERT ((Ba = "00" AND Act_b0 = '1') OR
- (Ba = "01" AND Act_b1 = '1') OR
- (Ba = "10" AND Act_b2 = '1') OR
- (Ba = "11" AND Act_b3 = '1'))
- REPORT "Bank is not Activated for Read"
- SEVERITY WARNING;
-
- -- Activate to Read without Auto Precharge
- IF Addr (10) = '0' THEN
- ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
- (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
- (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
- (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
- REPORT "tRCD violation during Read"
- SEVERITY WARNING;
- END IF;
-
- -- Activate to Read with Auto Precharge
- IF Addr (10) = '1' THEN
- ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
- (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
- (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
- (Ba = "11" AND NOW - RAP_chk3 >= tRAP))
- REPORT "tRAP violation during Read"
- SEVERITY WARNING;
- END IF;
-
- -- Auto precharge
- IF Addr (10) = '1' THEN
- Read_precharge (Conv_INTEGER(Ba)) := '1';
- Count_precharge (Conv_INTEGER(Ba)) := 0;
- END IF;
-
- -- DLL Check
- IF (DLL_reset = '1') THEN
- ASSERT (DLL_done = '1')
- REPORT "DLL RESET not complete"
- SEVERITY WARNING;
- END IF;
- END IF;
-
- -- Write Command
- IF Write_enable = '1' THEN
- -- Pipeline for Write
- Write_cmnd (2) := '1';
- Write_bank (2) := Ba;
- Write_cols (2) := Addr (8 DOWNTO 0);
-
- -- Interrupting a Write with Auto Precharge (same bank only)
- ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
- REPORT "It's illegal to interrupt a Write with Auto Precharge"
- SEVERITY WARNING;
-
- -- Activate to Write
- ASSERT ((Ba = "00" AND Act_b0 = '1') OR
- (Ba = "01" AND Act_b1 = '1') OR
- (Ba = "10" AND Act_b2 = '1') OR
- (Ba = "11" AND Act_b3 = '1'))
- REPORT "Bank is not Activated for Write"
- SEVERITY WARNING;
-
- -- Activate to Write
- ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
- (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
- (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
- (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
- REPORT "tRCD violation during Write"
- SEVERITY WARNING;
-
- -- Auto precharge
- IF Addr (10) = '1' THEN
- Write_precharge (Conv_INTEGER(Ba)) := '1';
- Count_precharge (Conv_INTEGER(Ba)) := 0;
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- --
- -- Dqs Receiver
- --
- dqs_rcvrs : PROCESS
- VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
- VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
- BEGIN
- WAIT ON Dqs;
- -- Latch data at posedge Dqs
- IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
- Dq_temp := Dq;
- Dm_temp := Dm;
- END IF;
- -- Latch data at negedge Dqs
- IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
- Dq_pair <= (Dq & Dq_temp);
- Dm_pair <= (Dm & Dm_temp);
- END IF;
- END PROCESS;
-
- --
- -- Setup timing checks
- --
- Setup_check : PROCESS
- BEGIN
- WAIT ON Sys_clk;
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- ASSERT(Cke'LAST_EVENT >= tIS)
- REPORT "CKE Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Cs_n'LAST_EVENT >= tIS)
- REPORT "CS# Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Cas_n'LAST_EVENT >= tIS)
- REPORT "CAS# Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Ras_n'LAST_EVENT >= tIS)
- REPORT "RAS# Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(We_n'LAST_EVENT >= tIS)
- REPORT "WE# Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Addr'LAST_EVENT >= tIS)
- REPORT "ADDR Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Ba'LAST_EVENT >= tIS)
- REPORT "BA Setup time violation -- tIS"
- SEVERITY WARNING;
- END IF;
- END PROCESS;
-
- --
- -- Hold timing checks
- --
- Hold_check : PROCESS
- BEGIN
- WAIT ON Sys_clk'DELAYED (tIH);
- IF Sys_clk'DELAYED (tIH) = '1' THEN
- ASSERT(Cke'LAST_EVENT >= tIH)
- REPORT "CKE Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Cs_n'LAST_EVENT >= tIH)
- REPORT "CS# Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Cas_n'LAST_EVENT >= tIH)
- REPORT "CAS# Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Ras_n'LAST_EVENT >= tIH)
- REPORT "RAS# Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(We_n'LAST_EVENT >= tIH)
- REPORT "WE# Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Addr'LAST_EVENT >= tIH)
- REPORT "ADDR Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Ba'LAST_EVENT >= tIH)
- REPORT "BA Hold time violation -- tIH"
- SEVERITY WARNING;
- END IF;
- END PROCESS;
-
-END behave;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd
deleted file mode 100644
index a50b6e8..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd
+++ /dev/null
@@ -1,269 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: SDRAM command controller
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_cmd is
- Generic (BL : natural := 2);
- Port (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- enable : in STD_LOGIC;
- u_tag_in : in user_tag_t;
- u_tag_out : out user_tag_t;
- phy_ctrl : out phy_ctrl_t;
- cmd : in sdr_cmd_t;
- cmd_we : in STD_LOGIC;
- cmd_ack : out STD_LOGIC;
- col_addr : in col_addr_t;
- mode_word : in mode_word_t;
- sdr_cmd_ctrl : out sdr_cmd_lines_t;
- sdr_addr : out sdr_addr_t;
- sdr_ba : out sdr_ba_t
- );
-end sdram_cmd;
-
-architecture behaviour of sdram_cmd is
-
- signal st_sdr, st_sdr_next : sdr_state_t;
-
- signal cc_preset : natural range 0 to 10;
- signal cc_load_en : std_logic;
- signal cycle_finished : std_logic;
-
- signal burst_preset : natural range 0 to 3;
- signal burst_load_en : std_logic;
- signal burst_finished : std_logic;
-
-begin
-
- u_tag_out <= u_tag_in;
-
-------------------------------------------------------------------------------------------
-
-fsm_sdr_state:
- process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
- begin
- st_sdr_next <= st_sdr;
- sdr_cmd_ctrl <= COMMAND(SD_NOP);
-
- cc_load_en <= '0';
- cc_preset <= TIMING(cmd);
- burst_load_en <= '0';
- cmd_ack <= '0';
- burst_preset <= BL/2-1;
- phy_ctrl.re <= '0';
- phy_ctrl.drive_en <= '0';
- phy_ctrl.we <= '0';
- phy_ctrl.utag_we <= '0';
- sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
- sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1);
-
- case st_sdr is
- when PWR_DOWN =>
- sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
- if enable = '1' then
- st_sdr_next <= IDLE;
- end if;
-
- when PRECHARGE =>
- if cycle_finished = '1' then
- st_sdr_next <= IDLE;
- end if;
-
- when MODE =>
- if cycle_finished = '1' then
- st_sdr_next <= IDLE;
- end if;
-
- when IDLE =>
- if cmd_we = '1' then
- cmd_ack <= '1';
- cc_load_en <= '1';
- cc_preset <= TIMING(cmd);
- sdr_cmd_ctrl <= COMMAND(cmd);
- case cmd is
- when SD_PRE =>
- st_sdr_next <= PRECHARGE;
- sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL);
- when SD_LMR =>
- st_sdr_next <= MODE;
- when SD_ACT =>
- st_sdr_next <= ROW_ACT;
- when SD_AR =>
- st_sdr_next <= AUTO_REF;
- when others => null;
- end case;
- end if;
-
- when ROW_ACT =>
- if cycle_finished = '1' then
- if cmd_we = '1' then
- cmd_ack <= '1';
- burst_load_en <= '1';
- cc_load_en <= '1';
- cc_preset <= TIMING(cmd);
- sdr_cmd_ctrl <= COMMAND(cmd);
- case cmd is
- when SD_PRE =>
- st_sdr_next <= PRECHARGE;
- when SD_READ =>
- phy_ctrl.utag_we <= '1';
- st_sdr_next <= READ;
- sdr_addr(col_addr_t'range) <= col_addr;
- when SD_WRITE =>
- phy_ctrl.utag_we <= '1';
- phy_ctrl.drive_en <= '1';
- st_sdr_next <= WRITE;
- sdr_addr(col_addr_t'range) <= col_addr;
- when others => null;
- end case;
- end if;
- end if;
-
- when WRITE =>
- phy_ctrl.drive_en <= '1';
- phy_ctrl.we <= '1';
- if burst_finished = '1' then
- if cmd_we = '1' and cmd = SD_WRITE then
- sdr_addr(col_addr_t'range) <= col_addr;
- cmd_ack <= '1';
- burst_load_en <= '1';
- sdr_cmd_ctrl <= COMMAND(cmd);
- phy_ctrl.utag_we <= '1';
- else
- phy_ctrl.drive_en <= '0';
- cc_load_en <= '1';
- cc_preset <= TIMING(SD_WRITE)+1;
- st_sdr_next <= ROW_ACT;
- end if;
- end if;
-
- when READ =>
- phy_ctrl.re <= '1';
- if burst_finished = '1' then
- if cmd_we = '1' and cmd = SD_READ then
- sdr_addr(col_addr_t'range) <= col_addr;
- cmd_ack <= '1';
- burst_load_en <= '1';
- sdr_cmd_ctrl <= COMMAND(cmd);
- phy_ctrl.utag_we <= '1';
- else
- cc_load_en <= '1';
- cc_preset <= TIMING(SD_READ);
- st_sdr_next <= ROW_ACT;
- end if;
- end if;
-
- when WRITE_A => -- not implemented yet
- cmd_ack <= '1';
- st_sdr_next <= IDLE;
-
- when READ_A => -- not implemented yet
- cmd_ack <= '1';
- st_sdr_next <= IDLE;
-
- when BURST_STOP => -- not implemented yet
- cmd_ack <= '1';
- st_sdr_next <= IDLE;
-
- when SELF_REF => -- not implemented yet
- cmd_ack <= '1';
- st_sdr_next <= IDLE;
-
- when PRE_PWR_DOWN => -- not implemented yet
- cmd_ack <= '1';
- st_sdr_next <= IDLE;
-
- when ACT_PWR_DOWN => -- not implemented yet
- cmd_ack <= '1';
- st_sdr_next <= IDLE;
-
- when AUTO_REF =>
- if cycle_finished = '1' then
- st_sdr_next <= IDLE;
- end if;
-
- when others =>
- st_sdr_next <= IDLE;
- end case;
-
- end process;
-
-fsm_sdr_state_next:
- process (rst, clk)
- begin
- if rst = '1' then
- st_sdr <= PWR_DOWN;
- elsif rising_edge(clk) then
- st_sdr <= st_sdr_next;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-cycle_counter:
- process (rst, clk)
- variable cycle_cnt : natural range 0 to 10;
- begin
- if rst = '1' then
- cycle_cnt := 0;
- cycle_finished <= '0';
- elsif rising_edge(clk) then
- cycle_finished <= '0';
- if cc_load_en = '1' then
- cycle_cnt := cc_preset;
- elsif cycle_cnt /= 0 then
- cycle_cnt := cycle_cnt - 1;
- else
- cycle_finished <= '1';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-burst_counter:
- process (rst, clk)
- variable burst_cnt : natural range 0 to 3;
- begin
- if rst = '1' then
- burst_cnt := 0;
- elsif rising_edge(clk) then
- burst_finished <= '0';
- if burst_load_en = '1' then
- burst_cnt := burst_preset;
- elsif burst_cnt /= 0 then
- burst_cnt := burst_cnt - 1;
- end if;
- if burst_cnt = 0 then
- burst_finished <= '1';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-end behaviour;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd
deleted file mode 100644
index b62e085..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: User SDRAM component adjustments
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package sdram_config is
-
- constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width
- constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
- constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
- constant DDR_ROW_ADDR_WIDTH : positive := 13; --
- constant DDR_COL_ADDR_WIDTH : positive := 9; --
-
- constant LMR_REG_BASE : natural := 0;
- constant LMR_REG_EXTENDED : natural := 1;
- constant LMR_OP_NORMAL : natural := 0;
- constant LMR_OP_RES_DLL : natural := 2;
- constant LMR_BT_SEQ : natural := 0;
- constant LMR_BT_ILVD : natural := 1;
- constant LMR_BL2 : natural := 1;
- constant LMR_BL4 : natural := 2;
- constant LMR_BL8 : natural := 3;
- constant LMR_CL2 : natural := 2;
- constant LMR_CL3 : natural := 3;
- constant LMR_CL2_5 : natural := 6;
-
- -- DDR SDRAM Hardware defined constants
- constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
- constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
- constant ENABLE_PRE_ALL : std_logic := '1';
- constant ENABLE_AUTO_PRE : std_logic := '0';
-
- -- DDR-SDR TIMING constants ------------------------------------------------------------------
- -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
- constant REFRESH_INTERVAL : real := 7.8125; -- us
-
- -- These values are for your SDRAM part (see datasheet)
- constant TCAS : positive := 2; -- CAS latency [clocks]
- constant TRP : positive := 2; -- precharge command period
- constant TRAS : positive := 4; -- active to precharge delay
- constant TRFC : positive := 8; -- auto refresh command period
- constant TMRD : positive := 2; -- load mode register command cylce time
- constant TRCD : positive := 2; -- active to read or write delay !
- constant TWR : positive := 2; -- write recovery time
-
- constant PWR_UP_WAIT : natural := 1; -- µs
-
- subtype user_tag_t is unsigned(3 downto 0);
-
- ----------------------------------------------------------------------------------------------
-
-end sdram_config;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd
deleted file mode 100644
index dbb5b80..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd
+++ /dev/null
@@ -1,487 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: SDRAM main controller and user I/F
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity sdram_ctrl is
- Generic
- (
- f_sysclk : natural := 100E6;
- BL : natural := 2
- );
- Port (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- u_busy : out STD_LOGIC;
- u_tag_in : in user_tag_t;
- u_tag_out : out user_tag_t;
- u_addr : in user_addr_t;
- u_cmd : in user_cmd_t;
- u_cmd_we : in STD_LOGIC;
- col_addr : out col_addr_t;
- sdr_cmd_busy : in STD_LOGIC;
- sdr_cmd : out sdr_cmd_t;
- sdr_cmd_we : out STD_LOGIC;
- sdr_mode : out mode_word_t;
- sdr_cke : out STD_LOGIC
- );
-end sdram_ctrl;
-
-architecture behaviour of sdram_ctrl is
-
- constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL);
-
- type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH);
- signal st_ctrl, st_ctrl_next : ctrl_state_t;
-
- constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
- signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
- signal pwr_up_cnt_rst : std_logic;
- signal pwr_up_finished : std_logic;
-
- signal cycle_cnt : natural range 0 to 255;
- signal cc_preset : natural range 0 to 255;
- signal cc_load_en : std_logic;
- signal cycle_finished : std_logic;
-
- signal seq_cnt : natural range 0 to 31;
- signal seq_rst_en : std_logic;
- signal seq_cnt_en : std_logic;
-
- constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
- signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
- signal refresh_request : std_logic;
- signal refresh_cnt_rst : std_logic;
-
- signal addr_reg_load_en : std_logic;
-
- signal u_tag_reg : user_tag_t;
- signal bank_addr_reg : bank_addr_t;
- signal row_addr_reg : row_addr_t;
- signal col_addr_reg : col_addr_t;
-
- signal u_bank_addr : bank_addr_t;
- signal u_row_addr : row_addr_t;
- signal u_col_addr : col_addr_t;
-
- signal act_request : std_logic;
- signal act_request_set : std_logic;
- signal act_request_clr : std_logic;
-
- type init_seq_rom_t is array (0 to 14) of init_seq_t;
-
- constant init_seq_rom : init_seq_rom_t :=
- (
- (
- cmd => SD_NOP,
- mode_word => (others => '0'),
- wait_cycle => 0
- ),
- (
- cmd => SD_PRE,
- mode_word => "000010000000000",
- wait_cycle => 0
- ),
- (
- cmd => SD_NOP,
- mode_word => (others => '0'),
- wait_cycle => 0
- ),
- (
- cmd => SD_LMR,
- mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010",
- wait_cycle => 0
- ),
- (
- cmd => SD_NOP,
- mode_word => (others => '0'),
- wait_cycle => 0
- ),
- (
- cmd => SD_LMR,
- mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
- wait_cycle => 200
- ),
- (
- cmd => SD_NOP,
- mode_word => (others => '0'),
- wait_cycle => 0
- ),
- (
- cmd => SD_PRE,
- mode_word => "000010000000000",
- wait_cycle => 0
- ),
- (
- cmd => SD_NOP,
- mode_word => (others => '0'),
- wait_cycle => 0
- ),
- (
- cmd => SD_AR,
- mode_word => (others => '0'),
- wait_cycle => 0
- ),
- (
- cmd => SD_NOP,
- mode_word => (others => '0'),
- wait_cycle => 0
- ),
- (
- cmd => SD_AR,
- mode_word => (others => '0'),
- wait_cycle => 0
- ),
- (
- cmd => SD_NOP,
- mode_word => (others => '0'),
- wait_cycle => 0
- ),
- (
- cmd => SD_LMR,
- mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
- wait_cycle => 200
- ),
- (
- cmd => SD_NOP,
- mode_word => (others => '0'),
- wait_cycle => 0
- )
-
- );
-
-begin
-
- u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
- u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
- u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
-
-------------------------------------------------------------------------------------------
-fsm_ctrl_state:
- process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request)
- begin
-
- u_busy <= '1';
- pwr_up_cnt_rst <= '0';
- cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
- cc_load_en <= '0';
- sdr_cmd <= init_seq_rom(seq_cnt).cmd;
- sdr_cmd_we <= '0';
- sdr_mode <= bank_addr_reg & row_addr_reg;
- col_addr <= col_addr_reg;
- sdr_cke <= '1';
- seq_cnt_en <= '0';
- seq_rst_en <= '0';
- addr_reg_load_en <= '0';
- refresh_cnt_rst <= '0';
- act_request_set <= '0';
- act_request_clr <= '0';
- u_tag_out <= u_tag_reg;
-
- st_ctrl_next <= st_ctrl;
- case st_ctrl is
- when RESET =>
- sdr_cke <= '0';
- pwr_up_cnt_rst <= '1';
- st_ctrl_next <= POWER_WAIT;
-
- when POWER_WAIT =>
- sdr_cke <= '0';
- if pwr_up_finished = '1' then
- seq_rst_en <= '1';
- st_ctrl_next <= INIT;
- end if;
-
- when INIT =>
- sdr_mode <= init_seq_rom(seq_cnt).mode_word;
- sdr_cmd <= init_seq_rom(seq_cnt).cmd;
- cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
- if seq_cnt = init_seq_rom_t'high then
- act_request_set <= '1';
- refresh_cnt_rst <= '1';
- st_ctrl_next <= USER_READY;
- elsif sdr_cmd_busy = '0' then
- cc_load_en <= '1';
- sdr_cmd_we <= '1';
- st_ctrl_next <= INIT_WAIT;
- end if;
-
- when INIT_WAIT =>
- if sdr_cmd_busy = '0' and cycle_finished = '1' then
- seq_cnt_en <= '1';
- st_ctrl_next <= INIT;
- end if;
-
- when USER_READY =>
- if sdr_cmd_busy = '0' then
- if refresh_request = '1' then
- sdr_mode(BIT_PRE_ALL) <= '1';
- sdr_cmd_we <= '1';
- sdr_cmd <= SD_PRE;
- st_ctrl_next <= REFRESH;
- else
- u_busy <= '0';
- if u_cmd_we = '1' then
- case u_cmd is
- when UCMD_NOP =>
- sdr_cmd <= SD_NOP;
- when UCMD_LMR =>
- sdr_cmd <= SD_NOP;
- when UCMD_WRITE =>
- col_addr <= u_col_addr;
- u_tag_out <= u_tag_in;
- sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
- addr_reg_load_en <= '1';
- act_request_clr <= '1';
- sdr_cmd <= SD_WRITE;
- if (u_row_addr /= row_addr_reg) or act_request = '1' then
- st_ctrl_next <= USER_WRITE_PRE;
- elsif (u_bank_addr /= bank_addr_reg) then
- if ENABLE_PRE_ALL = '1' then
- st_ctrl_next <= USER_WRITE_ACT;
- else
- st_ctrl_next <= USER_WRITE_PRE;
- end if;
- elsif sdr_cmd_busy = '0' then
- sdr_cmd_we <= '1';
- else
- st_ctrl_next <= USER_WRITE;
- end if;
- when UCMD_READ =>
- col_addr <= u_col_addr;
- u_tag_out <= u_tag_in;
- sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
- addr_reg_load_en <= '1';
- act_request_clr <= '1';
- sdr_cmd <= SD_READ;
- if (u_row_addr /= row_addr_reg) or act_request = '1' then
- st_ctrl_next <= USER_READ_PRE;
- elsif (u_bank_addr /= bank_addr_reg) then
- if ENABLE_PRE_ALL = '1' then
- st_ctrl_next <= USER_READ_ACT;
- else
- st_ctrl_next <= USER_READ_PRE;
- end if;
- elsif sdr_cmd_busy = '0' then
- sdr_cmd_we <= '1';
- else
- st_ctrl_next <= USER_READ;
- end if;
- when others => null;
- end case;
- end if;
- end if;
- end if;
-
- when USER_WRITE_PRE =>
- sdr_cmd <= SD_PRE;
- sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
- if sdr_cmd_busy = '0' then
- sdr_cmd_we <= '1';
- st_ctrl_next <= USER_WRITE_ACT;
- end if;
-
- when USER_WRITE_ACT =>
- sdr_cmd <= SD_ACT;
- if sdr_cmd_busy = '0' then
- sdr_cmd_we <= '1';
- st_ctrl_next <= USER_WRITE;
- end if;
-
- when USER_WRITE =>
- sdr_cmd <= SD_WRITE;
- sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
- if sdr_cmd_busy = '0' then
- sdr_cmd_we <= '1';
- st_ctrl_next <= USER_READY;
- end if;
-
- when USER_READ_PRE =>
- sdr_cmd <= SD_PRE;
- sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
- if sdr_cmd_busy = '0' then
- sdr_cmd_we <= '1';
- st_ctrl_next <= USER_READ_ACT;
- end if;
-
- when USER_READ_ACT =>
- sdr_cmd <= SD_ACT;
- if sdr_cmd_busy = '0' then
- sdr_cmd_we <= '1';
- st_ctrl_next <= USER_READ;
- end if;
-
- when USER_READ =>
- sdr_cmd <= SD_READ;
- sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
- if sdr_cmd_busy = '0' then
- sdr_cmd_we <= '1';
- st_ctrl_next <= USER_READY;
- end if;
-
- when REFRESH =>
- sdr_cmd <= SD_AR;
- if sdr_cmd_busy = '0' then
- sdr_cmd_we <= '1';
- st_ctrl_next <= USER_READY;
- refresh_cnt_rst <= '1';
- act_request_set <= '1';
- end if;
-
- when others =>
- st_ctrl_next <= RESET;
- end case;
-
- end process;
-
-fsm_ctrl_state_next:
- process (rst, clk)
- begin
- if rst = '1' then
- st_ctrl <= RESET;
- elsif rising_edge(clk) then
- st_ctrl <= st_ctrl_next;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-act_request_register:
- process (rst, clk)
- begin
- if rst = '1' then
- act_request <= '1';
- elsif rising_edge(clk) then
- if act_request_set = '1' then
- act_request <= '1';
- elsif act_request_clr = '1' then
- act_request <= '0';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-user_addr_register:
- process (rst, clk)
- begin
- if rst = '1' then
- bank_addr_reg <= (others => '0');
- row_addr_reg <= (others => '0');
- col_addr_reg <= (others => '0');
- u_tag_reg <= (others => '0');
- elsif rising_edge(clk) then
- if addr_reg_load_en = '1' then
- bank_addr_reg <= u_bank_addr;
- row_addr_reg <= u_row_addr;
- col_addr_reg <= u_col_addr;
- u_tag_reg <= u_tag_in;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-power_up_counter:
- process (rst, clk)
- begin
- if rst = '1' then
- pwr_up_cnt <= 0;
- pwr_up_finished <= '0';
- elsif rising_edge(clk) then
- pwr_up_finished <= '0';
- if pwr_up_cnt_rst = '1' then
- pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1;
- else
- if pwr_up_cnt /= 0 then
- pwr_up_cnt <= pwr_up_cnt - 1;
- else
- pwr_up_finished <= '1';
- end if;
- end if;
- end if;
- end process;
-
-
-------------------------------------------------------------------------------------------
-refresh_counter:
- process (rst, clk)
- begin
- if rst = '1' then
- refresh_cnt <= 0;
- refresh_request <= '0';
- elsif rising_edge(clk) then
- refresh_request <= '0';
- if refresh_cnt_rst = '1' then
- refresh_cnt <= REFRESH_CLOCK_INTERVAL-1;
- else
- if refresh_cnt /= 0 then
- refresh_cnt <= refresh_cnt - 1;
- else
- refresh_request <= '1';
- end if;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-cycle_counter:
- process (rst, clk)
- begin
- if rst = '1' then
- cycle_cnt <= 0;
- cycle_finished <= '0';
- elsif rising_edge(clk) then
- cycle_finished <= '0';
- if cc_load_en = '1' then
- cycle_cnt <= cc_preset;
- elsif cycle_cnt /= 0 then
- cycle_cnt <= cycle_cnt - 1;
- else
- cycle_finished <= '1';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-seq_counter:
- process (rst, clk)
- begin
- if rst = '1' then
- seq_cnt <= 0;
- elsif rising_edge(clk) then
- if seq_rst_en = '1' then
- seq_cnt <= 0;
- elsif seq_cnt_en = '1' then
- if seq_cnt /= init_seq_rom_t'high then
- seq_cnt <= seq_cnt + 1;
- end if;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
-end behaviour;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd
deleted file mode 100644
index 268636e..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd
+++ /dev/null
@@ -1,293 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_ctrl_frontend is
- Generic
- (
- BL : natural := 2;
- f_sysclk : natural := 100E6;
- read_phaseshift : integer := 0;
- fifo_depth : integer := 4
- );
- Port
- (
- sys_rst_in : in STD_LOGIC;
- sys_clk_in : in STD_LOGIC;
- sys_rst_out : out STD_LOGIC;
- sys_clk_out : out STD_LOGIC;
- sys_clk_fb : in STD_LOGIC;
-
- -- User interface
- busy : out STD_LOGIC;
- en : in STD_LOGIC;
- r_wn : in STD_LOGIC;
- be : in unsigned(SDR_DM_WIDTH-1 downto 0);
- addr : in user_addr_t;
- din : in unsigned(SDR_DATA_WIDTH-1 downto 0);
- dout : out unsigned(SDR_DATA_WIDTH-1 downto 0);
- dout_re : in STD_LOGIC;
- dout_vld : out STD_LOGIC;
-
- -- SDRAM signals
- sd_clk_p : out STD_LOGIC;
- sd_clk_n : out STD_LOGIC;
- sd_cke : out STD_LOGIC;
- sd_cs_n : out STD_LOGIC;
- sd_cas_n : out STD_LOGIC;
- sd_ras_n : out STD_LOGIC;
- sd_we_n : out STD_LOGIC;
- sd_addr : out sdr_addr_t;
- sd_ba : out sdr_ba_t;
- sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
- sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
- sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
-
- );
-end sdram_ctrl_frontend;
-
-architecture struct of sdram_ctrl_frontend is
-
- -- Number of user data words for simulation
- signal rst_out : std_logic;
- signal clk_out : std_logic;
-
- signal u_addr : user_addr_t;
- signal u_tag_in : user_tag_t;
- signal u_tag_rd : user_tag_t;
- signal u_tag_wr : user_tag_t;
- signal u_cmd : user_cmd_t;
- signal u_cmd_we : std_logic;
- signal u_busy : std_logic;
- signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0);
- signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0);
- signal u_dm_rd_in : unsigned(SDR_DM_WIDTH-1 downto 0);
- signal u_dm_rd_out : unsigned(SDR_DM_WIDTH-1 downto 0);
- signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
- signal u_data_vld : std_logic;
- signal u_req_wr : std_logic;
- signal rdy : std_logic;
-
- constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + SDR_DM_WIDTH;
- signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
- signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
- signal cat_fifo_re : std_logic;
- signal cat_fifo_we : std_logic;
- signal cat_fifo_full : std_logic;
- signal cat_fifo_empty : std_logic;
--- signal cat_fifo_almost_full : std_logic;
--- signal cat_fifo_almost_empty : std_logic;
-
- signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
- signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
- signal write_fifo_re : std_logic;
- signal write_fifo_we : std_logic;
- signal write_fifo_full : std_logic;
- signal write_fifo_empty : std_logic;
--- signal write_fifo_almost_full : std_logic;
--- signal write_fifo_almost_empty : std_logic;
-
- signal read_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
- signal read_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
- signal read_fifo_re : std_logic;
- signal read_fifo_we : std_logic;
- signal read_fifo_full : std_logic;
- signal read_fifo_empty : std_logic;
--- signal read_fifo_almost_full : std_logic;
--- signal read_fifo_almost_empty : std_logic;
-
- alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
- alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
- alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH);
- alias dm_rd_fifo_in is cat_fifo_din(SDR_DM_WIDTH-1 downto 0);
- alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
- alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
- alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH);
- alias dm_rd_fifo_out is cat_fifo_dout(SDR_DM_WIDTH-1 downto 0);
-
- alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH);
- alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0);
- alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH);
- alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0);
-
- alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-SDR_DM_WIDTH);
- alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-SDR_DM_WIDTH-1 downto 0);
- alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-SDR_DM_WIDTH);
- alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-SDR_DM_WIDTH-1 downto 0);
-
-begin
-
- -- Instantiate synchronous FIFO
- inst_cat_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => fifo_depth,
- data_width => CAT_FIFO_WIDTH
- )
- PORT MAP
- (
- rst => rst_out,
- clk => clk_out,
- we => cat_fifo_we,
- re => cat_fifo_re,
- fifo_full => cat_fifo_full,
- fifo_empty => cat_fifo_empty,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => cat_fifo_din,
- data_r => cat_fifo_dout
- );
-
- -- Instantiate synchronous FIFO
- inst_write_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => fifo_depth,
- data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH
- )
- PORT MAP
- (
- rst => rst_out,
- clk => clk_out,
- we => write_fifo_we,
- re => write_fifo_re,
- fifo_full => write_fifo_full,
- fifo_empty => write_fifo_empty,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => write_fifo_din,
- data_r => write_fifo_dout
- );
-
- -- Instantiate synchronous FIFO
- inst_read_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => fifo_depth,
- data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH
- )
- PORT MAP
- (
- rst => rst_out,
- clk => clk_out,
- we => read_fifo_we,
- re => read_fifo_re,
- fifo_full => read_fifo_full,
- fifo_empty => read_fifo_empty,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => read_fifo_din,
- data_r => read_fifo_dout
- );
-
- -- DDR SDRAM Controller Core
- inst_sdram_ctrl : entity work.sdram_ctrl_top
- Generic map
- (
- BL => BL,
- read_phaseshift => read_phaseshift,
- f_sysclk => f_sysclk
- )
- Port map
- (
-
- sys_rst_in => sys_rst_in,
- sys_clk_in => sys_clk_in,
-
- sys_rst_out => rst_out,
- sys_clk_out => clk_out,
- sys_clk_fb => sys_clk_fb,
-
- -- User interface
- u_data_vld => u_data_vld,
- u_data_req_w => u_req_wr,
- u_data_req_r => open,
- u_tag_in => u_tag_in,
- u_tag_rd => u_tag_rd,
- u_tag_wr => u_tag_wr,
- u_busy => u_busy,
- u_addr => u_addr,
- u_cmd => u_cmd,
- u_cmd_we => u_cmd_we,
- u_data_wr => u_data_w,
- u_data_rd => u_data_r,
- u_dm_wr_in => u_dm_wr_in,
- u_dm_rd_in => u_dm_rd_in,
- u_dm_rd_out => u_dm_rd_out,
-
- -- SDRAM signals
- sd_clk_p => sd_clk_p,
- sd_clk_n => sd_clk_n,
- sd_cke => sd_cke,
- sd_cs_n => sd_cs_n,
- sd_cas_n => sd_cas_n,
- sd_ras_n => sd_ras_n,
- sd_we_n => sd_we_n,
- sd_addr => sd_addr,
- sd_ba => sd_ba,
- sd_dm => sd_dm,
- sd_dqs => sd_dqs,
- sd_data => sd_data
-
- );
-
-------------------------------------------------------------------------------------------
- sys_rst_out <= rst_out;
- sys_clk_out <= clk_out;
- busy <= not rdy;
- rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full);
- write_fifo_we <= en and not r_wn and rdy;
- write_fifo_data_in <= din;
- write_fifo_dm_in <= not be;
- cat_fifo_we <= en and rdy;
- cmd_fifo_in <= UCMD_WRITE when r_wn = '0' else UCMD_READ;
- addr_fifo_in <= addr;
- dm_rd_fifo_in <= not be;
- tag_fifo_in <= (others=>'0');
- dout <= read_fifo_data_out;
- dout_vld <= not read_fifo_empty;
-
- u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
- u_cmd <= cmd_fifo_out;
- u_addr <= addr_fifo_out;
- u_dm_rd_in <= dm_rd_fifo_out;
- u_dm_wr_in <= write_fifo_dm_out;
- u_tag_in <= tag_fifo_out;
-
- write_fifo_re <= u_req_wr and (not write_fifo_empty);
- cat_fifo_re <= u_cmd_we;
- u_data_w <= write_fifo_data_out;
- read_fifo_re <= (not read_fifo_empty) and dout_re;
- read_fifo_we <= u_data_vld;
- read_fifo_data_in <= u_data_r;
- read_fifo_dm_in <= u_dm_rd_out;
-
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd
deleted file mode 100644
index 19768a4..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd
+++ /dev/null
@@ -1,289 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Top-level put all together
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_ctrl_top is
- Generic
- (
- BL : natural := 2;
- f_sysclk : natural := 100E6;
- read_phaseshift : integer := 0
- );
- Port
- (
- sys_rst_in : in STD_LOGIC;
- sys_clk_in : in STD_LOGIC;
- sys_rst_out : out STD_LOGIC;
- sys_clk_out : out STD_LOGIC;
- sys_clk_fb : in STD_LOGIC;
-
- -- User interface
- u_data_vld : out STD_LOGIC;
- u_data_req_w : out STD_LOGIC;
- u_data_req_r : out STD_LOGIC;
- u_busy : out STD_LOGIC;
- u_tag_in : in user_tag_t;
- u_tag_rd : out user_tag_t;
- u_tag_wr : out user_tag_t;
- u_addr : in user_addr_t;
- u_cmd : in user_cmd_t;
- u_cmd_we : in STD_LOGIC;
- u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0);
- u_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
- u_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
- u_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0);
- u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0);
-
- -- SDRAM signals
- sd_clk_p : out STD_LOGIC;
- sd_clk_n : out STD_LOGIC;
- sd_cke : out STD_LOGIC;
- sd_cs_n : out STD_LOGIC;
- sd_cas_n : out STD_LOGIC;
- sd_ras_n : out STD_LOGIC;
- sd_we_n : out STD_LOGIC;
- sd_addr : out sdr_addr_t;
- sd_ba : out sdr_ba_t;
- sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
- sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
- sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
-
- );
-end sdram_ctrl_top;
-
-architecture rtl of sdram_ctrl_top is
-
- signal clk0 : std_logic;
- signal clk270 : std_logic;
- signal read_clk270 : std_logic;
-
- signal phy_ctrl : phy_ctrl_t;
-
- signal u_tag : user_tag_t;
- signal sd_cmd_in : sdr_cmd_t;
- signal sd_cmd : sdr_cmd_t;
- signal sd_cmd_we : std_logic;
- signal cmd_ctrl : sdr_cmd_lines_t;
- signal cke : std_logic;
- signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0);
- signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0);
-
- -- Clock generator
-
- signal cg_rst : std_logic;
- signal cg_read_clk0 : std_logic;
- signal cg_read_clk270 : std_logic;
- signal cg_sys_clk0 : std_logic;
- signal cg_sys_clk270 : std_logic;
- signal cg_locked : std_logic;
- signal cg_error : std_logic;
- signal ctrl_rst : std_logic;
- signal part_ctrl : part_ctrl_t;
-
- -- SD command FIFO
-
- constant CMD_FIFO_ADDR_WIDTH : positive := 2;
- constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
- signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
- signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
- signal cmd_fifo_re : std_logic;
- signal cmd_fifo_we : std_logic;
- signal cmd_fifo_full : std_logic;
- signal cmd_fifo_empty : std_logic;
-
- alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
- alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
- alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
- alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
-
- alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
- alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
- alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
- alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
-
-begin
-
- ---------------------------------
- clk0 <= cg_sys_clk0;
- clk270 <= cg_sys_clk270;
- read_clk270 <= cg_read_clk270;
- cg_rst <= not cg_locked;
-
- ---------------------------------
- sys_clk_out <= cg_sys_clk0;
- sys_rst_out <= ctrl_rst;
-
- ---------------------------------
- part_ctrl.cmd <= cmd_ctrl;
- part_ctrl.ba <= ba;
- part_ctrl.addr <= addr;
- part_ctrl.cke <= cke;
-
- ---------------------------------
- sd_cmd_we <= not cmd_fifo_empty;
- cmd_fifo_in <= to_unsigned(sd_cmd_in, 4);
- sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out));
-
- ---------------------------------
- inst_reset: entity work.reset
- port map
- (
- clk => clk0,
- rst_in => cg_rst,
- rst_out => ctrl_rst
- );
-
- inst_clockgen : entity work.clockgen
- generic map
- (
- read_phaseshift => read_phaseshift,
- frequency_hz => f_sysclk
- )
- port map
- (
- rst => sys_rst_in,
- clk_in => sys_clk_in,
- clk_fb_in => sys_clk_fb,
- read_clk0_out => cg_read_clk0,
- read_clk270_out => cg_read_clk270,
- sys_clk0_out => cg_sys_clk0,
- sys_clk270_out => cg_sys_clk270,
- locked_out => cg_locked,
- error_out => cg_error
- );
-
- -- Main controller
- inst_sdram_ctrl : entity work.sdram_ctrl
- Generic map
- (
- f_sysclk => 100E6,
- BL => BL
- )
- Port map
- (
- rst => ctrl_rst,
- clk => clk0,
- u_busy => u_busy,
- u_tag_in => u_tag_in,
- u_tag_out => tag_fifo_in,
- u_cmd => u_cmd,
- u_cmd_we => u_cmd_we,
- u_addr => u_addr,
- sdr_cmd_busy => cmd_fifo_full,
- sdr_cmd => sd_cmd_in,
- sdr_cmd_we => cmd_fifo_we,
- col_addr => col_fifo_in,
- sdr_mode => mode_fifo_in,
- sdr_cke => cke
- );
-
- -- Instantiate synchronous FIFO
- inst_sd_cmd_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => CMD_FIFO_ADDR_WIDTH,
- data_width => CMD_FIFO_DATA_WIDTH,
- almost_full_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1),
- almost_empty_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1)
- )
- PORT MAP
- (
- rst => ctrl_rst,
- clk => clk0,
- we => cmd_fifo_we,
- re => cmd_fifo_re,
- fifo_full => cmd_fifo_full,
- fifo_empty => cmd_fifo_empty,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => cmd_fifo_din,
- data_r => cmd_fifo_dout
- );
-
- -- DDR SDRAM command fsm
- inst_sdram_cmd : entity work.sdram_cmd
- Generic map
- (
- BL => BL
- )
- Port map
- (
- rst => ctrl_rst,
- clk => clk0,
- u_tag_in => tag_fifo_out,
- u_tag_out => u_tag,
- phy_ctrl => phy_ctrl,
- enable => cke,
- cmd => sd_cmd,
- cmd_we => sd_cmd_we,
- cmd_ack => cmd_fifo_re,
- sdr_cmd_ctrl => cmd_ctrl,
- col_addr => col_fifo_out,
- mode_word => mode_fifo_out,
- sdr_ba => ba,
- sdr_addr => addr
- );
-
- -- DDR phy
- inst_ddr_phy : entity work.ddr_phy
- Port map
- (
- sys_rst => ctrl_rst,
- sys_clk0 => clk0,
- sys_clk270 => clk270,
- u_tag_in => u_tag,
- u_tag_rd => u_tag_rd,
- u_tag_wr => u_tag_wr,
- read_clk => read_clk270,
- phy_ctrl => phy_ctrl,
- part_ctrl => part_ctrl,
- sdr_data_req_w => u_data_req_w,
- sdr_data_req_r => u_data_req_r,
- sdr_data_w => u_data_wr,
- sdr_dm_wr_in => u_dm_wr_in,
- sdr_dm_rd_in => u_dm_rd_in,
- sdr_dm_rd_out => u_dm_rd_out,
- sdr_data_r => u_data_rd,
- sdr_data_vld => u_data_vld,
- part_clk_p => sd_clk_p,
- part_clk_n => sd_clk_n,
- part_addr => sd_addr,
- part_ba => sd_ba,
- part_dm => sd_dm,
- part_dqs => sd_dqs,
- part_data => sd_data,
- part_cs_n => sd_cs_n,
- part_we_n => sd_we_n,
- part_cas_n => sd_cas_n,
- part_ras_n => sd_ras_n,
- part_cke => sd_cke
- );
-
-end architecture rtl;
-
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd
deleted file mode 100644
index d235d75..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd
+++ /dev/null
@@ -1,133 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Type definitions
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.sdram_config.all;
-
-package sdram_types is
-
- -----------------------------------------------------------------------------------------
- -- Table of Timing Parameters as a function of operation
-
- -- Derived constants from sdram_config
-
- constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
- constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
- constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; --
- constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; --
-
- subtype user_cmd_t is unsigned(1 downto 0);
- constant UCMD_NOP : user_cmd_t := "00";
- constant UCMD_READ : user_cmd_t := "01";
- constant UCMD_WRITE : user_cmd_t := "10";
- constant UCMD_LMR : user_cmd_t := "11";
-
- subtype sdr_cmd_t is natural range 0 to 9;
- constant SD_DESELECT : sdr_cmd_t := 0;
- constant SD_NOP : sdr_cmd_t := 1;
- constant SD_LMR : sdr_cmd_t := 2;
- constant SD_ACT : sdr_cmd_t := 3;
- constant SD_READ : sdr_cmd_t := 4;
- constant SD_WRITE : sdr_cmd_t := 5;
- constant SD_PRE : sdr_cmd_t := 6;
- constant SD_BST : sdr_cmd_t := 7;
- constant SD_AR : sdr_cmd_t := 8;
- constant SD_SR : sdr_cmd_t := 9;
-
- type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
- subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
- subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
- subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
- subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);
-
- subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
- subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
- subtype col_addr_t is unsigned(8 downto 0);
-
- subtype cycle_cnt_t is natural range 0 to 10;
-
- type phy_ctrl_t is
- record
- drive_en : std_logic;
- re : std_logic;
- we : std_logic;
- utag_we : std_logic;
- end record phy_ctrl_t;
-
- type sdr_cmd_lines_t is
- record
- cs_n : std_logic;
- ras_n : std_logic;
- cas_n : std_logic;
- we_n : std_logic;
- end record sdr_cmd_lines_t;
-
- type part_ctrl_t is
- record
- cmd : sdr_cmd_lines_t;
- ba : unsigned(DDR_BANK_WIDTH-1 downto 0);
- addr : unsigned(DDR_ADDR_WIDTH-1 downto 0);
- cke : std_logic;
- end record part_ctrl_t;
-
- type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
- constant COMMAND : part_cmd_array_t :=
- -- command cs_n ras_qn cas_qn we_qn
- ( SD_DESELECT => ( '1', '1', '1', '1'),
- SD_NOP => ( '0', '1', '1', '1'),
- SD_LMR => ( '0', '0', '0', '0'),
- SD_ACT => ( '0', '0', '1', '1'),
- SD_READ => ( '0', '1', '0', '1'),
- SD_WRITE => ( '0', '1', '0', '0'),
- SD_PRE => ( '0', '0', '1', '0'),
- SD_BST => ( '0', '1', '1', '0'),
- SD_AR => ( '0', '0', '0', '1'),
- SD_SR => ( '0', '0', '0', '1')
- );
-
- type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
- constant TIMING : part_timing_array_t :=
- -- command cycle_cnt
- ( SD_DESELECT => ( 0 ),
- SD_NOP => ( 0 ),
- SD_LMR => ( TMRD-1 ),
- SD_ACT => ( TRCD-1 ),
- SD_READ => ( TCAS-1 ),
- SD_WRITE => ( TWR-1 ),
- SD_PRE => ( TRP-1 ),
- SD_BST => ( 0 ),
- SD_AR => ( TRFC-1 ),
- SD_SR => ( TRFC-1 )
- );
-
- type init_seq_t is
- record
- cmd : sdr_cmd_t;
- mode_word : mode_word_t;
- wait_cycle : natural;
- end record init_seq_t;
-
-end sdram_types;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd
deleted file mode 100644
index 034215c..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd
+++ /dev/null
@@ -1,336 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
- -- Number of user data words for simulation
- constant CLK_PERIOD : time := 10 ns;
- constant BURST_LEN : natural := 8;
-
- signal rst : std_logic := '1';
- signal clk : std_logic := '0';
- signal rst_out : std_logic;
- signal clk_out : std_logic;
- signal clk_fb : std_logic;
- signal part_clk_p : std_logic;
- signal part_clk_n : std_logic;
- signal part_cke : std_logic;
- signal part_cs_n : std_logic;
- signal part_we_n : std_logic;
- signal part_ras_n : std_logic;
- signal part_cas_n : std_logic;
- signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
- signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
- signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
- signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
- signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- signal u_addr : user_addr_t := (others => '0');
- signal u_tag_in : user_tag_t := "0000";
- signal u_tag_rd : user_tag_t;
- signal u_tag_wr : user_tag_t;
- signal u_cmd : user_cmd_t := UCMD_NOP;
- signal u_cmd_we : std_logic := '0';
- signal u_busy : std_logic;
- signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_data_vld : std_logic;
- signal u_req_wr : std_logic;
- signal u_req_rd : std_logic;
- signal u_read_en : std_logic := '0';
- signal u_write_en : std_logic := '0';
- signal u_addr_cnt_en : std_logic := '0';
- signal u_addr_load : std_logic := '0';
- signal u_addr_preset : user_addr_t := (others => '0');
- signal u_addr_end : user_addr_t := (others => '0');
- signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
- signal test_phase : test_phase_t := IDLE;
-
- type u_addr_mode_t is (MONOTONIC, RANDOM);
- signal u_addr_mode : u_addr_mode_t := MONOTONIC;
- signal cycle_cnt : natural := 1;
- signal data_cnt : natural := 0;
- signal efficiency : real := 0.0;
-
-begin
-
- clk_fb <= part_clk_p after 1 ns;
-
- -- DDR SDRAM Controller Core
- inst_sdram_ctrl : entity work.sdram_ctrl_top
- Generic map
- (
- BL => BURST_LEN,
- read_phaseshift => 0,
- f_sysclk => 100E6
- )
- Port map
- (
-
- sys_rst_in => rst,
- sys_clk_in => clk,
-
- sys_rst_out => rst_out,
- sys_clk_out => clk_out,
- sys_clk_fb => clk_fb,
-
- -- User interface
- u_data_vld => u_data_vld,
- u_data_req_w => u_req_wr,
- u_data_req_r => u_req_rd,
- u_tag_in => u_tag_in,
- u_tag_rd => u_tag_rd,
- u_tag_wr => u_tag_wr,
- u_busy => u_busy,
- u_addr => u_addr,
- u_cmd => u_cmd,
- u_cmd_we => u_cmd_we,
- u_data_wr => u_data_w,
- u_data_rd => u_data_r,
- u_dm_wr_in => u_dm,
- u_dm_rd_in => u_dm_rd_in,
- u_dm_rd_out => u_dm_rd_out,
-
- -- SDRAM signals
- sd_clk_p => part_clk_p,
- sd_clk_n => part_clk_n,
- sd_cke => part_cke,
- sd_cs_n => part_cs_n,
- sd_cas_n => part_cas_n,
- sd_ras_n => part_ras_n,
- sd_we_n => part_we_n,
- sd_addr => part_addr,
- sd_ba => part_ba,
- sd_dm => part_dm,
- sd_dqs => part_dqs,
- sd_data => part_data
-
- );
-
- -- MICRON DDR SDRAM Simulation Model
- i_mt46v16m16_0 : entity work.mt46v16m16
- port map (
- dq => std_logic_vector(part_data),
- dqs => std_logic_vector(part_dqs),
- addr => std_logic_vector(part_addr),
- ba => std_logic_vector(part_ba),
- clk => part_clk_p,
- clk_n => part_clk_n,
- cke => part_cke,
- cs_n => part_cs_n,
- ras_n => part_ras_n,
- cas_n => part_cas_n,
- we_n => part_we_n,
- dm => std_logic_vector(part_dm)
- );
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- clk <= not clk;
- end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_data_vld='1' then
- if u_read_en = '1' then
- assert (ref_data = u_data_r) report "Error on read!" severity failure;
- end if;
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- elsif u_read_en = '0' then
- last_data := (others => '0');
- ref_data <= (others => '0');
- end if;
- end if;
- end process;
-
-W_DATA_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_req_wr = '1' then
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- elsif u_write_en = '0' then
- last_data := (others => '0');
- u_data_w <= (others => '0');
- end if;
- end if;
- end process;
-
-ADDR_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_addr_load = '1' then
- u_addr <= u_addr_preset;
- elsif u_addr_cnt_en = '1' then
- if u_addr_mode = MONOTONIC then
- u_addr <= u_addr + BURST_LEN;
- else
- if u_addr(u_addr'left) = '1' then
- if BURST_LEN = 2 then
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
- elsif BURST_LEN = 4 then
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
- elsif BURST_LEN = 8 then
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
- end if;
- else
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
- end if;
- end if;
- end if;
- end if;
- end process;
-
-performance_count:
- process(clk_out)
- begin
- if rising_edge(clk_out) then
- if u_write_en = '1' or u_read_en = '1' then
- cycle_cnt <= cycle_cnt + 1;
- if u_req_wr = '1' or u_req_rd = '1' then
- data_cnt <= data_cnt + 1;
- end if;
- else
- cycle_cnt <= 1;
- data_cnt <= 0;
- end if;
- end if;
- end process;
-
- u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
-
- efficiency <= real(data_cnt)/real(cycle_cnt);
- u_cmd_we <= (u_write_en or u_read_en) and (not u_busy);
- u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
-
- process
- begin
-
- -- Write MAX_WORDS to DDR SDRAM Controller
- wait for 4*CLK_PERIOD;
- rst <= '0';
-
- wait until rising_edge(clk_out) and u_busy='0';
- wait for 137*CLK_PERIOD;
-
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 0
- u_addr_preset <= X"000000";
- u_addr_end <= X"008000"-BURST_LEN;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_cmd <= UCMD_WRITE;
- u_write_en <= '1';
- while u_addr /= u_addr_end loop
- wait until rising_edge(clk_out);
- end loop;
- u_write_en <= '0';
- wait until rising_edge(clk_out) and u_req_wr='0';
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 1
- u_addr_preset <= X"400000";
- u_addr_end <= X"408000"-BURST_LEN;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_cmd <= UCMD_WRITE;
- u_write_en <= '1';
- while u_addr /= u_addr_end loop
- wait until rising_edge(clk_out);
- end loop;
- u_write_en <= '0';
- wait until rising_edge(clk_out) and u_req_wr='0';
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 0
- u_addr_preset <= X"000000";
- u_addr_end <= X"008000"-BURST_LEN;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_cmd <= UCMD_READ;
- u_read_en <= '1';
- while u_addr /= u_addr_end loop
- wait until rising_edge(clk_out);
- end loop;
- u_read_en <= '0';
- wait until rising_edge(clk_out) and u_data_vld='0';
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 1
- u_addr_preset <= X"400000";
- u_addr_end <= X"408000"-BURST_LEN;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_cmd <= UCMD_READ;
- u_read_en <= '1';
- while u_addr /= u_addr_end loop
- wait until rising_edge(clk_out);
- end loop;
- u_read_en <= '0';
- wait until rising_edge(clk_out) and u_data_vld='0';
-
- wait;
-
- end process;
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd
deleted file mode 100644
index 51910b0..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd
+++ /dev/null
@@ -1,420 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity tb_sdr_ctrl_fifo is
-end;
-
-architecture struct of tb_sdr_ctrl_fifo is
-
- -- Number of user data words for simulation
- constant CLK_PERIOD : time := 10 ns;
- constant BURST_LEN : natural := 2;
-
- signal rst : std_logic := '1';
- signal clk : std_logic := '0';
- signal rst_out : std_logic;
- signal clk_out : std_logic;
- signal clk_fb : std_logic;
- signal part_clk_p : std_logic;
- signal part_clk_n : std_logic;
- signal part_cke : std_logic;
- signal part_cs_n : std_logic;
- signal part_we_n : std_logic;
- signal part_ras_n : std_logic;
- signal part_cas_n : std_logic;
- signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
- signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
- signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
- signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
- signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- signal u_addr : user_addr_t := (others => '0');
- signal u_tag_in : user_tag_t := "0000";
- signal u_tag_rd : user_tag_t;
- signal u_tag_wr : user_tag_t;
- signal u_cmd : user_cmd_t := UCMD_NOP;
- signal u_cmd_we : std_logic := '0';
- signal u_busy : std_logic;
- signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_data_vld : std_logic;
- signal u_req_wr : std_logic;
- signal u_req_rd : std_logic;
- signal u_read_en : std_logic := '0';
- signal u_write_en : std_logic := '0';
-
- signal cmd_fifo_din : unsigned(25 downto 0) := (others => '0');
- signal cmd_fifo_dout : unsigned(25 downto 0) := (others => '0');
- signal cmd_fifo_re : std_logic := '0';
- signal cmd_fifo_we : std_logic := '0';
- signal cmd_fifo_full : std_logic := '0';
- signal cmd_fifo_empty : std_logic := '0';
- signal cmd_fifo_almost_full : std_logic := '0';
- signal cmd_fifo_almost_empty : std_logic := '0';
-
- signal write_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal write_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal write_fifo_re : std_logic := '0';
- signal write_fifo_we : std_logic := '0';
- signal write_fifo_full : std_logic := '0';
- signal write_fifo_empty : std_logic := '0';
- signal write_fifo_almost_full : std_logic := '0';
- signal write_fifo_almost_empty : std_logic := '0';
-
- signal read_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal read_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal read_fifo_re : std_logic := '0';
- signal read_fifo_we : std_logic := '0';
- signal read_fifo_full : std_logic := '0';
- signal read_fifo_empty : std_logic := '0';
- signal read_fifo_almost_full : std_logic := '0';
- signal read_fifo_almost_empty : std_logic := '0';
-
- signal write_start : std_logic := '1';
- signal read_start : std_logic := '1';
-
- alias cmd_fifo_in is cmd_fifo_din(25 downto 24);
- alias addr_fifo_in is cmd_fifo_din(23 downto 0);
- alias cmd_fifo_out is cmd_fifo_dout(25 downto 24);
- alias addr_fifo_out is cmd_fifo_dout(23 downto 0);
-
-begin
-
- clk_fb <= part_clk_p after 1 ns;
-
- -- Instantiate synchronous FIFO
- inst_command_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => 8,
- data_width => 2+24
- )
- PORT MAP
- (
- rst => rst_out,
- clk => clk_out,
- we => cmd_fifo_we,
- re => cmd_fifo_re,
- fifo_full => cmd_fifo_full,
- fifo_empty => cmd_fifo_empty,
- fifo_afull => cmd_fifo_almost_full,
- fifo_aempty => cmd_fifo_almost_empty,
- data_w => cmd_fifo_din,
- data_r => cmd_fifo_dout
- );
-
- -- Instantiate synchronous FIFO
- inst_write_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => 8,
- data_width => 2*DDR_DATA_WIDTH
- )
- PORT MAP
- (
- rst => rst_out,
- clk => clk_out,
- we => write_fifo_we,
- re => write_fifo_re,
- fifo_full => write_fifo_full,
- fifo_empty => write_fifo_empty,
- fifo_afull => write_fifo_almost_full,
- fifo_aempty => write_fifo_almost_empty,
- data_w => write_fifo_din,
- data_r => write_fifo_dout
- );
-
- -- Instantiate synchronous FIFO
- inst_read_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => 8,
- data_width => 2*DDR_DATA_WIDTH
- )
- PORT MAP
- (
- rst => rst_out,
- clk => clk_out,
- we => read_fifo_we,
- re => read_fifo_re,
- fifo_full => read_fifo_full,
- fifo_empty => read_fifo_empty,
- fifo_afull => read_fifo_almost_full,
- fifo_aempty => read_fifo_almost_empty,
- data_w => read_fifo_din,
- data_r => read_fifo_dout
- );
-
- -- DDR SDRAM Controller Core
- inst_sdram_ctrl : entity work.sdram_ctrl_top
- Generic map
- (
- BL => BURST_LEN,
- read_phaseshift => 0,
- f_sysclk => 100E6
- )
- Port map
- (
-
- sys_rst_in => rst,
- sys_clk_in => clk,
-
- sys_rst_out => rst_out,
- sys_clk_out => clk_out,
- sys_clk_fb => clk_fb,
-
- -- User interface
- u_data_vld => u_data_vld,
- u_data_req_w => u_req_wr,
- u_data_req_r => u_req_rd,
- u_tag_in => u_tag_in,
- u_tag_rd => u_tag_rd,
- u_tag_wr => u_tag_wr,
- u_busy => u_busy,
- u_addr => u_addr,
- u_cmd => u_cmd,
- u_cmd_we => u_cmd_we,
- u_data_wr => u_data_w,
- u_data_rd => u_data_r,
- u_dm_wr_in => u_dm,
- u_dm_rd_in => u_dm_rd_in,
- u_dm_rd_out => u_dm_rd_out,
-
- -- SDRAM signals
- sd_clk_p => part_clk_p,
- sd_clk_n => part_clk_n,
- sd_cke => part_cke,
- sd_cs_n => part_cs_n,
- sd_cas_n => part_cas_n,
- sd_ras_n => part_ras_n,
- sd_we_n => part_we_n,
- sd_addr => part_addr,
- sd_ba => part_ba,
- sd_dm => part_dm,
- sd_dqs => part_dqs,
- sd_data => part_data
-
- );
-
- -- MICRON DDR SDRAM Simulation Model
- i_mt46v16m16_0 : entity work.mt46v16m16
- port map (
- dq => std_logic_vector(part_data),
- dqs => std_logic_vector(part_dqs),
- addr => std_logic_vector(part_addr),
- ba => std_logic_vector(part_ba),
- clk => part_clk_p,
- clk_n => part_clk_n,
- cke => part_cke,
- cs_n => part_cs_n,
- ras_n => part_ras_n,
- cas_n => part_cas_n,
- we_n => part_we_n,
- dm => std_logic_vector(part_dm)
- );
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- clk <= not clk;
- end process;
-
-------------------------------------------------------------------------------------------
- u_cmd_we <= (not cmd_fifo_empty) and write_start and (not u_busy);
- u_cmd <= cmd_fifo_out;
- u_addr <= addr_fifo_out;
-
- write_fifo_re <= u_req_wr and (not write_fifo_empty);
- cmd_fifo_re <= u_cmd_we;
- u_data_w <= write_fifo_dout;
- read_fifo_re <= (not read_fifo_empty) and read_start;
- read_fifo_we <= u_data_vld;
- read_fifo_din <= u_data_r;
-
- process
- begin
-
- -- Write MAX_WORDS to DDR SDRAM Controller
- wait for 4*CLK_PERIOD;
- rst <= '0';
-
- wait for 4*CLK_PERIOD;
- wait until rising_edge(clk_out) and rst_out='0';
-
-
write_fifo_we <= '1';
- cmd_fifo_we <= '1';
- write_fifo_din <= X"01020304";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000000";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"05060708";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000002";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"00001111";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000004";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"22223333";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000006";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"44445555";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000008";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"66667777";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"00000a";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"88889999";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"00000c";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"AAAABBBB";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"00000e";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"CCCCDDDD";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000010";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"EEEEFFFF";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000012";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '0';
- cmd_fifo_we <= '0';
-
--- wait until rising_edge(clk_out) and u_busy='0';
--- write_start <= '1';
--- wait until rising_edge(clk_out) and write_fifo_empty='1';
-
- write_fifo_we <= '1';
- cmd_fifo_we <= '1';
- write_fifo_din <= X"01234567";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000014";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '0';
- cmd_fifo_in <= UCMD_READ;
- addr_fifo_in <= X"000014";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"89ABCDEF";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000016";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"11223344";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000018";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '0';
- cmd_fifo_in <= UCMD_READ;
- addr_fifo_in <= X"000010";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"55667788";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"00001a";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"99990000";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"00001c";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '1';
- write_fifo_din <= X"AAAA5555";
- cmd_fifo_in <= UCMD_WRITE;
- addr_fifo_in <= X"000020";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '0';
- cmd_fifo_in <= UCMD_READ;
- addr_fifo_in <= X"000000";
-
- wait until rising_edge(clk_out);
- cmd_fifo_in <= UCMD_READ;
- addr_fifo_in <= X"000018";
-
- wait until rising_edge(clk_out);
- cmd_fifo_in <= UCMD_READ;
- addr_fifo_in <= X"00001A";
-
- wait until rising_edge(clk_out);
- cmd_fifo_in <= UCMD_READ;
- addr_fifo_in <= X"00001C";
-
- wait until rising_edge(clk_out);
- cmd_fifo_in <= UCMD_READ;
- addr_fifo_in <= X"000020";
-
- wait until rising_edge(clk_out);
- write_fifo_we <= '0';
- cmd_fifo_we <= '0';
-
- wait for 40*CLK_PERIOD;
- read_start <= '1';
- wait;
-
- end process;
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd
deleted file mode 100644
index 961b58e..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd
+++ /dev/null
@@ -1,322 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
- -- Number of user data words for simulation
- constant CLK_PERIOD : time := 10 ns;
- constant BURST_LEN : natural := 8;
-
- signal rst : std_logic := '1';
- signal clk : std_logic := '0';
- signal rst_out : std_logic;
- signal clk_out : std_logic;
- signal clk_fb : std_logic;
- signal part_clk_p : std_logic;
- signal part_clk_n : std_logic;
- signal part_cke : std_logic;
- signal part_cs_n : std_logic;
- signal part_we_n : std_logic;
- signal part_ras_n : std_logic;
- signal part_cas_n : std_logic;
- signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
- signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
- signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
- signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
- signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- signal u_addr : user_addr_t := (others => '0');
- signal lin_addr : user_addr_t := (others => '0');
- signal rand_gen : unsigned(7 downto 0) := (others => '0');
- signal u_tag_in : user_tag_t := "0000";
- signal u_tag_rd : user_tag_t;
- signal u_tag_wr : user_tag_t;
- signal u_cmd : user_cmd_t := UCMD_NOP;
- signal u_cmd_we : std_logic := '0';
- signal u_busy : std_logic;
- signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_data_vld : std_logic;
- signal u_req_wr : std_logic;
- signal u_req_rd : std_logic;
- signal u_read_en : std_logic := '0';
- signal u_write_en : std_logic := '0';
- signal rw_null_en : std_logic := '0';
- signal u_addr_cnt_en : std_logic := '0';
- signal u_addr_load : std_logic := '0';
- signal u_addr_preset : user_addr_t := (others => '0');
- signal u_addr_end : user_addr_t := (others => '0');
- signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
- signal test_phase : test_phase_t := IDLE;
-
- type u_addr_mode_t is (MONOTONIC, RANDOM);
- signal u_addr_mode : u_addr_mode_t := MONOTONIC;
- signal cycle_cnt : natural := 1;
- signal data_cnt : natural := 0;
- signal efficiency : real := 0.0;
-
-begin
-
- clk_fb <= part_clk_p after 1 ns;
-
- -- DDR SDRAM Controller Core
- inst_sdram_ctrl : entity work.sdram_ctrl_top
- Generic map
- (
- BL => BURST_LEN,
- read_phaseshift => 0,
- f_sysclk => 100E6
- )
- Port map
- (
-
- sys_rst_in => rst,
- sys_clk_in => clk,
-
- sys_rst_out => rst_out,
- sys_clk_out => clk_out,
- sys_clk_fb => clk_fb,
-
- -- User interface
- u_data_vld => u_data_vld,
- u_data_req_w => u_req_wr,
- u_data_req_r => u_req_rd,
- u_tag_in => u_tag_in,
- u_tag_rd => u_tag_rd,
- u_tag_wr => u_tag_wr,
- u_busy => u_busy,
- u_addr => u_addr,
- u_cmd => u_cmd,
- u_cmd_we => u_cmd_we,
- u_data_wr => u_data_w,
- u_data_rd => u_data_r,
- u_dm_wr_in => u_dm,
- u_dm_rd_in => u_dm_rd_in,
- u_dm_rd_out => u_dm_rd_out,
-
- -- SDRAM signals
- sd_clk_p => part_clk_p,
- sd_clk_n => part_clk_n,
- sd_cke => part_cke,
- sd_cs_n => part_cs_n,
- sd_cas_n => part_cas_n,
- sd_ras_n => part_ras_n,
- sd_we_n => part_we_n,
- sd_addr => part_addr,
- sd_ba => part_ba,
- sd_dm => part_dm,
- sd_dqs => part_dqs,
- sd_data => part_data
-
- );
-
- -- MICRON DDR SDRAM Simulation Model
- i_mt46v16m16_0 : entity work.mt46v16m16
- port map (
- dq => std_logic_vector(part_data),
- dqs => std_logic_vector(part_dqs),
- addr => std_logic_vector(part_addr),
- ba => std_logic_vector(part_ba),
- clk => part_clk_p,
- clk_n => part_clk_n,
- cke => part_cke,
- cs_n => part_cs_n,
- ras_n => part_ras_n,
- cas_n => part_cas_n,
- we_n => part_we_n,
- dm => std_logic_vector(part_dm)
- );
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- clk <= not clk;
- end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_data_vld='1' then
- if u_read_en = '1' and u_tag_rd = "0000" then
- assert (ref_data = u_data_r) report "Error on read!" severity failure;
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- end if;
- elsif u_read_en = '0' and rw_null_en = '0' then
- last_data := (others => '0');
- ref_data <= (others => '0');
- end if;
- end if;
- end process;
-
-W_DATA_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_req_wr = '1' and u_tag_wr = "0000" then
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- elsif u_write_en = '0' and rw_null_en = '0' then
- last_data := (others => '0');
- u_data_w <= (others => '0');
- end if;
- end if;
- end process;
-
-ADDR_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_addr_load = '1' then
- lin_addr <= u_addr_preset;
- rand_gen <= X"80";
- elsif u_addr_cnt_en = '1' then
- lin_addr <= lin_addr + BURST_LEN;
- if rand_gen(rand_gen'left) = '1' then
- rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010";
- else
- rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left);
- end if;
- end if;
- end if;
- end process;
-
-performance_count:
- process(clk_out)
- begin
- if rising_edge(clk_out) then
- if u_write_en = '1' or u_read_en = '1' then
- cycle_cnt <= cycle_cnt + 1;
- if u_req_wr = '1' or u_req_rd = '1' then
- data_cnt <= data_cnt + 1;
- end if;
- else
- cycle_cnt <= 1;
- data_cnt <= 0;
- end if;
- end if;
- end process;
-
- u_tag_in <= "000" & rw_null_en;
-
- efficiency <= real(data_cnt)/real(cycle_cnt);
- u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
- u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0';
- u_addr <= (rand_gen(7) and (not rw_null_en)) & lin_addr(lin_addr'left-1 downto 0);
- process
- begin
-
- -- Write MAX_WORDS to DDR SDRAM Controller
- wait for 4*CLK_PERIOD;
- rst <= '0';
-
- wait until rising_edge(clk_out) and u_busy='0';
- wait for 137*CLK_PERIOD;
-
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 0
- test_phase <= WRITE_MULTI;
- u_addr_preset <= X"000000";
- u_addr_end <= X"010000"-BURST_LEN;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_cmd <= UCMD_READ;
- u_write_en <= '1';
- rw_null_en <= '1';
- while lin_addr /= u_addr_end loop
- u_cmd <= UCMD_READ;
- rw_null_en <= '1';
- if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
- if rand_gen(1) = '1' or rand_gen(7) = '1' then
- u_cmd <= UCMD_WRITE;
- end if;
- rw_null_en <= '0';
- end if;
- wait until rising_edge(clk_out);
- end loop;
- u_write_en <= '0';
- rw_null_en <= '0';
- wait until rising_edge(clk_out) and u_req_wr='0';
- wait for 200*CLK_PERIOD;
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 0
- test_phase <= READ_MULTI;
- u_addr_preset <= X"000000";
- u_addr_end <= X"010000"-BURST_LEN;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_cmd <= UCMD_WRITE;
- u_read_en <= '1';
- rw_null_en <= '1';
- while lin_addr /= u_addr_end loop
- u_cmd <= UCMD_WRITE;
- rw_null_en <= '1';
- if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
- if rand_gen(1) = '1' or rand_gen(7) = '1' then
- u_cmd <= UCMD_READ;
- end if;
- rw_null_en <= '0';
- end if;
- wait until rising_edge(clk_out);
- end loop;
- u_read_en <= '0';
- rw_null_en <= '0';
- wait until rising_edge(clk_out) and u_data_vld='0';
-
- wait;
-
- end process;
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd
deleted file mode 100644
index 286fb33..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd
+++ /dev/null
@@ -1,320 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
- -- Number of user data words for simulation
- constant CLK_PERIOD : time := 10 ns;
- constant BURST_LEN : natural := 8;
-
- signal rst : std_logic := '1';
- signal clk : std_logic := '0';
- signal rst_out : std_logic;
- signal clk_out : std_logic;
- signal clk_fb : std_logic;
- signal part_clk_p : std_logic;
- signal part_clk_n : std_logic;
- signal part_cke : std_logic;
- signal part_cs_n : std_logic;
- signal part_we_n : std_logic;
- signal part_ras_n : std_logic;
- signal part_cas_n : std_logic;
- signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
- signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
- signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
- signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
- signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- signal u_addr : user_addr_t := (others => '0');
- signal lin_addr : user_addr_t := (others => '0');
- signal rand_gen : unsigned(7 downto 0) := (others => '0');
- signal u_tag_in : user_tag_t := "0000";
- signal u_tag_rd : user_tag_t;
- signal u_tag_wr : user_tag_t;
- signal u_cmd : user_cmd_t := UCMD_NOP;
- signal u_cmd_we : std_logic := '0';
- signal u_busy : std_logic;
- signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_data_vld : std_logic;
- signal u_req_wr : std_logic;
- signal u_req_rd : std_logic;
- signal u_read_en : std_logic := '0';
- signal u_write_en : std_logic := '0';
- signal rw_null_en : std_logic := '0';
- signal u_addr_cnt_en : std_logic := '0';
- signal u_addr_load : std_logic := '0';
- signal u_addr_preset : user_addr_t := (others => '0');
- signal u_addr_end : user_addr_t := (others => '0');
- signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
- signal test_phase : test_phase_t := IDLE;
-
- type u_addr_mode_t is (MONOTONIC, RANDOM);
- signal u_addr_mode : u_addr_mode_t := MONOTONIC;
- signal cycle_cnt : natural := 1;
- signal data_cnt : natural := 0;
- signal efficiency : real := 0.0;
-
-begin
-
- clk_fb <= part_clk_p after 1 ns;
-
- -- DDR SDRAM Controller Core
- inst_sdram_ctrl : entity work.sdram_ctrl_top
- Generic map
- (
- BL => BURST_LEN,
- read_phaseshift => 0,
- f_sysclk => 100E6
- )
- Port map
- (
-
- sys_rst_in => rst,
- sys_clk_in => clk,
-
- sys_rst_out => rst_out,
- sys_clk_out => clk_out,
- sys_clk_fb => clk_fb,
-
- -- User interface
- u_data_vld => u_data_vld,
- u_data_req_w => u_req_wr,
- u_data_req_r => u_req_rd,
- u_tag_in => u_tag_in,
- u_tag_rd => u_tag_rd,
- u_tag_wr => u_tag_wr,
- u_busy => u_busy,
- u_addr => u_addr,
- u_cmd => u_cmd,
- u_cmd_we => u_cmd_we,
- u_data_wr => u_data_w,
- u_data_rd => u_data_r,
- u_dm_wr_in => u_dm,
- u_dm_rd_in => u_dm_rd_in,
- u_dm_rd_out => u_dm_rd_out,
-
- -- SDRAM signals
- sd_clk_p => part_clk_p,
- sd_clk_n => part_clk_n,
- sd_cke => part_cke,
- sd_cs_n => part_cs_n,
- sd_cas_n => part_cas_n,
- sd_ras_n => part_ras_n,
- sd_we_n => part_we_n,
- sd_addr => part_addr,
- sd_ba => part_ba,
- sd_dm => part_dm,
- sd_dqs => part_dqs,
- sd_data => part_data
-
- );
-
- -- MICRON DDR SDRAM Simulation Model
- i_mt46v16m16_0 : entity work.mt46v16m16
- port map (
- dq => std_logic_vector(part_data),
- dqs => std_logic_vector(part_dqs),
- addr => std_logic_vector(part_addr),
- ba => std_logic_vector(part_ba),
- clk => part_clk_p,
- clk_n => part_clk_n,
- cke => part_cke,
- cs_n => part_cs_n,
- ras_n => part_ras_n,
- cas_n => part_cas_n,
- we_n => part_we_n,
- dm => std_logic_vector(part_dm)
- );
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- clk <= not clk;
- end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_data_vld='1' then
- if u_read_en = '1' and u_tag_rd = "0000" then
- assert (ref_data = u_data_r) report "Error on read!" severity failure;
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- end if;
- elsif u_read_en = '0' and rw_null_en = '0' then
- last_data := (others => '0');
- ref_data <= (others => '0');
- end if;
- end if;
- end process;
-
-W_DATA_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_req_wr = '1' and u_tag_wr = "0000" then
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- elsif u_write_en = '0' and rw_null_en = '0' then
- last_data := (others => '0');
- u_data_w <= (others => '0');
- end if;
- end if;
- end process;
-
-ADDR_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_addr_load = '1' then
- lin_addr <= u_addr_preset;
- rand_gen <= X"80";
- elsif u_addr_cnt_en = '1' then
- lin_addr <= lin_addr + BURST_LEN;
- if rand_gen(rand_gen'left) = '1' then
- rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010";
- else
- rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left);
- end if;
- end if;
- end if;
- end process;
-
-performance_count:
- process(clk_out)
- begin
- if rising_edge(clk_out) then
- if u_write_en = '1' or u_read_en = '1' then
- cycle_cnt <= cycle_cnt + 1;
- if u_req_wr = '1' or u_req_rd = '1' then
- data_cnt <= data_cnt + 1;
- end if;
- else
- cycle_cnt <= 1;
- data_cnt <= 0;
- end if;
- end if;
- end process;
-
- u_tag_in <= "000" & rw_null_en;
-
- efficiency <= real(data_cnt)/real(cycle_cnt);
- u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
- u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0';
- u_addr <= (rand_gen(7) and (rw_null_en)) & lin_addr(lin_addr'left-1 downto 0);
- process
- begin
-
- -- Write MAX_WORDS to DDR SDRAM Controller
- wait for 4*CLK_PERIOD;
- rst <= '0';
-
- wait until rising_edge(clk_out) and u_busy='0';
- wait for 137*CLK_PERIOD;
-
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 0
- test_phase <= WRITE_MULTI;
- u_addr_preset <= X"000000";
- u_addr_end <= X"010000"-BURST_LEN;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_cmd <= UCMD_WRITE;
- u_write_en <= '1';
- while lin_addr /= u_addr_end loop
- u_cmd <= UCMD_WRITE;
- rw_null_en <= '0';
- if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
- if rand_gen(1) = '1' or rand_gen(7) = '1' then
- u_cmd <= UCMD_READ;
- end if;
- rw_null_en <= '1';
- end if;
- wait until rising_edge(clk_out);
- end loop;
- u_write_en <= '0';
- rw_null_en <= '0';
- wait until rising_edge(clk_out) and u_req_wr='0';
- wait for 200*CLK_PERIOD;
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 0
- test_phase <= READ_MULTI;
- u_addr_preset <= X"000000";
- u_addr_end <= X"010000"-BURST_LEN;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_cmd <= UCMD_READ;
- u_read_en <= '1';
- while lin_addr /= u_addr_end loop
- u_cmd <= UCMD_READ;
- rw_null_en <= '0';
- if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
- if rand_gen(1) = '1' or rand_gen(7) = '1' then
- u_cmd <= UCMD_WRITE;
- end if;
- rw_null_en <= '1';
- end if;
- wait until rising_edge(clk_out);
- end loop;
- u_read_en <= '0';
- rw_null_en <= '0';
- wait until rising_edge(clk_out) and u_data_vld='0';
-
- wait;
-
- end process;
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd
deleted file mode 100644
index 5f96aa3..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd
+++ /dev/null
@@ -1,319 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
- -- Number of user data words for simulation
- constant CLK_PERIOD : time := 10 ns;
- constant BURST_LEN : natural := 8;
-
- signal rst : std_logic := '1';
- signal clk : std_logic := '0';
- signal rst_out : std_logic;
- signal clk_out : std_logic;
- signal clk_fb : std_logic;
- signal part_clk_p : std_logic;
- signal part_clk_n : std_logic;
- signal part_cke : std_logic;
- signal part_cs_n : std_logic;
- signal part_we_n : std_logic;
- signal part_ras_n : std_logic;
- signal part_cas_n : std_logic;
- signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
- signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
- signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
- signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
- signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- signal u_addr : user_addr_t := (others => '0');
- signal u_tag_in : user_tag_t := "0000";
- signal u_tag_rd : user_tag_t;
- signal u_tag_wr : user_tag_t;
- signal u_cmd : user_cmd_t := UCMD_NOP;
- signal u_cmd_we : std_logic := '0';
- signal u_busy : std_logic;
- signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_data_vld : std_logic;
- signal u_req_wr : std_logic;
- signal u_req_rd : std_logic;
- signal u_read_en : std_logic := '0';
- signal u_write_en : std_logic := '0';
- signal u_addr_cnt_en : std_logic := '0';
- signal u_addr_load : std_logic := '0';
- signal u_addr_preset : user_addr_t := (others => '0');
- signal u_addr_end : user_addr_t := (others => '0');
- signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
- signal test_phase : test_phase_t := IDLE;
-
- type u_addr_mode_t is (MONOTONIC, RANDOM);
- signal u_addr_mode : u_addr_mode_t := MONOTONIC;
- signal cycle_cnt : natural := 1;
- signal data_cnt : natural := 0;
- signal efficiency : real := 0.0;
-
-begin
-
- clk_fb <= part_clk_p after 1 ns;
-
- -- DDR SDRAM Controller Core
- inst_sdram_ctrl : entity work.sdram_ctrl_top
- Generic map
- (
- BL => BURST_LEN,
- read_phaseshift => 0,
- f_sysclk => 100E6
- )
- Port map
- (
-
- sys_rst_in => rst,
- sys_clk_in => clk,
-
- sys_rst_out => rst_out,
- sys_clk_out => clk_out,
- sys_clk_fb => clk_fb,
-
- -- User interface
- u_data_vld => u_data_vld,
- u_data_req_w => u_req_wr,
- u_data_req_r => u_req_rd,
- u_tag_in => u_tag_in,
- u_tag_rd => u_tag_rd,
- u_tag_wr => u_tag_wr,
- u_busy => u_busy,
- u_addr => u_addr,
- u_cmd => u_cmd,
- u_cmd_we => u_cmd_we,
- u_data_wr => u_data_w,
- u_data_rd => u_data_r,
- u_dm_wr_in => u_dm,
- u_dm_rd_in => u_dm_rd_in,
- u_dm_rd_out => u_dm_rd_out,
-
- -- SDRAM signals
- sd_clk_p => part_clk_p,
- sd_clk_n => part_clk_n,
- sd_cke => part_cke,
- sd_cs_n => part_cs_n,
- sd_cas_n => part_cas_n,
- sd_ras_n => part_ras_n,
- sd_we_n => part_we_n,
- sd_addr => part_addr,
- sd_ba => part_ba,
- sd_dm => part_dm,
- sd_dqs => part_dqs,
- sd_data => part_data
-
- );
-
- -- MICRON DDR SDRAM Simulation Model
- i_mt46v16m16_0 : entity work.mt46v16m16
- port map (
- dq => std_logic_vector(part_data),
- dqs => std_logic_vector(part_dqs),
- addr => std_logic_vector(part_addr),
- ba => std_logic_vector(part_ba),
- clk => part_clk_p,
- clk_n => part_clk_n,
- cke => part_cke,
- cs_n => part_cs_n,
- ras_n => part_ras_n,
- cas_n => part_cas_n,
- we_n => part_we_n,
- dm => std_logic_vector(part_dm)
- );
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- clk <= not clk;
- end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_data_vld='1' then
- if u_read_en = '1' then
- assert (ref_data = u_data_r) report "Error on read!" severity failure;
- end if;
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- elsif u_read_en = '0' then
- last_data := (others => '0');
- ref_data <= (others => '0');
- end if;
- end if;
- end process;
-
-W_DATA_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_req_wr = '1' then
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- elsif u_write_en = '0' then
- last_data := (others => '0');
- u_data_w <= (others => '0');
- end if;
- end if;
- end process;
-
-ADDR_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_addr_load = '1' then
- u_addr <= u_addr_preset;
- elsif u_addr_cnt_en = '1' then
- if u_addr_mode = MONOTONIC then
- u_addr <= u_addr + BURST_LEN;
- else
- if u_addr(u_addr'left) = '1' then
- if BURST_LEN = 2 then
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
- elsif BURST_LEN = 4 then
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
- elsif BURST_LEN = 8 then
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
- end if;
- else
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
- end if;
- end if;
- end if;
- end if;
- end process;
-
-performance_count:
- process(clk_out)
- begin
- if rising_edge(clk_out) then
- if u_write_en = '1' or u_read_en = '1' then
- cycle_cnt <= cycle_cnt + 1;
- if u_req_wr = '1' or u_req_rd = '1' then
- data_cnt <= data_cnt + 1;
- end if;
- else
- cycle_cnt <= 1;
- data_cnt <= 0;
- end if;
- end if;
- end process;
-
- u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
-
- efficiency <= real(data_cnt)/real(cycle_cnt);
- u_cmd_we <= (u_write_en or u_read_en) and (not u_busy);
- u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
-
- process
- begin
-
- -- Write MAX_WORDS to DDR SDRAM Controller
- wait for 4*CLK_PERIOD;
- rst <= '0';
-
- wait until rising_edge(clk_out) and u_busy='0';
- wait for 137*CLK_PERIOD;
-
-
wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 0
- test_phase <= WRITE_MULTI;
- u_addr_preset <= X"800000";
- if BURST_LEN = 2 then
- u_addr_end <= X"5E2330";
- elsif BURST_LEN = 4 then
- u_addr_end <= X"7DEDD0";
- elsif BURST_LEN = 8 then
- u_addr_end <= X"5666B0";
- end if;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_addr_mode <= RANDOM;
- u_cmd <= UCMD_WRITE;
- u_write_en <= '1';
- while u_addr /= u_addr_end loop
- wait until rising_edge(clk_out);
- end loop;
- u_write_en <= '0';
- wait until rising_edge(clk_out) and u_req_wr='0';
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 0
- test_phase <= READ_MULTI;
- u_addr_preset <= X"800000";
- if BURST_LEN = 2 then
- u_addr_end <= X"5E2330";
- elsif BURST_LEN = 4 then
- u_addr_end <= X"7DEDD0";
- elsif BURST_LEN = 8 then
- u_addr_end <= X"5666B0";
- end if;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_addr_mode <= RANDOM;
- u_cmd <= UCMD_READ;
- u_read_en <= '1';
- while u_addr /= u_addr_end loop
- wait until rising_edge(clk_out);
- end loop;
- u_read_en <= '0';
- wait until rising_edge(clk_out) and u_data_vld='0';
-
- wait;
-
- end process;
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd
deleted file mode 100644
index c60d600..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd
+++ /dev/null
@@ -1,333 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
- -- Number of user data words for simulation
- constant CLK_PERIOD : time := 10 ns;
- constant BURST_LEN : natural := 2;
-
- signal rst : std_logic := '1';
- signal clk : std_logic := '0';
- signal rst_out : std_logic;
- signal clk_out : std_logic;
- signal clk_fb : std_logic;
- signal part_clk_p : std_logic;
- signal part_clk_n : std_logic;
- signal part_cke : std_logic;
- signal part_cs_n : std_logic;
- signal part_we_n : std_logic;
- signal part_ras_n : std_logic;
- signal part_cas_n : std_logic;
- signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
- signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
- signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
- signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
- signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- signal u_addr : user_addr_t := (others => '0');
- signal u_tag_in : user_tag_t := "0000";
- signal u_tag_rd : user_tag_t;
- signal u_tag_wr : user_tag_t;
- signal u_cmd : user_cmd_t := UCMD_NOP;
- signal u_cmd_we : std_logic := '0';
- signal u_busy : std_logic;
- signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
- signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal u_data_vld : std_logic;
- signal u_req_wr : std_logic;
- signal u_req_rd : std_logic;
- signal u_read_en : std_logic := '0';
- signal u_write_en : std_logic := '0';
- signal rw_null_en : std_logic := '0';
- signal u_addr_cnt_en : std_logic := '0';
- signal u_addr_load : std_logic := '0';
- signal u_addr_preset : user_addr_t := (others => '0');
- signal u_addr_end : user_addr_t := (others => '0');
- signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
- signal test_phase : test_phase_t := IDLE;
-
- type u_addr_mode_t is (MONOTONIC, RANDOM);
- signal u_addr_mode : u_addr_mode_t := MONOTONIC;
- signal cycle_cnt : natural := 1;
- signal data_cnt : natural := 0;
- signal efficiency : real := 0.0;
-
-begin
-
- clk_fb <= part_clk_p after 1 ns;
-
- -- DDR SDRAM Controller Core
- inst_sdram_ctrl : entity work.sdram_ctrl_top
- Generic map
- (
- BL => BURST_LEN,
- read_phaseshift => 0,
- f_sysclk => 100E6
- )
- Port map
- (
-
- sys_rst_in => rst,
- sys_clk_in => clk,
-
- sys_rst_out => rst_out,
- sys_clk_out => clk_out,
- sys_clk_fb => clk_fb,
-
- -- User interface
- u_data_vld => u_data_vld,
- u_data_req_w => u_req_wr,
- u_data_req_r => u_req_rd,
- u_tag_in => u_tag_in,
- u_tag_rd => u_tag_rd,
- u_tag_wr => u_tag_wr,
- u_busy => u_busy,
- u_addr => u_addr,
- u_cmd => u_cmd,
- u_cmd_we => u_cmd_we,
- u_data_wr => u_data_w,
- u_data_rd => u_data_r,
- u_dm_wr_in => u_dm,
- u_dm_rd_in => u_dm_rd_in,
- u_dm_rd_out => u_dm_rd_out,
-
- -- SDRAM signals
- sd_clk_p => part_clk_p,
- sd_clk_n => part_clk_n,
- sd_cke => part_cke,
- sd_cs_n => part_cs_n,
- sd_cas_n => part_cas_n,
- sd_ras_n => part_ras_n,
- sd_we_n => part_we_n,
- sd_addr => part_addr,
- sd_ba => part_ba,
- sd_dm => part_dm,
- sd_dqs => part_dqs,
- sd_data => part_data
-
- );
-
- -- MICRON DDR SDRAM Simulation Model
- i_mt46v16m16_0 : entity work.mt46v16m16
- port map (
- dq => std_logic_vector(part_data),
- dqs => std_logic_vector(part_dqs),
- addr => std_logic_vector(part_addr),
- ba => std_logic_vector(part_ba),
- clk => part_clk_p,
- clk_n => part_clk_n,
- cke => part_cke,
- cs_n => part_cs_n,
- ras_n => part_ras_n,
- cas_n => part_cas_n,
- we_n => part_we_n,
- dm => std_logic_vector(part_dm)
- );
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- clk <= not clk;
- end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_data_vld='1' then
- if u_read_en = '1' then
- assert (ref_data = u_data_r) report "Error on read!" severity failure;
- end if;
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- elsif u_read_en = '0' and rw_null_en = '0' then
- last_data := (others => '0');
- ref_data <= (others => '0');
- end if;
- end if;
- end process;
-
-W_DATA_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_req_wr = '1' then
- for i in 0 to DDR_DATA_WIDTH/4-1 loop
- u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
- end loop;
- last_data := last_data + DDR_DATA_WIDTH/4;
- elsif u_write_en = '0' and rw_null_en = '0' then
- last_data := (others => '0');
- u_data_w <= (others => '0');
- end if;
- end if;
- end process;
-
-ADDR_GEN:
- process(clk_out)
- variable last_data : unsigned(7 downto 0) := (others => '0');
- begin
- if rising_edge(clk_out) then
- if u_addr_load = '1' then
- u_addr <= u_addr_preset;
- elsif u_addr_cnt_en = '1' then
- if u_addr_mode = MONOTONIC then
- u_addr <= u_addr + BURST_LEN;
- else
- if u_addr(u_addr'left) = '1' then
- if BURST_LEN = 2 then
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
- elsif BURST_LEN = 4 then
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
- elsif BURST_LEN = 8 then
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
- end if;
- else
- u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
- end if;
- end if;
- end if;
- end if;
- end process;
-
-performance_count:
- process(clk_out)
- begin
- if rising_edge(clk_out) then
- if u_write_en = '1' or u_read_en = '1' then
- cycle_cnt <= cycle_cnt + 1;
- if u_req_wr = '1' or u_req_rd = '1' then
- data_cnt <= data_cnt + 1;
- end if;
- else
- cycle_cnt <= 1;
- data_cnt <= 0;
- end if;
- end if;
- end process;
-
- u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
-
- efficiency <= real(data_cnt)/real(cycle_cnt);
- u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
- u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
-
- process
- begin
-
- -- Write MAX_WORDS to DDR SDRAM Controller
- wait for 4*CLK_PERIOD;
- rst <= '0';
-
- wait until rising_edge(clk_out) and u_busy='0';
- wait for 137*CLK_PERIOD;
-
- -- Bank 0
- test_phase <= WRITE_MULTI;
- u_addr_preset <= X"800000";
- if BURST_LEN = 2 then
- u_addr_end <= X"646808";
- elsif BURST_LEN = 4 then
- u_addr_end <= X"7DEDD0";
- elsif BURST_LEN = 8 then
- u_addr_end <= X"5666B0";
- end if;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_addr_mode <= RANDOM;
- while u_addr /= u_addr_end loop
- u_cmd <= UCMD_WRITE;
- u_write_en <= '1';
- rw_null_en <= '0';
- if u_addr(20) = '0' then
- u_cmd <= UCMD_READ;
- u_write_en <= '0';
- rw_null_en <= '1';
- end if;
- wait until rising_edge(clk_out);
- end loop;
- u_write_en <= '0';
- rw_null_en <= '0';
- wait for 200*CLK_PERIOD;
-
- wait until rising_edge(clk_out) and u_busy='0';
- -- Bank 0
- test_phase <= READ_MULTI;
- u_addr_preset <= X"800000";
- if BURST_LEN = 2 then
- u_addr_end <= X"646808";
- elsif BURST_LEN = 4 then
- u_addr_end <= X"7DEDD0";
- elsif BURST_LEN = 8 then
- u_addr_end <= X"5666B0";
- end if;
- u_addr_load <= '1';
- wait until rising_edge(clk_out);
- u_addr_load <= '0';
- wait until rising_edge(clk_out);
- u_addr_mode <= RANDOM;
- while u_addr /= u_addr_end loop
- u_cmd <= UCMD_READ;
- u_read_en <= '1';
- rw_null_en <= '0';
- if u_addr(20) = '0' then
- u_cmd <= UCMD_WRITE;
- u_read_en <= '0';
- rw_null_en <= '1';
- end if;
- wait until rising_edge(clk_out);
- end loop;
- u_read_en <= '0';
- rw_null_en <= '0';
- wait until rising_edge(clk_out) and u_data_vld='0';
-
- wait;
-
- end process;
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd
deleted file mode 100644
index 95ffa58..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd
+++ /dev/null
@@ -1,385 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity tb_sdram_ctrl_frontend is
-end;
-
-architecture struct of tb_sdram_ctrl_frontend is
-
- -- Number of user data words for simulation
- constant CLK_PERIOD : time := 10 ns;
- constant BURST_LEN : natural := 2;
-
- signal rst : std_logic := '1';
- signal clk : std_logic := '0';
- signal rst_out : std_logic;
- signal clk_out : std_logic;
- signal clk_fb : std_logic;
- signal part_clk_p : std_logic;
- signal part_clk_n : std_logic;
- signal part_cke : std_logic;
- signal part_cs_n : std_logic;
- signal part_we_n : std_logic;
- signal part_ras_n : std_logic;
- signal part_cas_n : std_logic;
- signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
- signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
- signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
- signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
- signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
- signal addr : user_addr_t := (others => '0');
- signal r_wn : std_logic := '0';
- signal en : std_logic := '0';
- signal busy : std_logic;
- signal din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal be : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "1111";
- signal dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
- signal dout_vld : std_logic;
- signal dout_re : std_logic;
- signal dout_reg : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-begin
-
- clk_fb <= part_clk_p after 1 ns;
-
- -- DDR SDRAM Controller Core
- inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend
- Generic map
- (
- BL => BURST_LEN,
- read_phaseshift => 0,
- f_sysclk => 100E6,
- fifo_depth => 4
- )
- Port map
- (
-
- sys_rst_in => rst,
- sys_clk_in => clk,
-
- sys_rst_out => rst_out,
- sys_clk_out => clk_out,
- sys_clk_fb => clk_fb,
-
- busy => busy,
- en => en,
- r_wn => r_wn,
- be => be,
- addr => addr,
- din => din,
- dout => dout,
- dout_re => dout_re,
- dout_vld => dout_vld,
-
- -- SDRAM signals
- sd_clk_p => part_clk_p,
- sd_clk_n => part_clk_n,
- sd_cke => part_cke,
- sd_cs_n => part_cs_n,
- sd_cas_n => part_cas_n,
- sd_ras_n => part_ras_n,
- sd_we_n => part_we_n,
- sd_addr => part_addr,
- sd_ba => part_ba,
- sd_dm => part_dm,
- sd_dqs => part_dqs,
- sd_data => part_data
-
- );
-
- -- MICRON DDR SDRAM Simulation Model
- i_mt46v16m16_0 : entity work.mt46v16m16
- port map (
- dq => std_logic_vector(part_data),
- dqs => std_logic_vector(part_dqs),
- addr => std_logic_vector(part_addr),
- ba => std_logic_vector(part_ba),
- clk => part_clk_p,
- clk_n => part_clk_n,
- cke => part_cke,
- cs_n => part_cs_n,
- ras_n => part_ras_n,
- cas_n => part_cas_n,
- we_n => part_we_n,
- dm => std_logic_vector(part_dm)
- );
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- clk <= not clk;
- end process;
-
-read_register:
- process(clk_out)
- begin
- if rising_edge(clk_out) then
- if dout_vld = '1' then
- dout_reg <= dout;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------------------
- dout_re <= dout_vld;
-
- process
- begin
-
- -- Write MAX_WORDS to DDR SDRAM Controller
- wait for 4*CLK_PERIOD;
- rst <= '0';
-
- wait for 4*CLK_PERIOD;
- wait until rising_edge(clk_out) and rst_out='0';
-
- for i in 0 to 999 loop
-
en <= '1';
- r_wn <= '0';
- din <= to_unsigned(i, 32);
- addr <= to_unsigned(2*i, 24);
- wait until rising_edge(clk_out) and busy = '0';
- end loop;
-
- for i in 0 to 999 loop
- en <= '1';
- r_wn <= '1';
- din <= to_unsigned(i, 32);
- addr <= to_unsigned(2*i, 24);
- wait until rising_edge(clk_out) and busy = '0';
- end loop;
-
- en <= '1';
- r_wn <= '0';
- din <= X"01020304";
- addr <= X"000000";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"05060708";
- addr <= X"000002";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"00001111";
- addr <= X"000004";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"22223333";
- addr <= X"000006";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"44445555";
- addr <= X"000008";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"66667777";
- addr <= X"00000a";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"88889999";
- addr <= X"00000c";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"AAAABBBB";
- addr <= X"00000e";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"CCCCDDDD";
- addr <= X"000010";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"EEEEFFFF";
- addr <= X"000012";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"FFFFFFFF";
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '1';
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"87CCCCCC";
- be <= "1000";
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '1';
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"CC65CCCC";
- be <= "0100";
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '1';
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"CCCC43CC";
- be <= "0010";
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '1';
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"89ABCDEF";
- addr <= X"000016";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"CCCCCC21";
- be <= "0001";
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '1';
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"55555555";
- be <= "1010";
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '1';
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"AAAAAAAA";
- be <= "0101";
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '1';
- addr <= X"000014";
-
- wait until rising_edge(clk_out) and busy = '0';
- be <= "1111";
- en <= '1';
- r_wn <= '0';
- din <= X"11223344";
- addr <= X"000018";
-
- wait until rising_edge(clk_out) and busy = '0';
- r_wn <= '1';
- addr <= X"000010";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"55667788";
- addr <= X"00001a";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"99990000";
- addr <= X"00001c";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '1';
- r_wn <= '0';
- din <= X"AAAA5555";
- addr <= X"000020";
-
- wait until rising_edge(clk_out) and busy = '0';
- r_wn <= '1';
- addr <= X"000000";
-
- wait until rising_edge(clk_out) and busy = '0';
- r_wn <= '1';
- addr <= X"000018";
-
- wait until rising_edge(clk_out) and busy = '0';
- r_wn <= '1';
- addr <= X"00001A";
-
- wait until rising_edge(clk_out) and busy = '0';
- r_wn <= '1';
- addr <= X"00001C";
-
- wait until rising_edge(clk_out) and busy = '0';
- r_wn <= '1';
- addr <= X"000020";
-
- wait until rising_edge(clk_out) and busy = '0';
- en <= '0';
-
- wait;
-
- end process;
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo
index 584e104..5cab31c 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo
+++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo
@@ -13,6 +13,7 @@ vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd"
vcom -explicit -93 "../src/sdram_config.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
vcom -explicit -93 "../src/sdram_cmd.vhd"
vcom -explicit -93 "../src/sdram_ctrl.vhd"
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo
index f576e65..eda0016 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo
+++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo
@@ -14,7 +14,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_fb
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk0_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk270_o
@@ -38,7 +37,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {38990166 ps} 0}
+WaveRestoreCursors {{Cursor 1} {76048900 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -52,4 +51,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
-WaveRestoreZoom {38975716 ps} {39081070 ps}
+WaveRestoreZoom {0 ps} {210 us}
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo
index 976aebf..522c355 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo
+++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo
@@ -13,6 +13,7 @@ vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd"
vcom -explicit -93 "../src/sdram_config.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
vcom -explicit -93 "../src/sdram_cmd.vhd"
vcom -explicit -93 "../src/sdram_ctrl.vhd"
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo
index 20af0f9..ff17b67 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo
+++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo
@@ -21,10 +21,6 @@ add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_we
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_full
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_empty
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270var_o
add wave -noupdate -divider Part
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n
@@ -45,7 +41,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {199582900 ps} 0}
+WaveRestoreCursors {{Cursor 1} {52445000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -59,4 +55,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
-WaveRestoreZoom {199427964 ps} {200030108 ps}
+WaveRestoreZoom {52319857 ps} {52922001 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd
similarity index 100%
rename from lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd
rename to lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
index ae38d48..d3d11ce 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
@@ -29,13 +29,8 @@ use work.sdram_config.all;
use work.sdram_types.all;
entity sdram_cmd is
- Generic
- (
- f_sdrclk : real := 100.0;
- BL : natural := 2
- );
- Port
- (
+ Generic (BL : natural := 2);
+ Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
@@ -57,7 +52,7 @@ architecture behaviour of sdram_cmd is
signal st_sdr, st_sdr_next : sdr_state_t;
- signal cc_preset : natural range 0 to 15;
+ signal cc_preset : natural range 0 to 10;
signal cc_load_en : std_logic;
signal cycle_finished : std_logic;
@@ -65,23 +60,6 @@ architecture behaviour of sdram_cmd is
signal burst_load_en : std_logic;
signal burst_finished : std_logic;
- subtype cycle_cnt_t is natural range 0 to 15;
-
- type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
- constant TIMING : part_timing_array_t :=
- -- command cycle_cnt
- ( SD_DESELECT => (0 ),
- SD_NOP => (0 ),
- SD_LMR => (TMRD-1 ),
- SD_ACT => (to_cycles(TRCD, f_sdrclk)-1),
- SD_READ => (TCAS-1 ),
- SD_WRITE => (to_cycles(TWR, f_sdrclk)-1),
- SD_PRE => (to_cycles(TRP, f_sdrclk)-1),
- SD_BST => (0 ),
- SD_AR => (to_cycles(TRFC, f_sdrclk)-1),
- SD_SR => (to_cycles(TRFC, f_sdrclk)-1)
- );
-
begin
u_tag_out <= u_tag_in;
@@ -249,7 +227,7 @@ fsm_sdr_state_next:
------------------------------------------------------------------------------------------
cycle_counter:
process (rst, clk)
- variable cycle_cnt : natural range 0 to 15;
+ variable cycle_cnt : natural range 0 to 10;
begin
if rst = '1' then
cycle_cnt := 0;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
index 534232b..b0a6253 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
@@ -54,18 +54,18 @@ package sdram_config is
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
- constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
+ constant REFRESH_INTERVAL : real := 7.8125; -- us
-- These values are for your SDRAM part (see datasheet)
- constant TCAS : positive := 2; -- CAS latency [clocks]
- constant TRP : real := 20.0; -- precharge command period [ns]
- constant TRAS : real := 45.0; -- active to precharge delay [ns]
- constant TRFC : real := 75.0; -- auto refresh command period [ns]
- constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
- constant TRCD : real := 20.0; -- active to read or write delay [ns]
- constant TWR : real := 15.0; -- write recovery time [ns]
+ constant TCAS : positive := 2; -- CAS latency [clocks]
+ constant TRP : positive := 2; -- precharge command period
+ constant TRAS : positive := 4; -- active to precharge delay
+ constant TRFC : positive := 8; -- auto refresh command period
+ constant TMRD : positive := 2; -- load mode register command cylce time
+ constant TRCD : positive := 2; -- active to read or write delay !
+ constant TWR : positive := 2; -- write recovery time
- constant PWR_UP_WAIT : real := 1.0E3; -- [ns]
+ constant PWR_UP_WAIT : natural := 1; -- µs
subtype user_tag_t is unsigned(3 downto 0);
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
index d812b1c..42ad1c9 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
@@ -32,8 +32,8 @@ use work.utils_pkg.all;
entity sdram_ctrl is
Generic
(
- f_sysclk : real := 100.0;
- BL : natural := 2
+ f_sysclk : natural := 100E6;
+ BL : natural := 2
);
Port (
rst : in STD_LOGIC;
@@ -60,7 +60,7 @@ architecture behaviour of sdram_ctrl is
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t;
- constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk);
+ constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
signal pwr_up_cnt_rst : std_logic;
signal pwr_up_finished : std_logic;
@@ -74,7 +74,7 @@ architecture behaviour of sdram_ctrl is
signal seq_rst_en : std_logic;
signal seq_cnt_en : std_logic;
- constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk);
+ constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
signal refresh_request : std_logic;
signal refresh_cnt_rst : std_logic;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
index 5d997c3..936b508 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
@@ -32,10 +32,9 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend64_wb is
Generic
(
- BL : natural := 2;
- f_sysclk : real := 100.0;
- f_sdrclk : real := 100.0;
- fifo_depth : integer := 4
+ BL : natural := 2;
+ f_sysclk : natural := 100E6;
+ fifo_depth : integer := 4
);
Port
(
@@ -206,7 +205,6 @@ begin
(
BL => BL,
f_sysclk => f_sysclk,
- f_sdrclk => f_sdrclk,
fifo_depth => fifo_depth
)
Port map
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
index 57002b9..6d293d7 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
@@ -32,9 +32,8 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend_wb is
Generic
(
- BL : natural := 2;
- f_sysclk : real := 100.0;
- f_sdrclk : real := 100.0;
+ BL : natural := 2;
+ f_sysclk : natural := 100E6;
fifo_depth : integer := 4
);
Port
@@ -206,7 +205,6 @@ begin
(
BL => BL,
f_sysclk => f_sysclk,
- f_sdrclk => f_sdrclk,
fifo_depth => fifo_depth
)
Port map
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
index 8d4a9a4..bbca07d 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
@@ -31,9 +31,8 @@ use work.sdram_types.all;
entity sdram_ctrl_top is
Generic
(
- BL : natural := 2;
- f_sysclk : real := 100.0;
- f_sdrclk : real := 100.0;
+ BL : natural := 2;
+ f_sysclk : natural := 100E6;
fifo_depth : natural := 3
);
Port
@@ -92,6 +91,7 @@ architecture rtl of sdram_ctrl_top is
-- Clock generator
+ signal ctrl_rst : std_logic;
signal part_ctrl : part_ctrl_t;
-- SD command FIFO
@@ -128,17 +128,24 @@ begin
sd_cmd <= sdr_cmd_t(to_integer(sd_cmd_fifo_out));
---------------------------------
-
+ inst_reset: entity work.reset
+ port map
+ (
+ clk => sys_clk_in,
+ rst_in => sys_rst_in,
+ rst_out => ctrl_rst
+ );
+
-- Main controller
inst_sdram_ctrl : entity work.sdram_ctrl
Generic map
(
- f_sysclk => f_sysclk,
- BL => BL
+ f_sysclk => 100E6,
+ BL => BL
)
Port map
(
- rst => sys_rst_in,
+ rst => ctrl_rst,
clk => sys_clk_in,
u_busy => u_busy,
u_tag_in => u_tag_in,
@@ -163,7 +170,7 @@ begin
)
PORT MAP
(
- rst => sys_rst_in,
+ rst => ctrl_rst,
clk_w => sys_clk_in,
clk_r => sdram_clk0_in,
we => cmd_fifo_we,
@@ -180,12 +187,11 @@ begin
inst_sdram_cmd : entity work.sdram_cmd
Generic map
(
- f_sdrclk => f_sdrclk,
BL => BL
)
Port map
(
- rst => sys_rst_in,
+ rst => ctrl_rst,
clk => sdram_clk0_in,
u_tag_in => sd_tag_fifo_out,
u_tag_out => u_tag,
@@ -205,7 +211,7 @@ begin
inst_ddr_phy : entity work.ddr_phy
Port map
(
- sys_rst => sys_rst_in,
+ sys_rst => ctrl_rst,
sys_clk0 => sdram_clk0_in,
sys_clk270 => sdram_clk270_in,
u_tag_in => u_tag,
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
index 5520b28..d235d75 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
@@ -24,7 +24,6 @@
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-USE IEEE.MATH_REAL.ALL;
use work.sdram_config.all;
@@ -68,6 +67,8 @@ package sdram_types is
subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
subtype col_addr_t is unsigned(8 downto 0);
+ subtype cycle_cnt_t is natural range 0 to 10;
+
type phy_ctrl_t is
record
drive_en : std_logic;
@@ -107,6 +108,21 @@ package sdram_types is
SD_SR => ( '0', '0', '0', '1')
);
+ type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
+ constant TIMING : part_timing_array_t :=
+ -- command cycle_cnt
+ ( SD_DESELECT => ( 0 ),
+ SD_NOP => ( 0 ),
+ SD_LMR => ( TMRD-1 ),
+ SD_ACT => ( TRCD-1 ),
+ SD_READ => ( TCAS-1 ),
+ SD_WRITE => ( TWR-1 ),
+ SD_PRE => ( TRP-1 ),
+ SD_BST => ( 0 ),
+ SD_AR => ( TRFC-1 ),
+ SD_SR => ( TRFC-1 )
+ );
+
type init_seq_t is
record
cmd : sdr_cmd_t;
@@ -114,17 +130,4 @@ package sdram_types is
wait_cycle : natural;
end record init_seq_t;
- function to_cycles(T_ns : real; f_Mhz : real) return natural;
-
-end sdram_types;
-
-package body sdram_types is
-
- function to_cycles(T_ns : real; f_Mhz : real) return natural is
- begin
-
- return natural(ceil(1.0E-3*T_ns*f_Mhz));
-
- end to_cycles;
-
end sdram_types;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
index fdfd07d..1de777d 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
@@ -36,7 +36,7 @@ architecture struct of tb_sdram_ctrl_frontend64_wb is
-- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns;
- constant SDCLK_PERIOD : time := 7.5 ns;
+ constant SDCLK_PERIOD : time := 8 ns;
constant BURST_LEN : natural := 2;
signal rst : std_logic := '1';
@@ -122,7 +122,7 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
- clk_in_freq => 100.0,
+ clk_in_freq_hz => 100E6,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
@@ -151,8 +151,7 @@ inst_clockgen : entity work.clockgen
GENERIC MAP
(
BL => BURST_LEN,
- f_sysclk => 100.000,
- f_sdrclk => 133.333,
+ f_sysclk => 100E6,
fifo_depth => 4
)
PORT MAP
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
index 9673d37..2a9d9bf 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
@@ -119,7 +119,7 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
- clk_in_freq => 100.0,
+ clk_in_freq_hz => 100E6,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
@@ -146,8 +146,7 @@ inst_clockgen : entity work.clockgen
GENERIC MAP
(
BL => BURST_LEN,
- f_sysclk => 100.0,
- f_sdrclk => 100.0,
+ f_sysclk => 100E6,
fifo_depth => 4
)
PORT MAP
diff --git a/lib/SSRAM/sim/ModelSim SE .lnk b/lib/SSRAM/sim/ModelSim SE .lnk
deleted file mode 100644
index 935209c..0000000
Binary files a/lib/SSRAM/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo
deleted file mode 100644
index 9aafbb0..0000000
--- a/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-## NOTE: Do not edit this file.
-##
-vlib work
-
-# Top and TB
-vcom -explicit -93 "../src/package_utility.vhd"
-vcom -explicit -93 "../src/CY7C1354B.vhd"
-vcom -explicit -93 "../src/ssram_frontend_wb.vhd"
-vcom -explicit -93 "../src/tb_ssram_frontend_wb.vhd"
-
-vsim -t 1ps -lib work tb_ssram_frontend_wb
-do {tb_ssram_frontend_wb.wdo}
-view wave
-view structure
-view signals
-run 6us
-
\ No newline at end of file
diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo
deleted file mode 100644
index 71718ed..0000000
--- a/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo
+++ /dev/null
@@ -1,47 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/clk_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/rst_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/cyc_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/stb_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/we_o
-add wave -noupdate -format Literal /tb_ssram_frontend_wb/sel_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ack_i
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/mrdy_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_d
-add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_dp
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_a
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_cke_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_adv
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_mode
-add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_bw_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_we_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_oe_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_ce_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_zz
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dout_reg
-add wave -noupdate -format Literal -radix unsigned /tb_ssram_frontend_wb/dout_cnt
-add wave -noupdate -format Literal /tb_ssram_frontend_wb/inst_ssram_frontend_wb/vld_pipe
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk_fb
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1343191 ps} 0} {{Cursor 2} {178651436 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {6300 ns}
diff --git a/lib/SSRAM/src/CY7C1354B.vhd b/lib/SSRAM/src/CY7C1354B.vhd
deleted file mode 100644
index d652656..0000000
--- a/lib/SSRAM/src/CY7C1354B.vhd
+++ /dev/null
@@ -1,388 +0,0 @@
------------------------------------------------------------------------------------------
---
--- File Name: CY7C1354B.VHD
--- Version: 2.0
--- Date: Nov 22nd, 2004
--- Model: BUS Functional
---
---
--- Author: RKF
--- Company: Cypress Semiconductor
--- Model: CY7C1354B (256k x 36)
--- Mode: Pipelined
---
--- Description: NoBL SRAM VHDL Model
---
--- Limitation: None
---
--- Note: - BSDL Model available separately
--- - Set simulator resolution to "ps" timescale
---
--- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
--- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
---
--- Copyright (c) 2004 Cypress Semiconductor
--- All rights reserved
---
--- Trademarks: NoBL and No Bus Latency are trademarks of Cypress Semiconductor
---
--- Rev Author Date Changes
--- --- -------- ------- ----------
--- 2.0 RKF 11/22/2004 - Second Release
--- - Fully Tested with New Test Bench and Test Vectors
------------------------------------------------------------------------------------------
-
-LIBRARY ieee,work;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
- Use IEEE.Std_Logic_Arith.all;
--- Use work.all;
- USE work.package_utility.all;
-
-ENTITY cy7c1354 IS
-
- GENERIC (
-
- -- Constant parameters
- addr_bits : INTEGER := 18;
- data_bits : INTEGER := 32;
- par_bits : INTEGER := 4;
-
- -- Timing parameters for -5 (225 Mhz)
--- tCYC : TIME := 4.4 ns;
--- tCH : TIME := 1.8 ns;
--- tCL : TIME := 1.8 ns;
--- tCO : TIME := 2.8 ns;
--- tAS : TIME := 1.4 ns;
--- tCENS : TIME := 1.4 ns;
--- tWES : TIME := 1.4 ns;
--- tDS : TIME := 1.4 ns;
--- tAH : TIME := 0.4 ns;
--- tCENH : TIME := 0.4 ns;
--- tWEH : TIME := 0.4 ns;
--- tDH : TIME := 0.4 ns
-
-
-
- -- Timing parameters for -6 (200 Mhz)
- --tCYC : TIME := 5.0 ns;
- --tCH : TIME := 2.0 ns;
- --tCL : TIME := 2.0 ns;
- --tCO : TIME := 3.2 ns;
- --tAS : TIME := 1.5 ns;
- --tCENS : TIME := 1.5 ns;
- --tWES : TIME := 1.5 ns;
- --tDS : TIME := 1.5 ns;
- --tAH : TIME := 0.5 ns;
- --tCENH : TIME := 0.5 ns;
- --tWEH : TIME := 0.5 ns;
- --tDH : TIME := 0.5 ns
-
-
- -- Timing parameters for -7 (166 Mhz)
- tCYC : TIME := 6.0 ns;
- tCH : TIME := 2.4 ns;
- tCL : TIME := 2.4 ns;
- tCO : TIME := 3.5 ns;
- tAS : TIME := 1.5 ns;
- tCENS : TIME := 1.5 ns;
- tWES : TIME := 1.5 ns;
- tDS : TIME := 1.5 ns;
- tAH : TIME := 0.5 ns;
- tCENH : TIME := 0.5 ns;
- tWEH : TIME := 0.5 ns;
- tDH : TIME := 0.5 ns
-
-
-
- );
-
- -- Port Declarations
- PORT (
- Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O
- Dpq : INOUT STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0); -- Data parity I/O
- Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address
- Mode : IN STD_LOGIC := '1'; -- Burst Mode
- Clk : IN STD_LOGIC; -- Clk
- CEN_n : IN STD_LOGIC; -- CEN#
- AdvLd_n : IN STD_LOGIC; -- Adv/Ld#
- Bwa_n : IN STD_LOGIC; -- Bwa#
- Bwb_n : IN STD_LOGIC; -- BWb#
- Bwc_n : IN STD_LOGIC; -- Bwc#
- Bwd_n : IN STD_LOGIC; -- BWd#
- Rw_n : IN STD_LOGIC; -- RW#
- Oe_n : IN STD_LOGIC; -- OE#
- Ce1_n : IN STD_LOGIC; -- CE1#
- Ce2 : IN STD_LOGIC; -- CE2
- Ce3_n : IN STD_LOGIC; -- CE3#
- Zz : IN STD_LOGIC -- Snooze Mode
- );
-END cy7c1354;
-
-ARCHITECTURE behave OF cy7c1354 IS
- SIGNAL ce : STD_LOGIC := '0';
- SIGNAL doe : STD_LOGIC := '0';
- SIGNAL dout : STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
- SIGNAL dout_p : STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
- SIGNAL Addr_read_sig : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
-
-BEGIN
-
-
- ce <= NOT(Ce1_n) AND NOT(Ce3_n) AND Ce2;
-
- doe <= NOT(Oe_n) AND NOT(Zz);
-
- -- Output Buffers
- WITH doe SELECT
- Dq <= TRANSPORT dout AFTER (tCO) WHEN '1',
- (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
-
- WITH doe SELECT
- Dpq <= TRANSPORT dout_p AFTER (tCO) WHEN '1',
- (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
-
-
- -- Check for Clock Timing Violation
- clk_check : PROCESS
- VARIABLE clk_high, clk_low : TIME := 0 ns;
- BEGIN
- WAIT ON Clk;
- IF Clk = '1' AND NOW >= tCYC THEN
- ASSERT (NOW - clk_low >= tCH)
- REPORT "Clk width low - tCH violation"
- SEVERITY ERROR;
- ASSERT (NOW - clk_high >= tCYC)
- REPORT "Clk period high - tCYC violation"
- SEVERITY ERROR;
- clk_high := NOW;
- ELSIF Clk = '0' AND NOW /= 0 ns THEN
- ASSERT (NOW - clk_high >= tCL)
- REPORT "Clk width high - tCL violation"
- SEVERITY ERROR;
- ASSERT (NOW - clk_low >= tCYC)
- REPORT "Clk period low - tCYC violation"
- SEVERITY ERROR;
- clk_low := NOW;
- END IF;
- END PROCESS;
-
- -- Check for Setup Timing Violation
- setup_check : PROCESS
- BEGIN
- WAIT ON Clk;
- IF Clk = '1' and (Ce1_n = '0' and Ce2 = '1' and Ce3_n = '0') THEN
- ASSERT (Addr'LAST_EVENT >= tAS)
- REPORT "Addr - tAS violation"
- SEVERITY ERROR;
- ASSERT (CEN_n'LAST_EVENT >= tCENS)
- REPORT "CKE# - tCENS violation"
- SEVERITY ERROR;
- ASSERT (Ce1_n'LAST_EVENT >= tWES)
- REPORT "CE1# - tWES violation"
- SEVERITY ERROR;
- ASSERT (Ce2'LAST_EVENT >= tWES)
- REPORT "CE2 - tWES violation"
- SEVERITY ERROR;
- ASSERT (Ce3_n'LAST_EVENT >= tWES)
- REPORT "CE3# - tWES violation"
- SEVERITY ERROR;
- ASSERT (AdvLd_n'LAST_EVENT >= tWES)
- REPORT "ADV/LD# - tWES violation"
- SEVERITY ERROR;
- ASSERT (Rw_n'LAST_EVENT >= tWES)
- REPORT "RW# - tWES violation"
- SEVERITY ERROR;
- ASSERT (Bwa_n'LAST_EVENT >= tWES)
- REPORT "BWa# - tWES violation"
- SEVERITY ERROR;
- ASSERT (Bwb_n'LAST_EVENT >= tWES)
- REPORT "BWb# - tWES violation"
- SEVERITY ERROR;
- ASSERT (Bwc_n'LAST_EVENT >= tWES)
- REPORT "BWc# - tWES violation"
- SEVERITY ERROR;
- ASSERT (Bwd_n'LAST_EVENT >= tWES)
- REPORT "BWd# - tWES violation"
- SEVERITY ERROR;
- ASSERT (Dq'LAST_EVENT >= tDS)
- REPORT "Dq - tDS violation"
- SEVERITY ERROR;
- END IF;
- END PROCESS;
-
- -- Check for Hold Timing Violation
- hold_check : PROCESS
- BEGIN
- WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH);
- IF Clk'DELAYED(tAH) = '1' THEN
- ASSERT (Addr'LAST_EVENT > tAH)
- REPORT "Addr - tAH violation"
- SEVERITY ERROR;
- END IF;
- IF Clk'DELAYED(tCENH) = '1' THEN
- ASSERT (CEN_n'LAST_EVENT > tCENH)
- REPORT "CKE# - tCENH violation"
- SEVERITY ERROR;
- END IF;
- IF Clk'DELAYED(tDH) = '1' THEN
- ASSERT (Dq'LAST_EVENT > tDH)
- REPORT "Dq - tDH violation"
- SEVERITY ERROR;
- END IF;
- IF Clk'DELAYED(tWEH) = '1' THEN
- ASSERT (Ce1_n'LAST_EVENT > tWEH)
- REPORT "CE1# - tWEH violation"
- SEVERITY ERROR;
- ASSERT (Ce2'LAST_EVENT > tWEH)
- REPORT "CE2 - tWEH violation"
- SEVERITY ERROR;
- ASSERT (Ce3_n'LAST_EVENT > tWEH)
- REPORT "CE3 - tWEH violation"
- SEVERITY ERROR;
- ASSERT (AdvLd_n'LAST_EVENT > tWEH)
- REPORT "ADV/LD# - tWEH violation"
- SEVERITY ERROR;
- ASSERT (Rw_n'LAST_EVENT > tWEH)
- REPORT "RW# - tWEH violation"
- SEVERITY ERROR;
- ASSERT (Bwa_n'LAST_EVENT > tWEH)
- REPORT "BWa# - tWEH violation"
- SEVERITY ERROR;
- ASSERT (Bwb_n'LAST_EVENT > tWEH)
- REPORT "BWb# - tWEH violation"
- SEVERITY ERROR;
- ASSERT (Bwc_n'LAST_EVENT > tWEH)
- REPORT "BWc# - tWEH violation"
- SEVERITY ERROR;
- ASSERT (Bwd_n'LAST_EVENT > tWEH)
- REPORT "BWd# - tWEH violation"
- SEVERITY ERROR;
- END IF;
-
- END PROCESS;
-
- -- Main Program
- main : PROCESS
-
- TYPE memory_array IS ARRAY ((2**addr_bits) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (((data_bits+par_bits) / 4) - 1 DOWNTO 0);
-
- VARIABLE Addr_in : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
- VARIABLE first_Addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
- VARIABLE Addr_read : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
- VARIABLE Addr_write : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
- VARIABLE bAddr0, bAddr1 : STD_LOGIC := '0';
- VARIABLE bank0 : memory_array;
- VARIABLE bank1 : memory_array;
- VARIABLE bank2 : memory_array;
- VARIABLE bank3 : memory_array;
-
- VARIABLE ce_in : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
- VARIABLE rw_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "111";
- VARIABLE bwa_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
- VARIABLE bwb_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
- VARIABLE bwc_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
- VARIABLE bwd_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
- VARIABLE bcnt : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-
- BEGIN
- WAIT ON Clk;
- IF Clk'EVENT AND Clk = '1' THEN
- IF CEN_n = '0' AND Zz = '0' THEN
- -- Write Address Register
- Addr_write := Addr_read;
-
- -- Read Address Register
- Addr_read := Addr_in ((addr_bits - 1) DOWNTO 2) & bAddr1 & bAddr0;
-
- -- Address Register
- IF AdvLd_n = '0' and ce = '1' THEN
- Addr_in := Addr;
- first_Addr := Addr(1 DOWNTO 0);
- bcnt := Addr(1 DOWNTO 0);
- END IF;
-
-
- -- Burst Logic
- IF Mode = '0' AND AdvLd_n = '1' THEN
- bcnt := bcnt + 1;
- ELSIF Mode = '1' AND AdvLd_n = '1' THEN
- IF (CONV_INTEGER1 (first_Addr) REM 2 = 0) THEN
- bcnt := bcnt + 1;
- ELSIF (CONV_INTEGER1 (first_Addr) REM 2 = 1) THEN
- bcnt := bcnt - 1;
- END IF;
- END IF;
-
-
- bAddr1 := bcnt (1);
- bAddr0 := bcnt (0);
-
- -- Read Logic
- ce_in (0) := ce_in (1);
-
- IF AdvLd_n = '0' THEN
- ce_in (1) := ce;
- END IF;
-
- rw_in (0) := rw_in (1);
- rw_in (1) := rw_in (2);
-
- IF AdvLd_n = '0' THEN
- rw_in (2) := NOT(ce AND NOT(Rw_n));
- END IF;
-
- -- Write Registry and Data Coherency Control Logic
- bwa_in (0) := bwa_in (1);
- bwb_in (0) := bwb_in (1);
- bwc_in (0) := bwc_in (1);
- bwd_in (0) := bwd_in (1);
- bwa_in (1) := bwa_in (2);
- bwb_in (1) := bwb_in (2);
- bwc_in (1) := bwc_in (2);
- bwd_in (1) := bwd_in (2);
- bwa_in (2) := Bwa_n;
- bwb_in (2) := Bwb_n;
- bwc_in (2) := Bwc_n;
- bwd_in (2) := Bwd_n;
-
- -- Write Data to Memory
- IF rw_in (0) = '0' AND bwa_in (0) = '0' THEN
- bank0 (CONV_INTEGER1 (Addr_write)) := Dpq(0) & Dq ( (data_bits / 4) - 1 DOWNTO 0);
- END IF;
- IF rw_in (0) = '0' AND bwb_in (0) = '0' THEN
- bank1 (CONV_INTEGER1 (Addr_write)) := Dpq(1) & Dq ((data_bits / 2 - 1) DOWNTO (data_bits / 4));
- END IF;
- IF rw_in (0) = '0' AND bwc_in (0) = '0' THEN
- bank2 (CONV_INTEGER1 (Addr_write)) := Dpq(2) & Dq ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2));
- END IF;
- IF rw_in (0) = '0' AND bwd_in (0) = '0' THEN
- bank3 (CONV_INTEGER1 (Addr_write)) := Dpq(3) & Dq (data_bits - 1 DOWNTO (3 * (data_bits / 4)));
- END IF;
- END IF;
-
- Addr_read_sig <= Addr_read;
-
- -- Read Data from Memory Array
- IF ce_in (0) = '1' AND rw_in (1) = '1' THEN
- dout ((data_bits / 4) - 1 DOWNTO 0) <= bank0 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0);
- dout ((data_bits / 2 - 1) DOWNTO (data_bits / 4)) <= bank1 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0);
- dout ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2)) <= bank2 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0);
- dout (data_bits - 1 DOWNTO (3 * (data_bits / 4))) <= bank3 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0);
- dout_p(0) <= bank0 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
- dout_p(1) <= bank1 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
- dout_p(2) <= bank2 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
- dout_p(3) <= bank3 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
- ELSE
- dout <= (OTHERS => 'Z');
- dout_p <= (OTHERS => 'Z');
- END IF;
- END IF;
- END PROCESS;
-
-END behave;
-
-
-
diff --git a/lib/SSRAM/src/package_utility.vhd b/lib/SSRAM/src/package_utility.vhd
deleted file mode 100644
index 9fb543f..0000000
--- a/lib/SSRAM/src/package_utility.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
---****************************************************************
---** MODEL : package_utility **
---** COMPANY : Cypress Semiconductor **
---** REVISION: 1.0 Created new package utility model **
---** **
---****************************************************************
-Library ieee,work;
- Use ieee.std_logic_1164.all;
- Use IEEE.Std_Logic_Arith.all;
- Use IEEE.std_logic_TextIO.all;
- --- Use work.package_timing.all;
-
-Library Std;
- Use STD.TextIO.all;
-
-Package package_utility is
-
-FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR;
-FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER;
-
-End; -- package package_utility
-
-Package body package_utility is
-
-
-------------------------------------------------------------------------------------------------
---Converts string into std_logic_vector
-------------------------------------------------------------------------------------------------
-
-FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS
- VARIABLE result : STD_LOGIC_VECTOR(S'RANGE);
- BEGIN
- FOR i IN S'RANGE LOOP
- IF S(i) = '0' THEN
- result(i) := '0';
- ELSIF S(i) = '1' THEN
- result(i) := '1';
- ELSIF S(i) = 'X' THEN
- result(i) := 'X';
- ELSE
- result(i) := 'Z';
- END IF;
- END LOOP;
- RETURN result;
-END convert_string;
-
-------------------------------------------------------------------------------------------------
---Converts std_logic_vector into integer
-------------------------------------------------------------------------------------------------
-
-FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS
- VARIABLE result : INTEGER := 0;
- BEGIN
- FOR i IN S'RANGE LOOP
- IF S(i) = '1' THEN
- result := result + (2**i);
- ELSIF S(i) = '0' THEN
- result := result;
- ELSE
- result := 0;
- END IF;
- END LOOP;
- RETURN result;
- END CONV_INTEGER1;
-
-
-
-
-end package_utility;
-
-
-
-
diff --git a/lib/SSRAM/src/ssram_frontend_wb.vhd b/lib/SSRAM/src/ssram_frontend_wb.vhd
deleted file mode 100644
index 056b328..0000000
--- a/lib/SSRAM/src/ssram_frontend_wb.vhd
+++ /dev/null
@@ -1,181 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-ENTITY ssram_frontend_wb IS
- Generic
- (
- latency : natural := 2; -- clock cycles
- addr_width : natural := 20;
- data_width : natural := 32;
- parity_width : natural := 4
- );
- Port
- (
- -- J-Bus domain
- CLK_I : in STD_LOGIC;
- RST_I : in STD_LOGIC;
- CYC_I : in STD_LOGIC;
- STB_I : in STD_LOGIC;
- SEL_I : in unsigned(3 downto 0);
- WE_I : in STD_LOGIC;
- ACK_O : out STD_LOGIC;
- SRDY_O : out STD_LOGIC;
- MRDY_I : in STD_LOGIC;
- ADDR_I : in unsigned(31 downto 0);
- DAT_I : in unsigned(31 downto 0);
- DAT_O : out unsigned(31 downto 0);
-
- -- Sync SRAM domain
- ssram_clk_o : out std_logic;
- ssram_clk_fb : in std_logic;
- ssram_cke_n : out std_logic;
- ssram_ce_n : out std_logic;
- ssram_oe_n : out std_logic;
- ssram_we_n : out std_logic;
- ssram_adv : out std_logic;
- ssram_mode : out std_logic;
- ssram_zz : out std_logic;
- ssram_a : out unsigned(addr_width-1 downto 0);
- ssram_d : inout unsigned(data_width-1 downto 0);
- ssram_dp : inout unsigned(parity_width-1 downto 0);
- ssram_bw_n : out unsigned(3 downto 0)
- );
-END ssram_frontend_wb;
-
-ARCHITECTURE behavior OF ssram_frontend_wb IS
-
- constant topad : time := 3 ns;
- subtype ssram_d_t is unsigned(data_width+parity_width-1 downto 0);
- type data_pipe_t is array (latency downto 0) of ssram_d_t;
-
- signal ssram_clk : std_logic;
- signal dcm_locked : std_logic;
- signal dcm_clk0 : std_logic;
- signal dcm_clk1 : std_logic;
- signal data_en : std_logic;
- signal drive : std_logic;
- signal vld_pipe : unsigned(latency downto 0);
- signal drive_pipe : unsigned(latency downto 0);
- signal data_pipe : data_pipe_t;
- signal ssram_dout : ssram_d_t;
-
-begin
-
- SRDY_O <= CYC_I and dcm_locked;
- ACK_O <= vld_pipe(vld_pipe'left);
- DAT_O(data_width-1 downto 0) <= ssram_d;
-
- data_en <= CYC_I and STB_I;
- ssram_dout <= "0000" & DAT_I(data_width-1 downto 0);
- drive <= drive_pipe(drive_pipe'left);
-
- ssram_clk_o <= ssram_clk after topad;
- ssram_cke_n <= not dcm_locked after topad;
- ssram_oe_n <= not vld_pipe(vld_pipe'left-1) after topad;
-
-inst_clock_out : ODDR
- generic map
- (
- DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
- INIT => '0', -- Initial value for Q port ('1' or '0')
- SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
- )
- port map (
- Q => ssram_clk, -- 1-bit DDR output
- C => dcm_clk1, -- 1-bit clock input
- CE => '1', -- 1-bit clock enable input
- D1 => '1', -- 1-bit data input (positive edge)
- D2 => '0', -- 1-bit data input (negative edge)
- R => '0', -- 1-bit reset input
- S => '0' -- 1-bit set input
- );
-
-ssram_bufg: bufg
- port map
- (
- o => dcm_clk1,
- i => dcm_clk0
- );
-
-inst_DCM_BASE_0 : DCM_BASE
- generic map (
- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
- -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
- CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
- CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00
- CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
- CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
- DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
- DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
- -- an integer from 0 to 15
- DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
- DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
- FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
- STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
- port map (
- CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput
- CLK180 => open, -- 180 degree DCM CLK output
- CLK270 => open, -- 270 degree DCM CLK output
- CLK2X => open, -- 2X DCM CLK output
- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
- CLK90 => open, -- 90 degree DCM CLK output
- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
- CLKFX => open, -- DCM CLK synthesis out (M/D)
- CLKFX180 => open, -- 180 degree CLK synthesis out
- LOCKED => dcm_locked, -- DCM LOCK status output
- CLKFB => ssram_clk_fb, -- DCM clock feedback
- CLKIN => CLK_I, -- Clock input (from IBUFG, BUFG or DCM)
- RST => RST_I -- DCM asynchronous reset input
- );
-
-
-data_valid_pipeline:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- vld_pipe <= (others => '0');
- else
- vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & (data_en and MRDY_I and not WE_I);
- end if;
- end if;
- end process;
-
-data_out_pipeline:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- ssram_ce_n <= '1' after topad;
- ssram_we_n <= '1' after topad;
- ssram_adv <= '0' after topad;
- ssram_mode <= '0' after topad;
- ssram_zz <= '1' after topad;
- drive_pipe <= (others => '0');
- elsif dcm_locked = '1' then
- ssram_ce_n <= not data_en after topad;
- ssram_we_n <= not (WE_I and data_en) after topad;
- ssram_adv <= '0' after topad;
- ssram_mode <= '0' after topad;
- ssram_zz <= '0' after topad;
- ssram_a <= ADDR_I(addr_width-1 downto 0) after topad;
- ssram_bw_n <= not SEL_I after topad;
- drive_pipe <= drive_pipe(drive_pipe'left-1 downto 0) & (data_en and WE_I);
- data_pipe <= data_pipe(data_pipe'left-1 downto 0) & ssram_dout;
- end if;
- end if;
- end process;
-
- ssram_d <= data_pipe(data_pipe'left)(data_width-1 downto 0) after topad when drive = '1' else (others => 'Z') after topad;
- ssram_dp <= data_pipe(data_pipe'left)(data_width+parity_width-1 downto data_width) after topad when drive = '1' else (others => 'Z') after topad;
-
-end behavior;
diff --git a/lib/SSRAM/src/tb_ssram_frontend_wb.vhd b/lib/SSRAM/src/tb_ssram_frontend_wb.vhd
deleted file mode 100644
index 86f1411..0000000
--- a/lib/SSRAM/src/tb_ssram_frontend_wb.vhd
+++ /dev/null
@@ -1,457 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-USE work.package_utility.all;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-ENTITY tb_ssram_frontend_wb IS
-END tb_ssram_frontend_wb;
-
-ARCHITECTURE behavior OF tb_ssram_frontend_wb IS
-
- constant CLK_PERIOD : time := 10 ns;
- signal CLK_O : std_logic := '1';
- signal RST_O : std_logic := '1';
- signal CYC_O : std_logic := '0';
- signal STB_O : std_logic := '0';
- signal WE_O : std_logic := '0';
- signal SEL_O : unsigned(3 downto 0) := (others => '1');
- signal ACK_I : std_logic;
- signal MRDY_O : std_logic := '1';
- signal SRDY_I : std_logic;
- signal ADDR_O : unsigned(31 downto 0) := (others => '-');
- signal DAT_I : unsigned(31 downto 0);
- signal DAT_O : unsigned(31 downto 0) := (others => '-');
-
- SIGNAL ssram_d : unsigned (32 - 1 DOWNTO 0) := (OTHERS => 'Z');
- SIGNAL ssram_dp : unsigned (4 - 1 DOWNTO 0) := (OTHERS => 'Z');
- SIGNAL ssram_a : unsigned (20 - 1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL ssram_clk : STD_LOGIC := '0';
- SIGNAL ssram_cke_n : STD_LOGIC;
- SIGNAL ssram_adv : STD_LOGIC;
- SIGNAL ssram_mode : STD_LOGIC;
- SIGNAL ssram_bw_n : unsigned(3 downto 0);
- SIGNAL ssram_we_n : STD_LOGIC;
- SIGNAL ssram_oe_n : STD_LOGIC;
- SIGNAL ssram_ce_n : STD_LOGIC;
- SIGNAL ssram_zz : STD_LOGIC;
-
- SIGNAL ssram_clk_fb : STD_LOGIC;
-
- signal dout_rst : std_logic := '0';
- signal dout_reg : unsigned(31 downto 0);
- signal dout_cnt : natural range 0 to 255;
-
-BEGIN
-
- ssram_clk_fb <= ssram_clk after 0.5 ns;
-
-inst_ssram_frontend_wb : entity work.ssram_frontend_wb
- GENERIC MAP
- (
- addr_width => 20,
- data_width => 32,
- parity_width => 4
- )
- PORT MAP
- (
- -- J-Bus domain
- RST_I => RST_O,
- CLK_I => CLK_O,
- CYC_I => CYC_O,
- STB_I => STB_O,
- SEL_I => SEL_O,
- WE_I => WE_O,
- ACK_O => ACK_I,
- SRDY_O => SRDY_I,
- MRDY_I => MRDY_O,
- ADDR_I => ADDR_O,
- DAT_I => DAT_O,
- DAT_O => DAT_I,
-
- -- Sync SRAM domain
- ssram_clk_o => ssram_clk,
- ssram_clk_fb => ssram_clk_fb,
- ssram_cke_n => ssram_cke_n,
- ssram_ce_n => ssram_ce_n,
- ssram_oe_n => ssram_oe_n,
- ssram_we_n => ssram_we_n,
- ssram_adv => ssram_adv,
- ssram_mode => ssram_mode,
- ssram_zz => ssram_zz,
- ssram_a => ssram_a,
- ssram_d => ssram_d,
- ssram_dp => ssram_dp,
- ssram_bw_n => ssram_bw_n
- );
-
-inst_ssram : entity work.cy7c1354
- -- PORT MAP Declarations
- PORT MAP
- (
- Dq => STD_LOGIC_VECTOR(ssram_d), -- Data I/O
- Dpq => STD_LOGIC_VECTOR(ssram_dp), -- Data I/O
- Addr => STD_LOGIC_VECTOR(ssram_a(19 downto 2)), -- Address
- Mode => ssram_mode, -- Burst Mode
- Clk => ssram_clk, -- Clk
- CEN_n => ssram_cke_n, -- CEN#
- AdvLd_n => ssram_adv, -- Adv/Ld#
- Bwa_n => ssram_bw_n(0), -- Bwa#
- Bwb_n => ssram_bw_n(1), -- BWb#
- Bwc_n => ssram_bw_n(2), -- Bwc#
- Bwd_n => ssram_bw_n(3), -- BWd#
- Rw_n => ssram_we_n, -- RW#
- Oe_n => ssram_oe_n, -- OE#
- Ce1_n => ssram_ce_n, -- CE1#
- Ce2 => '1', -- CE2
- Ce3_n => '0', -- CE3#
- Zz => ssram_zz
- );
-
-read_register:
- process(CLK_O)
- begin
- if rising_edge(CLK_O) then
- if dout_rst = '1' then
- dout_cnt <= 0;
- elsif ACK_I = '1' and WE_O = '0' then
- dout_reg <= DAT_I;
- dout_cnt <= dout_cnt + 1;
- end if;
- end if;
- end process;
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- CLK_O <= not CLK_O;
- end process;
-
-STIMULUS: process
-
- begin
-
- wait for 5*CLK_PERIOD;
- RST_O <= '0';
-
- wait until rising_edge(CLK_O);
- -- 8 single cycles
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '1';
- DAT_O <= X"1234_0000";
- ADDR_O <= X"0000_0000";
-
- for i in 0 to 31 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- STB_O <= '0';
- wait until rising_edge(CLK_O);
- CYC_O <= '0';
-
- ------------------------------------------------------------
- wait for 3*CLK_PERIOD;
- ------------------------------------------------------------
-
- -- 8-word burst cycle
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '0';
- ADDR_O <= X"0000_0000";
-
- for i in 0 to 31 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- STB_O <= '0';
- wait until rising_edge(CLK_O) and dout_cnt = 31;
- CYC_O <= '0';
-
- ------------------------------------------------------------
- wait for 3*CLK_PERIOD;
- ------------------------------------------------------------
-
- wait until rising_edge(CLK_O);
- -- 1-word burst cycle
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '1';
- SEL_O <= "0011";
- ADDR_O <= X"0000_0010";
- DAT_O <= X"DEADBEEF";
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
- wait until rising_edge(CLK_O);
- CYC_O <= '0';
-
- ------------------------------------------------------------
- wait for 3*CLK_PERIOD;
- ------------------------------------------------------------
-
- wait until rising_edge(CLK_O);
- -- 1-word burst cycle
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '0';
- ADDR_O <= X"0000_0010";
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
- wait until rising_edge(CLK_O) and ACK_I = '1';
- CYC_O <= '0';
-
- ------------------------------------------------------------
- wait for 3*CLK_PERIOD;
- ------------------------------------------------------------
-
- -- 8-word burst cycle
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
-
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '0';
- ADDR_O <= X"0000_0000";
-
- for i in 0 to 31 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- STB_O <= '0';
- wait until rising_edge(CLK_O) and dout_cnt = 31;
- CYC_O <= '0';
-
- ------------------------------------------------------------
- wait for 10*CLK_PERIOD;
- ------------------------------------------------------------
-
-
- -- 8-word burst cycle
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
-
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '0';
- ADDR_O <= X"0000_0000";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- STB_O <= '0';
- wait until rising_edge(CLK_O) and dout_cnt = 7;
- CYC_O <= '0';
-
-
- ------------------------------------------------------------
- wait for 10*CLK_PERIOD;
- ------------------------------------------------------------
-
- -- 8-word burst cycle
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
-
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '1';
- SEL_O <= "1111";
- DAT_O <= X"1111_0000";
- ADDR_O <= X"0000_0000";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- WE_O <= '0';
- ADDR_O <= X"0000_0000";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- STB_O <= '0';
- wait until rising_edge(CLK_O) and dout_cnt = 7;
- CYC_O <= '0';
-
- -- 8-word burst cycle
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
-
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '1';
- SEL_O <= "1111";
- DAT_O <= X"2222_0000";
- ADDR_O <= X"0000_0400";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- WE_O <= '0';
- ADDR_O <= X"0000_0400";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- STB_O <= '0';
- wait until rising_edge(CLK_O) and dout_cnt = 7;
- CYC_O <= '0';
-
- -- 8-word burst cycle
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
-
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '1';
- SEL_O <= "1111";
- DAT_O <= X"3333_0000";
- ADDR_O <= X"0000_0800";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- WE_O <= '0';
- ADDR_O <= X"0000_0800";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- STB_O <= '0';
- wait until rising_edge(CLK_O) and dout_cnt = 7;
- CYC_O <= '0';
-
- -- 8-word burst cycle
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
-
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '1';
- SEL_O <= "1111";
- DAT_O <= X"4444_0000";
- ADDR_O <= X"0000_0C00";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- WE_O <= '0';
- ADDR_O <= X"0000_0C00";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- STB_O <= '0';
- wait until rising_edge(CLK_O) and dout_cnt = 7;
- CYC_O <= '0';
-
- ------------------------------------------------------------
- wait for 10*CLK_PERIOD;
- ------------------------------------------------------------
-
- -- 8-word burst cycle
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
-
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '0';
- ADDR_O <= X"0000_0000";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- ADDR_O <= X"0000_0400";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
-
- ADDR_O <= X"0000_0800";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
-
- ADDR_O <= X"0000_0C00";
-
- for i in 0 to 7 loop
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- end loop;
-
- STB_O <= '0';
- wait until rising_edge(CLK_O) and dout_cnt = 31;
- CYC_O <= '0';
-
- wait;
-
- end process;
-
-END;
diff --git a/lib/VGA_ctrl/src/align.vhd b/lib/VGA_ctrl/src/align.vhd
deleted file mode 100644
index 4da7d81..0000000
--- a/lib/VGA_ctrl/src/align.vhd
+++ /dev/null
@@ -1,151 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.utils_pkg.all; -- Imports the standard textio package.
-
-ENTITY align IS
- Generic
- (
- data_width : natural := 32;
- aggregate_size : natural := 8
- );
- Port
- (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- ce : in STD_LOGIC;
- eb : in STD_LOGIC;
- offset : in unsigned(NextExpBaseTwo(data_width/aggregate_size)-1 downto 0);
- din_vld : in STD_LOGIC;
- din : in unsigned(data_width-1 downto 0);
- dout_vld : out STD_LOGIC;
- dout : out unsigned(data_width-1 downto 0);
- byte_en : out unsigned (data_width/aggregate_size-1 downto 0)
-
- );
-END align;
-
-ARCHITECTURE behavior OF align IS
-
- signal shift_dout : unsigned(data_width-1 downto 0);
- signal shift_vld : std_logic;
-
- signal reg0_vld : std_logic;
- signal reg0 : unsigned(data_width-1 downto 0);
-
- signal reg : unsigned(data_width-1 downto 0);
- signal reg_vld : std_logic;
- signal reg_be : unsigned(data_width/aggregate_size-1 downto 0);
-
- signal data_vld : std_logic;
-
- type byte_en_rom_t is array (0 to 2*data_width/aggregate_size-1) of unsigned (data_width/aggregate_size-1 downto 0);
-
- function gen_byte_en_rom(N : natural) return byte_en_rom_t is
- variable k : integer;
- variable result : byte_en_rom_t;
- begin
-
- k:=0;
-
- result(k) := (others => '1');
- k := k + 1;
-
- for i in 1 to N-1 loop
- result(k) := (N-1 downto i => '1') & (i-1 downto 0 => '0');
- k := k + 1;
- end loop;
-
- result(k) := (others => '1');
- k := k + 1;
-
- for i in 1 to N-1 loop
- result(k) := (N-1 downto i => '0') & (i-1 downto 0 => '1');
- k := k + 1;
- end loop;
-
- return result;
- end gen_byte_en_rom;
-
- signal byte_en_rom : byte_en_rom_t := gen_byte_en_rom(data_width/aggregate_size);
- signal be : unsigned (data_width/aggregate_size-1 downto 0);
-
---------------------------------------------------------------------------
-begin
-
- be <= byte_en_rom(to_integer(not eb & offset));
- byte_en <= be;
- dout <= reg;
- dout_vld <= data_vld;
-
-inst_shifter : entity work.shifter
- GENERIC MAP
- (
- data_width => data_width,
- aggregate_size => aggregate_size,
- do_pipelined => true
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- ce => ce,
- sa => to_integer(offset),
- din_vld => din_vld,
- din => din,
- dout_vld => shift_vld,
- dout => shift_dout
-
- );
-
-proc_data_valid:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- reg0_vld <= '0';
- data_vld <= '0';
- elsif ce = '1' then
- reg0_vld <= shift_vld;
- data_vld <= shift_vld;
- end if;
- end if;
- end process;
-
-proc_align:
- process(clk)
- begin
- if rising_edge(clk) then
- if ce = '1' then
- if shift_vld = '1' then
- reg0 <= shift_dout;
- end if;
- end if;
- end if;
- end process;
-
-proc_blit_dst_combine:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- reg_vld <= '0';
- elsif ce = '1' then
- if reg0_vld = '1' or shift_vld = '1' then
- reg_vld <= '1';
- reg <= reg0;
- if shift_vld = '1' then
- for i in 0 to data_width/aggregate_size-1 loop
- if be(i) = '1' then
- reg(aggregate_size*(i+1)-1 downto aggregate_size*i) <= shift_dout(aggregate_size*(i+1)-1 downto aggregate_size*i);
- end if;
- end loop;
- end if;
- end if;
- end if;
- end if;
- end process;
-
---------------------------------------------------------------------------
-end behavior;
diff --git a/lib/VGA_ctrl/src/clkgen_virtex4.vhd b/lib/VGA_ctrl/src/clkgen_virtex4.vhd
index 0a08d0c..d56bd66 100644
--- a/lib/VGA_ctrl/src/clkgen_virtex4.vhd
+++ b/lib/VGA_ctrl/src/clkgen_virtex4.vhd
@@ -32,8 +32,8 @@ use UNISIM.vcomponents.all;
entity clkgen is
Generic
(
- clk_in_freq : real := 100.0;
- clk_out_freq : real := 100.0
+ clk_in_freq_hz : integer := 100E6;
+ clk_out_freq_hz : integer := 100E6
);
Port
(
@@ -57,10 +57,10 @@ architecture tech of clkgen is
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
- CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, clk_out_freq), -- Can be any interger from 1 to 32
- CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, clk_out_freq), -- Can be any integer from 2 to 32
+ CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, clk_out_freq_hz), -- Can be any interger from 1 to 32
+ CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, clk_out_freq_hz), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
- CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
+ CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
diff --git a/lib/VGA_ctrl/src/shifter.vhd b/lib/VGA_ctrl/src/shifter.vhd
deleted file mode 100644
index fb57b6f..0000000
--- a/lib/VGA_ctrl/src/shifter.vhd
+++ /dev/null
@@ -1,133 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-use work.utils_pkg.all; -- Imports the standard textio package.
-
-ENTITY shifter IS
- Generic
- (
- data_width : natural := 32;
- aggregate_size : natural := 8;
- positive_shift_left : boolean := true;
- do_pipelined : boolean := true
- );
- Port
- (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- ce : in STD_LOGIC;
- sa : in integer;
- din_vld : in STD_LOGIC;
- din : in unsigned(data_width-1 downto 0);
- dout_vld : out STD_LOGIC;
- dout : out unsigned(data_width-1 downto 0)
-
- );
-END shifter;
-
-ARCHITECTURE behavior OF shifter IS
-
- constant num_rounds : natural := NextExpBaseTwo(data_width/aggregate_size);
- subtype sa_rnd_t is signed(num_rounds-1 downto 0);
- subtype word_t is unsigned(data_width-1 downto 0);
- type word_array_t is array (0 to num_rounds) of word_t;
-
- signal rot_data : word_array_t;
- signal sa_rnd : sa_rnd_t;
-
- type sa_rnd_array_t is array (0 to num_rounds) of sa_rnd_t;
- signal sa_rnd_pipe : sa_rnd_array_t;
- signal dout_vld_pipe : unsigned(0 to num_rounds);
-
---------------------------------------------------------------------------
-function rol_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
- variable result : unsigned(x'range);
- constant sa : natural := (2**stage_num) * size;
- begin
- if en = '1' then
- result := x(x'left-sa downto 0) & x(x'left downto x'length-sa);
- else
- result := x;
- end if;
- return result;
-
-end rol_stage;
-
-
-function ror_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
- variable result : unsigned(x'range);
- constant sa : natural := (2**stage_num) * size;
- begin
- if en = '1' then
- result := x(sa-1 downto 0) & x(x'left downto sa);
- else
- result := x;
- end if;
- return result;
-
-end ror_stage;
-
---------------------------------------------------------------------------
-begin
-
---------------------------------------------------------------------------
-gen_non_pipelined:
-if do_pipelined = false generate
-begin
-
- rot_data(0) <= din;
-
-gen_rotate:
- for stage in 0 to num_rounds-1 generate
- begin
- rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size) when positive_shift_left else
- ror_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size);
- end generate;
-
- sa_rnd <= to_signed(sa, num_rounds);
- dout <= rot_data(num_rounds);
- dout_vld <= din_vld;
-
-end generate;
-
---------------------------------------------------------------------------
-gen_pipelined:
-if do_pipelined = true generate
-begin
-
- rot_data(0) <= din;
- sa_rnd_pipe(0) <= to_signed(sa, num_rounds);
- dout_vld_pipe(0) <= din_vld;
-
-gen_rotate:
- for stage in 0 to num_rounds-1 generate
- begin
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- dout_vld_pipe(stage+1) <= '0';
- elsif ce = '1' then
- dout_vld_pipe(stage+1) <= dout_vld_pipe(stage);
- if dout_vld_pipe(stage) = '1' then
- sa_rnd_pipe(stage+1) <= sa_rnd_pipe(stage);
- if positive_shift_left then
- rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
- else
- rot_data(stage+1) <= ror_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
- end if;
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- dout <= rot_data(num_rounds);
- dout_vld <= dout_vld_pipe(num_rounds);
-
-end generate;
-
---------------------------------------------------------------------------
-end behavior;
diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
index 1fea15b..ac7ec08 100644
--- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
@@ -66,7 +66,6 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
signal rdy : std_logic := '0';
signal read_reg : unsigned(31 downto 0) := (others => '-');
- signal const_color : unsigned(31 downto 0) := X"1111_1111";
-- VGA signals
signal vga_clk : std_logic := '1';
@@ -79,11 +78,6 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
signal vga_vsync : std_logic;
signal vga_en : std_logic;
- type blit_size_array_t is array (0 to 6) of natural;
-
- constant blit_size_x : blit_size_array_t := (32, 31, 32, 31, 1, 32, 1);
- constant blit_size_y : blit_size_array_t := (32, 32, 31, 31, 32, 1, 1);
-
BEGIN
inst_vga_frontend64 : entity work.vga_frontend64
@@ -92,7 +86,6 @@ inst_vga_frontend64 : entity work.vga_frontend64
fifo_depth => 2048,
fifo_almost_full_thresh => 2048-128,
fifo_almost_empty_thresh => 512,
- BLIT_CHUNK_SIZE => 512,
tsvga => tsvga
)
PORT MAP
@@ -213,39 +206,6 @@ VGA_CLK_GEN: process
-- Master
STIMULUS: process
- variable result : unsigned(31 downto 0);
-
- procedure reg_write(reg, val : unsigned) is
- begin
-
- CYC_O <= '1';
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- WE_O <= '1';
- ADDR_O <= reg;
- SDAT_O <= val;
- STB_O <= '1';
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
- CYC_O <= '0';
-
- end procedure reg_write;
-
- procedure reg_read(reg : unsigned) is
- begin
-
- CYC_O <= '1';
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- WE_O <= '0';
- ADDR_O <= reg;
- STB_O <= '1';
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
- CYC_O <= '0';
- wait until rising_edge(CLK_O) and ACK_I = '1';
- result := SDAT_I;
-
- end procedure reg_read;
-
begin
wait for 6*CLK_PERIOD;
@@ -391,225 +351,105 @@ STIMULUS: process
wait for 60000*CLK_PERIOD;
- for i in 0 to blit_size_array_t'length-1 loop
+ for i in 0 to 99 loop
-
- -------------------------------------------------
- -- BLIT aligned => aligned test
- -------------------------------------------------
- while(true) loop
- reg_read(X"0000_0000");
- if result(8) = '0' then
- exit;
- end if;
- end loop;
-
- -- set source start address
- reg_write(X"0000_0020", X"4100_0000");
-
+ -- BLIT test
+ -- Read status
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_0000";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and ACK_I = '1';
+ -- set src addr first
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_O <= X"4100_0000";
+ ADDR_O <= X"0000_0020";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+ -- set src addr last
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_O <= X"4100_0000" + to_unsigned(4*(80*4-1), 32);
+ ADDR_O <= X"0000_0024";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
-- set src dim-x
- reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set destination start address
- reg_write(X"0000_0050", X"4200_0000");
-
- -- set constant color
- reg_write(X"0000_0054", const_color);
-
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_O <= to_unsigned(4*80, 32);
+ ADDR_O <= X"0000_0028";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+ -- set dst addr first
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_O <= X"4200_0000";
+ ADDR_O <= X"0000_0050";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+ -- set dst addr last
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_O <= X"4200_0000" + to_unsigned(4*(80*4-1), 32);
+ ADDR_O <= X"0000_0054";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
-- set dst dim-x
- reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_O <= to_unsigned(4*80, 32);
+ ADDR_O <= X"0000_0058";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
-- set nx
- reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_O <= to_unsigned(80-1, 32);
+ ADDR_O <= X"0000_0060";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
-- set ny
- reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_O <= X"0000_0003";
+ ADDR_O <= X"0000_0064";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
-- set blit request
- reg_read(X"0000_0000");
- reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_O <= read_reg or X"0000_0100";
+ ADDR_O <= X"0000_0000";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+ CYC_O <= '0';
+ WE_O <= '0';
+ wait for 100000*CLK_PERIOD;
- -------------------------------------------------
- -- BLIT unaligned => aligned test
- -------------------------------------------------
- while(true) loop
- reg_read(X"0000_0000");
- if result(8) = '0' then
- exit;
- end if;
- end loop;
-
- -- set source start address
- reg_write(X"0000_0020", X"4100_0004");
-
- -- set src dim-x
- reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set destination start address
- reg_write(X"0000_0050", X"4200_0000");
-
- -- set constant color
- reg_write(X"0000_0054", const_color);
-
- -- set dst dim-x
- reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set nx
- reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-
- -- set ny
- reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-
- -- set blit request
- reg_read(X"0000_0000");
- reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-
-
- -------------------------------------------------
- -- BLIT aligned => unaligned test
- -------------------------------------------------
- while(true) loop
- reg_read(X"0000_0000");
- if result(8) = '0' then
- exit;
- end if;
- end loop;
-
- -- set source start address
- reg_write(X"0000_0020", X"4100_0000");
-
- -- set src dim-x
- reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set destination start address
- reg_write(X"0000_0050", X"4200_0004");
-
- -- set constant color
- reg_write(X"0000_0054", const_color);
-
- -- set dst dim-x
- reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set nx
- reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-
- -- set ny
- reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-
- -- set blit request
- reg_read(X"0000_0000");
- reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-
-
- -------------------------------------------------
- -- BLIT unaligned => unaligned test
- -------------------------------------------------
- while(true) loop
- reg_read(X"0000_0000");
- if result(8) = '0' then
- exit;
- end if;
- end loop;
-
- -- set source start address
- reg_write(X"0000_0020", X"4100_0004");
-
- -- set src dim-x
- reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set destination start address
- reg_write(X"0000_0050", X"4200_0004");
-
- -- set constant color
- reg_write(X"0000_0054", const_color);
-
- -- set dst dim-x
- reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set nx
- reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-
- -- set ny
- reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-
- -- set blit request
- reg_read(X"0000_0000");
- reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-
- -------------------------------------------------
- -- BLIT const => aligned test
- -------------------------------------------------
- while(true) loop
- reg_read(X"0000_0000");
- if result(8) = '0' then
- exit;
- end if;
- end loop;
-
- -- set source start address
- reg_write(X"0000_0020", X"4100_0000");
-
- -- set src dim-x
- reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set destination start address
- reg_write(X"0000_0050", X"4200_0000");
-
- -- set constant color
- reg_write(X"0000_0054", const_color);
-
- -- set dst dim-x
- reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set nx
- reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-
- -- set ny
- reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-
- -- set blit request
- reg_read(X"0000_0000");
- reg_write(X"0000_0000", result or X"0001_0100");
-
- -------------------------------------------------
- -- BLIT const => unaligned test
- -------------------------------------------------
- while(true) loop
- reg_read(X"0000_0000");
- if result(8) = '0' then
- exit;
- end if;
- end loop;
-
- -- set source start address
- reg_write(X"0000_0020", X"4100_0000");
-
- -- set src dim-x
- reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set destination start address
- reg_write(X"0000_0050", X"4200_0004");
-
- -- set constant color
- reg_write(X"0000_0054", const_color);
-
- -- set dst dim-x
- reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-
- -- set nx
- reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-
- -- set ny
- reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-
- -- set blit request
- reg_read(X"0000_0000");
- reg_write(X"0000_0000", result or X"0001_0100");
-
- wait for 60000*CLK_PERIOD;
- const_color <= const_color + X"1111_1111";
-
+
end loop;
wait;
diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd
index 66177b3..93973f0 100644
--- a/lib/VGA_ctrl/src/vga_frontend64.vhd
+++ b/lib/VGA_ctrl/src/vga_frontend64.vhd
@@ -30,7 +30,6 @@ entity vga_frontend64 is
fifo_depth : integer := 2048;
fifo_almost_full_thresh : natural := 2000;
fifo_almost_empty_thresh : natural := 48;
- BLIT_CHUNK_SIZE : natural := 512;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
Port
@@ -155,11 +154,10 @@ architecture Behavioral of vga_frontend64 is
signal vga_scan_dma_en2 : std_logic;
signal request_cnt_rst : std_logic;
signal request_en : std_logic;
- signal bus_read_en : std_logic;
+ signal read_bus_en : std_logic;
signal request_cnt : unsigned(28 downto 0);
signal read_cnt : unsigned(28 downto 0);
signal bus_read_fin : std_logic;
- signal bus_cycle_en : std_logic;
signal CYC_O_scan : std_logic;
signal STB_O_scan : std_logic;
@@ -168,34 +166,18 @@ architecture Behavioral of vga_frontend64 is
signal front : unsigned(31 downto 0);
signal back : unsigned(31 downto 0);
-
-- Blitter vars
+ constant BLIT_CHUNK_SIZE : natural := 512;
signal blit_chunk_cnt : natural range 0 to BLIT_CHUNK_SIZE-1;
- signal blit_chunk_cnt_rst : std_logic;
- signal blit_chunk_cnt_en : std_logic;
- -- Source Blitter FIFO signals
- signal blitfifo_src_full : std_logic;
- signal blitfifo_src_empty : std_logic;
- signal blitfifo_src_re : std_logic;
- signal blitfifo_src_we : std_logic;
- signal blitfifo_src_out : unsigned(63 downto 0);
- signal blitfifo_src_in : unsigned(63 downto 0);
+ -- Blitter FIFO signals
+ signal blitfifo_full : std_logic;
+ signal blitfifo_empty : std_logic;
+ signal blitfifo_color_re : std_logic;
+ signal blitfifo_color_we : std_logic;
+ signal blitfifo_color_out : unsigned(63 downto 0);
+ signal blitfifo_color_in : unsigned(63 downto 0);
- -- Source alignment register
- signal blit_src_addr : unsigned(2 downto 0);
- signal blit_src_reg_vld : std_logic;
- signal blit_src_reg : unsigned(63 downto 0);
- signal blit_src_rdy : std_logic;
- signal blit_src_we : std_logic;
- signal blit_src_re : std_logic;
- signal blit_src_unaligned : std_logic;
- signal blit_src_do_extra : std_logic;
- signal blit_src_do_extra2 : std_logic;
-
- signal blit_src_row_cnt : unsigned(31 downto 0);
- signal blit_src_first : std_logic;
- signal blit_src_last : std_logic;
signal blit_src_cnt_x : unsigned(31 downto 0);
signal blit_src_cnt_y : unsigned(31 downto 0);
signal blit_src_off_y : unsigned(31 downto 0);
@@ -205,72 +187,42 @@ architecture Behavioral of vga_frontend64 is
signal STB_O_blit_src : std_logic;
signal ADDR_O_blit_src : unsigned(31 downto 0);
- -- Destination alignment register
- signal blit_dst_reg : unsigned(63 downto 0);
- signal blit_dst_reg_vld : std_logic;
- signal blit_dst_unaligned : std_logic;
- signal blit_dst_row_cnt : unsigned(31 downto 0);
- signal blit_dst_first : std_logic;
- signal blit_dst_last : std_logic;
- signal blit_dst_do_extra : std_logic;
- signal blit_dst_reg_be : unsigned(7 downto 0);
- signal blit_dst_rdy : std_logic;
- signal blit_dst_we : std_logic;
- signal blit_dst_re : std_logic;
- signal blit_dst_be : unsigned(7 downto 0);
- signal blit_dst_vld : std_logic;
signal blit_dst_cnt_x : unsigned(31 downto 0);
signal blit_dst_cnt_y : unsigned(31 downto 0);
signal blit_dst_off_y : unsigned(31 downto 0);
signal blit_dst_offset : unsigned(31 downto 0);
signal blit_dst_finish : std_logic;
-
- signal blit_const_color : unsigned(31 downto 0);
- signal blit_const_color_en : std_logic;
- signal blit_const_color_vld : std_logic;
-
-
signal CYC_O_blit_dst : std_logic;
signal STB_O_blit_dst : std_logic;
signal ADDR_O_blit_dst : unsigned(31 downto 0);
signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
- -- Bus output FIFO
- signal busout_fifo_din : unsigned(104 downto 0);
- signal busout_fifo_dout : unsigned(104 downto 0);
- signal busout_fifo_re : std_logic;
- signal busout_fifo_we : std_logic;
- signal busout_fifo_full : std_logic;
- signal busout_fifo_empty : std_logic;
- signal busout_fifo_rdy : std_logic;
+ -- Bus FIFO
+ signal bus_fifo_din : unsigned(104 downto 0);
+ signal bus_fifo_dout : unsigned(104 downto 0);
+ signal bus_fifo_re : std_logic;
+ signal bus_fifo_we : std_logic;
+ signal bus_fifo_full : std_logic;
+ signal bus_fifo_empty : std_logic;
+ signal bus_rdy : std_logic;
- alias busout_fifo_addr_in is busout_fifo_din(31 downto 0);
- alias busout_fifo_data_in is busout_fifo_din(95 downto 32);
- alias busout_fifo_sel_in is busout_fifo_din(103 downto 96);
- alias busout_fifo_we_in is busout_fifo_din(104);
+ alias bus_fifo_addr_in is bus_fifo_din(31 downto 0);
+ alias bus_fifo_data_in is bus_fifo_din(95 downto 32);
+ alias bus_fifo_sel_in is bus_fifo_din(103 downto 96);
+ alias bus_fifo_we_in is bus_fifo_din(104);
- alias busout_fifo_addr_out is busout_fifo_dout(31 downto 0);
- alias busout_fifo_data_out is busout_fifo_dout(95 downto 32);
- alias busout_fifo_sel_out is busout_fifo_dout(103 downto 96);
- alias busout_fifo_we_out is busout_fifo_dout(104);
+ alias bus_fifo_addr_out is bus_fifo_dout(31 downto 0);
+ alias bus_fifo_data_out is bus_fifo_dout(95 downto 32);
+ alias bus_fifo_sel_out is bus_fifo_dout(103 downto 96);
+ alias bus_fifo_we_out is bus_fifo_dout(104);
- -- Bus input FIFO
- signal busin_fifo_din : unsigned(63 downto 0);
- signal busin_fifo_dout : unsigned(63 downto 0);
- signal busin_fifo_re : std_logic;
- signal busin_fifo_we : std_logic;
- signal busin_fifo_full : std_logic;
- signal busin_fifo_empty : std_logic;
- signal busin_fifo_rdy : std_logic;
- signal busin_fifo_dout_vld : std_logic;
-
- type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_prime_pipe, blit_dst_bus_request, bus_fin);
+ type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_bus_request, blit_dst_bus_fin);
signal s, sn : vm_state_t;
---------------------------------------------------------------------------
begin
+
proc_synced_vga_scan_en:
process(CLK_I)
begin
@@ -305,7 +257,7 @@ proc_blit_request_flags:
blit_request <= '0';
elsif blit_request_set = '1' then
blit_request <= '1';
- elsif blit_dst_finish = '1' then
+ elsif blit_dst_finish = '1' and blitfifo_empty = '1' then
blit_request <= '0';
end if;
end if;
@@ -317,7 +269,7 @@ proc_blit_complete_flag:
if rising_edge(CLK_I) then
if RST_I = '1' or blit_request_set = '1' or blit_complete_ack = '1' then
blit_complete <= '0';
- elsif blit_dst_finish = '1' and blit_request = '1' then
+ elsif blit_dst_finish = '1' and blitfifo_empty = '1' and blit_request = '1' then
blit_complete <= '1';
end if;
end if;
@@ -367,12 +319,12 @@ inst_vga_backend : entity work.vga_backend
);
SRDY_O <= CYC_I; -- and cg_rdy;
- MRDY_O <= busin_fifo_rdy; --not fifo_full;
- STB_O <= not busout_fifo_empty;
- ADDR_O <= busout_fifo_addr_out;
- MDAT_O <= busout_fifo_data_out;
- SEL_O <= busout_fifo_sel_out;
- WE_O <= busout_fifo_we_out;
+ MRDY_O <= not fifo_full;
+ STB_O <= not bus_fifo_empty;
+ ADDR_O <= bus_fifo_addr_out;
+ MDAT_O <= bus_fifo_data_out;
+ SEL_O <= bus_fifo_sel_out;
+ WE_O <= bus_fifo_we_out;
odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length);
ctrl_scan_en <= '1';
@@ -407,71 +359,67 @@ inst_linefifo: entity work.fifo_async
);
- fifo_color_in <= busin_fifo_dout;
+ fifo_color_in <= MDAT_I;
fifo_color_re <= stat_scan and odd_pixel(0);
- fifo_color_we <= busin_fifo_dout_vld and CYC_O_scan; -- TODO:
+ fifo_color_we <= ACK_I and read_bus_en and CYC_O_scan; -- TODO:
--- Bus input FIFO
-inst_busin_fifo: entity work.fifo_sync
+inst_blitfifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE),
+ data_width => 64
+ )
+ PORT MAP
+ (
+ rst => blit_reset,
+ clk => CLK_I,
+ we => blitfifo_color_we,
+ re => blitfifo_color_re,
+ data_w => blitfifo_color_in,
+ data_r => blitfifo_color_out,
+ fifo_full => blitfifo_full,
+ fifo_empty => blitfifo_empty,
+ fifo_afull => open,
+ fifo_aempty => open
+
+ );
+
+ blitfifo_color_in <= MDAT_I;
+ blitfifo_color_re <= STB_O_blit_dst and bus_rdy;
+ blitfifo_color_we <= ACK_I and read_bus_en and CYC_O_blit_src; -- TODO:
+
+-- Instantiate synchronous FIFO
+inst_bus_fifo: entity work.fifo_sync
GENERIC MAP
(
- addr_width => 2,
- data_width => busin_fifo_din'length,
- do_last_read_update => true
+ addr_width => 2,
+ data_width => 105
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
- we => busin_fifo_we,
- re => busin_fifo_re,
- fifo_full => busin_fifo_full,
- fifo_empty => busin_fifo_empty,
+ we => bus_fifo_we,
+ re => bus_fifo_re,
+ fifo_full => bus_fifo_full,
+ fifo_empty => bus_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
- data_w => busin_fifo_din,
- data_r => busin_fifo_dout
+ data_w => bus_fifo_din,
+ data_r => bus_fifo_dout
);
- busin_fifo_rdy <= not busin_fifo_full;
- busin_fifo_din <= MDAT_I;
- busin_fifo_we <= ACK_I and bus_cycle_en and bus_read_en;
- busin_fifo_dout_vld <= not busin_fifo_empty;
- busin_fifo_re <= not fifo_full when CYC_O_scan = '1' else blit_src_we;
-
--- Bus output FIFO
-inst_busout_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => 2,
- data_width => busout_fifo_din'length,
- do_last_read_update => false
- )
- PORT MAP
- (
- rst => RST_I,
- clk => CLK_I,
- we => busout_fifo_we,
- re => busout_fifo_re,
- fifo_full => busout_fifo_full,
- fifo_empty => busout_fifo_empty,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => busout_fifo_din,
- data_r => busout_fifo_dout
- );
- busout_fifo_rdy <= not busout_fifo_full;
- busout_fifo_re <= not busout_fifo_empty and SRDY_I;
- busout_fifo_we <= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst);
- busout_fifo_data_in <= blit_dst_reg;
- busout_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
+ bus_rdy <= not bus_fifo_full;
+ bus_fifo_re <= not bus_fifo_empty and SRDY_I;
+ bus_fifo_we <= STB_O_scan or STB_O_blit_src or STB_O_blit_dst;
+ bus_fifo_data_in <= blitfifo_color_out;
+ bus_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
ADDR_O_scan;
- busout_fifo_sel_in <= blit_dst_be when CYC_O_blit_dst = '1' else (others => '1');
- busout_fifo_we_in <= CYC_O_blit_dst;
- CYC_O <= bus_cycle_en;
+ bus_fifo_sel_in <= (others => '1');
+ bus_fifo_we_in <= CYC_O_blit_dst;
-------------------------------------------------------------------------------------
--- VGA master FSM
+ CYC_O <= CYC_O_scan or CYC_O_blit_src or CYC_O_blit_dst;
+
vga_master_next:
process(CLK_I)
begin
@@ -485,7 +433,7 @@ vga_master_next:
end process;
vga_master:
- process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_rdy, busout_fifo_empty, blit_chunk_cnt, blitfifo_src_empty, blit_dst_vld, blit_src_finish, blit_const_color_en)
+ process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, bus_read_fin, bus_fifo_empty, blit_chunk_cnt, blitfifo_empty, blit_src_finish)
begin
CYC_O_scan <= '0';
@@ -496,13 +444,9 @@ vga_master:
STB_O_blit_dst <= '0';
request_cnt_rst <= '0';
request_en <= '0';
- bus_read_en <= '0';
-
- bus_cycle_en <= '0';
- blit_chunk_cnt_rst <= '0';
- blit_chunk_cnt_en <= '0';
-
+ read_bus_en <= '0';
sn <= s;
+
case s is
when init =>
if stat_vga_rdy = '1' then
@@ -511,75 +455,59 @@ vga_master:
when rdy =>
request_cnt_rst <= '1';
- blit_chunk_cnt_rst <= '1';
if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then
sn <= scan_bus_request;
- elsif blit_request = '1' then -- ToDo: richtig prüfen anhand eines states wer dran ist. Nicht auf FIFO state prüfen
- if blitfifo_src_empty = '0' or blit_dst_vld = '1' then
- sn <= blit_dst_prime_pipe;
- elsif blit_const_color_en = '0' then
+ elsif blit_request = '1' then
+ if blitfifo_empty = '1' then
sn <= blit_src_bus_request;
+ else
+ sn <= blit_dst_bus_request;
end if;
end if;
when scan_bus_request =>
- bus_cycle_en <= '1';
CYC_O_scan <= '1';
STB_O_scan <= '1';
request_en <= '1';
- bus_read_en <= '1';
+ read_bus_en <= '1';
if fifo_almost_full = '1' then
sn <= scan_bus_read;
end if;
when scan_bus_read =>
- bus_cycle_en <= '1';
- CYC_O_scan <= '1';
- bus_read_en <= '1';
+ CYC_O_scan <= '1';
+ read_bus_en <= '1';
if bus_read_fin = '1' then
sn <= rdy;
end if;
when blit_src_bus_request =>
- bus_cycle_en <= '1';
CYC_O_blit_src <= '1';
STB_O_blit_src <= '1';
request_en <= '1';
- bus_read_en <= '1';
- blit_chunk_cnt_en <= '1';
+ read_bus_en <= '1';
if blit_chunk_cnt = 0 or blit_src_finish = '1' then
sn <= blit_src_bus_read;
end if;
when blit_src_bus_read =>
- bus_cycle_en <= '1';
CYC_O_blit_src <= '1';
- bus_read_en <= '1';
+ read_bus_en <= '1';
if bus_read_fin = '1' then
sn <= rdy;
end if;
- when blit_dst_prime_pipe =>
- bus_cycle_en <= '1';
- CYC_O_blit_dst <= '1';
- STB_O_blit_dst <= blit_dst_vld;
- blit_chunk_cnt_en <= blit_dst_vld;
- if blit_dst_vld = '1' then
- sn <= blit_dst_bus_request;
- end if;
-
when blit_dst_bus_request =>
- bus_cycle_en <= '1';
CYC_O_blit_dst <= '1';
- STB_O_blit_dst <= blit_dst_vld;
- blit_chunk_cnt_en <= blit_dst_vld;
- if blit_chunk_cnt = 0 or blit_dst_vld = '0' then
- sn <= bus_fin;
+ STB_O_blit_dst <= '1';
+ if blitfifo_empty = '1' then
+ STB_O_blit_dst <= '0';
+ sn <= blit_dst_bus_fin;
end if;
- when bus_fin =>
- bus_cycle_en <= '1';
- if busout_fifo_empty = '1' then
+ when blit_dst_bus_fin =>
+ CYC_O_blit_dst <= '1';
+ if bus_fifo_empty = '1' then
sn <= rdy;
end if;
@@ -589,14 +517,13 @@ vga_master:
end case;
end process;
-------------------------------------------------------------------------------------
proc_bus_request_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
request_cnt <= (others => '0');
- elsif request_en = '1' and busout_fifo_rdy = '1' then
+ elsif request_en = '1' and bus_rdy = '1' then
request_cnt <= request_cnt + 1;
end if;
end if;
@@ -608,7 +535,7 @@ proc_bus_read_counter:
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
read_cnt <= (others => '0');
- elsif busin_fifo_dout_vld = '1' then
+ elsif read_bus_en = '1' and ACK_I = '1' then
read_cnt <= read_cnt + 1;
end if;
end if;
@@ -629,17 +556,16 @@ proc_blit_chunk_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
- if blit_chunk_cnt_rst = '1' then
- blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
- elsif blit_chunk_cnt_en = '1' and busout_fifo_rdy = '1' then
- if blit_chunk_cnt /= 0 then
+ if STB_O_blit_src = '1' then
+ if blit_chunk_cnt /= 0 and bus_rdy = '1' then
blit_chunk_cnt <= blit_chunk_cnt - 1;
end if;
+ else
+ blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
blit_reset <= RST_I or (blit_request_set and not blit_request);
ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
@@ -652,7 +578,7 @@ proc_scan_addr:
if vga_scan_dma_en2 = '0' then
pixel_cnt <= 0;
front <= host_fb_front;
- elsif STB_O_scan = '1' and busout_fifo_rdy = '1' then
+ elsif STB_O_scan = '1' and bus_rdy = '1' then
if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
pixel_cnt <= pixel_cnt + 1;
else
@@ -666,93 +592,7 @@ proc_scan_addr:
end if;
end process;
----------------------------------------------------------------------------------
-inst_align_src : entity work.align
- GENERIC MAP
- (
- data_width => 64,
- aggregate_size => 8
- )
- PORT MAP
- (
- rst => blit_reset,
- clk => CLK_I,
- ce => blit_src_re,
- eb => '1',
- offset => blit_src_addr,
- din_vld => blit_src_we,
- din => busin_fifo_dout,
- dout_vld => blit_src_reg_vld,
- dout => blit_src_reg,
- byte_en => open
-
- );
-
- blit_src_we <= busin_fifo_dout_vld and CYC_O_blit_src; -- TODO:
- blit_src_re <= not blitfifo_src_full; -- TODO:
-
-proc_blit_src_counter:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if blit_reset = '1' then
- blit_src_row_cnt <= (others => '0');
- blit_src_unaligned <= '0';
- blit_src_first <= '0';
- blit_src_last <= '0';
- blit_src_do_extra2 <= '0';
- if blit_src_addr (2 downto 0) /= "000" then
- blit_src_unaligned <= not blit_const_color_en;
- blit_src_first <= not blit_const_color_en;
- blit_src_do_extra2 <= not blit_const_color_en;
- end if;
- elsif blit_src_re = '1' then
- if blit_src_reg_vld = '1' then
- blit_src_first <= '0';
- if blit_src_row_cnt /= blit_nx then
- blit_src_row_cnt <= blit_src_row_cnt + 1;
- elsif blit_src_do_extra2 = '1' then
- blit_src_do_extra2 <= '0';
- else
- if blit_src_unaligned = '1' then
- blit_src_do_extra2 <= '1';
- end if;
- blit_src_row_cnt <= (others => '0');
- blit_src_first <= blit_src_unaligned;
- end if;
- end if;
- end if;
- end if;
- end process;
-
-inst_blitfifo_src: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE),
- data_width => blitfifo_src_in'length
- )
- PORT MAP
- (
- rst => blit_reset,
- clk => CLK_I,
- we => blitfifo_src_we,
- re => blitfifo_src_re,
- data_w => blitfifo_src_in,
- data_r => blitfifo_src_out,
- fifo_full => blitfifo_src_full,
- fifo_empty => blitfifo_src_empty,
- fifo_afull => open,
- fifo_aempty => open
-
- );
-
- blitfifo_src_we <= (blit_src_reg_vld and not blit_src_first) when blit_const_color_en = '0' else (blit_request and not blit_src_finish);
- blitfifo_src_in <= blit_src_reg when blit_const_color_en = '0' else (blit_const_color & blit_const_color);
- blitfifo_src_re <= blit_dst_re;
-
----------------------------------------------------------------------------------
- ADDR_O_blit_src <= blit_addr_src_0(31 downto 3) & "000" + blit_src_offset;
- blit_src_addr <= blit_addr_src_0(2 downto 0);
+ ADDR_O_blit_src <= blit_addr_src_0 + blit_src_offset;
proc_blit_addr_src:
process(CLK_I)
@@ -764,100 +604,43 @@ proc_blit_addr_src:
blit_src_offset <= (others => '0');
blit_src_off_y <= blit_dimx_src_0;
blit_src_finish <= '0';
- blit_src_do_extra <= '0';
- if blit_src_addr (2 downto 0) /= "000" then
- blit_src_do_extra <= not blit_const_color_en;
- end if;
- elsif blit_src_finish = '0' and ((STB_O_blit_src = '1' and busout_fifo_rdy = '1') or (blit_const_color_en = '1' and blitfifo_src_full = '0')) then
- blit_src_offset <= blit_src_offset + 8;
+ elsif STB_O_blit_src = '1' and bus_rdy = '1' then
if blit_src_cnt_x /= blit_nx then
blit_src_cnt_x <= blit_src_cnt_x + 1;
- elsif blit_src_do_extra = '1' then
- blit_src_do_extra <= '0';
+ blit_src_offset <= blit_src_offset + 8;
else
- if blit_src_unaligned = '1' then
- blit_src_do_extra <= '1';
- end if;
if blit_src_cnt_y /= blit_ny then
- blit_src_cnt_x <= (others => '0');
+ blit_src_cnt_x <= (others => '0');
blit_src_offset <= blit_src_off_y;
blit_src_cnt_y <= blit_src_cnt_y + 1;
blit_src_off_y <= blit_src_off_y + blit_dimx_src_0;
else
blit_src_finish <= '1';
- end if;
+ end if;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-inst_align_dst : entity work.align
- GENERIC MAP
- (
- data_width => 64,
- aggregate_size => 8
- )
- PORT MAP
- (
- rst => blit_reset,
- clk => CLK_I,
- eb => '1',
- ce => blit_dst_re,
- offset => blit_addr_dst(2 downto 0),
- din_vld => blit_dst_we,
- din => blitfifo_src_out,
- dout_vld => blit_dst_reg_vld,
- dout => blit_dst_reg,
- byte_en => blit_dst_reg_be
-
- );
-
- blit_dst_be <= blit_dst_reg_be when blit_dst_first = '1' else
- not blit_dst_reg_be when blit_dst_last = '1' else
- (others => '1');
-
-
- blit_dst_we <= not blitfifo_src_empty;
- blit_dst_re <= CYC_O_blit_dst and busout_fifo_rdy and not blit_dst_last;
- blit_dst_vld <= blit_dst_reg_vld or blit_dst_last;
-
----------------------------------------------------------------------------------
- ADDR_O_blit_dst <= blit_addr_dst(31 downto 3) & "000" + blit_dst_offset;
+ ADDR_O_blit_dst <= blit_addr_dst + blit_dst_offset;
proc_blit_addr_dst:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if blit_reset = '1' then
+ blit_dst_cnt_x <= (others => '0');
blit_dst_cnt_y <= (others => '0');
blit_dst_offset <= (others => '0');
blit_dst_off_y <= blit_dimx_dst;
blit_dst_finish <= '0';
- blit_dst_cnt_x <= (others => '0');
- blit_dst_do_extra <= '0';
- blit_dst_first <= '1';
- blit_dst_last <= '0';
- blit_dst_unaligned <= '0';
- if blit_addr_dst (2 downto 0) /= "000" then
- blit_dst_unaligned <= '1';
- blit_dst_do_extra <= '1';
- end if;
- elsif blit_dst_finish = '0' and (STB_O_blit_dst = '1' and busout_fifo_rdy = '1') then
- blit_dst_first <= blit_dst_last;
- blit_dst_last <= '0';
- blit_dst_offset <= blit_dst_offset + 8;
+ elsif STB_O_blit_dst = '1' and bus_rdy = '1' then
if blit_dst_cnt_x /= blit_nx then
blit_dst_cnt_x <= blit_dst_cnt_x + 1;
- elsif blit_dst_do_extra = '1' then
- blit_dst_do_extra <= '0';
- blit_dst_last <= '1';
+ blit_dst_offset <= blit_dst_offset + 8;
else
- if blit_dst_unaligned = '1' then
- blit_dst_do_extra <= '1';
- end if;
if blit_dst_cnt_y /= blit_ny then
- blit_dst_cnt_x <= (others => '0');
+ blit_dst_cnt_x <= (others => '0');
blit_dst_offset <= blit_dst_off_y;
blit_dst_cnt_y <= blit_dst_cnt_y + 1;
blit_dst_off_y <= blit_dst_off_y + blit_dimx_dst;
@@ -869,7 +652,6 @@ proc_blit_addr_dst:
end if;
end process;
----------------------------------------------------------------------------------
inst_char_gen : entity work.char_gen
GENERIC MAP
(
@@ -1011,8 +793,6 @@ registers_read:
end if;
end process;
- blit_const_color_en <= blit_func_sel(0);
-
registers_write:
process(CLK_I)
begin
@@ -1034,9 +814,6 @@ registers_write:
blit_comb_sel <= (others => '0');
host_fb_front <= X"40000000";
host_fb_back <= X"40010000";
- blit_addr_src_0 <= X"40000000";
- blit_addr_src_1 <= X"40020000";
- blit_addr_dst <= X"40040000";
cg_color <= (X"FF", X"FF", X"FF", X"FF");
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(6 downto 2) is
@@ -1092,7 +869,7 @@ registers_write:
-- sys_blit_descr_src_0
-- 0x20
when "01000" =>
- blit_addr_src_0 <= SDAT_I(31 downto 0);
+ blit_addr_src_0 <= SDAT_I(31 downto 3) & "000";
-- 0x28
when "01010" =>
@@ -1101,7 +878,7 @@ registers_write:
-- sys_blit_descr_src_1
-- 0x30
when "01100" =>
- blit_addr_src_1 <= SDAT_I(31 downto 0);
+ blit_addr_src_1 <= SDAT_I(31 downto 3) & "000";
-- 0x38
when "01110" =>
@@ -1110,12 +887,7 @@ registers_write:
-- sys_blit_descr_dst
-- 0x50
when "10100" =>
- blit_addr_dst <= SDAT_I(31 downto 0);
-
- -- sys_blit_const_color
- -- 0x54
- when "10101" =>
- blit_const_color <= SDAT_I(31 downto 0);
+ blit_addr_dst <= SDAT_I(31 downto 3) & "000";
-- 0x58
when "10110" =>
diff --git a/lib/ac97_ctrl/sim/tb_ac97_wb.fdo b/lib/ac97_ctrl/sim/tb_ac97_wb.fdo
deleted file mode 100644
index bbdc249..0000000
--- a/lib/ac97_ctrl/sim/tb_ac97_wb.fdo
+++ /dev/null
@@ -1,20 +0,0 @@
-## NOTE: Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
-##
-vlib work
-vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit -93 "../../FIFO/src/fifo_sync_dist.vhd"
-vcom -explicit -93 "../../misc/singleshot.vhd"
-vcom -explicit -93 "../src/core/ac_out.vhd"
-vcom -explicit -93 "../src/core/ac_in.vhd"
-vcom -explicit -93 "../src/core/ac_io.vhd"
-vcom -explicit -93 "../src/core/ac97_wb.vhd"
-vcom -explicit -93 "../src/tb_ac97_wb.vhd"
-vsim -t 1ps -lib work tb_ac97_wb
-do {tb_ac97_wb.wdo}
-view wave
-view structure
-view signals
-run 700us
diff --git a/lib/ac97_ctrl/sim/tb_ac97_wb.wdo b/lib/ac97_ctrl/sim/tb_ac97_wb.wdo
deleted file mode 100644
index f7e1885..0000000
--- a/lib/ac97_ctrl/sim/tb_ac97_wb.wdo
+++ /dev/null
@@ -1,77 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ac97_wb/clk_o
-add wave -noupdate -format Logic /tb_ac97_wb/rst_o
-add wave -noupdate -format Logic /tb_ac97_wb/int_i
-add wave -noupdate -format Logic /tb_ac97_wb/cyc_o
-add wave -noupdate -format Logic /tb_ac97_wb/stb_o
-add wave -noupdate -format Logic /tb_ac97_wb/we_o
-add wave -noupdate -format Logic /tb_ac97_wb/ack_i
-add wave -noupdate -format Logic /tb_ac97_wb/mrdy_o
-add wave -noupdate -format Logic /tb_ac97_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_o
-add wave -noupdate -format Logic /tb_ac97_wb/dout_rst
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dout_reg
-add wave -noupdate -format Literal /tb_ac97_wb/dout_cnt
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_bit_clk
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_reset_n
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_out
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_ssync
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_in
-add wave -noupdate -divider UUT
-add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_reg_we
-add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_pending
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_addr
-add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_cmd_we
-add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_tx_pcm_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/stat_reg
-add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_reg_re
-add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_pending
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_addr
-add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_tx_pcm_addr
-add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_rx_pcm_addr
-add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_sync_strobe
-add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_slot_valid
-add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_ready
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_data_start
-add wave -noupdate -format Logic /tb_ac97_wb/clk_o
-add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_status
-add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_frame
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_frame_valid
-add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_tx
-add wave -noupdate -format Literal /tb_ac97_wb/uut/request
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_dout
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_re
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_we
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_full
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_empty
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_data_start
-add wave -noupdate -format Logic /tb_ac97_wb/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_dout
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_re
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_we
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_full
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_empty
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac97_stat
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {200000401 ps} 0} {{Cursor 2} {699514236 ps} 0} {{Cursor 4} {4999959266 ps} 0}
-configure wave -namecolwidth 173
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {699260742 ps} {700038909 ps}
diff --git a/lib/ac97_ctrl/sim/tb_ac_in.fdo b/lib/ac97_ctrl/sim/tb_ac_in.fdo
deleted file mode 100644
index fd7fb1f..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_in.fdo
+++ /dev/null
@@ -1,14 +0,0 @@
-## NOTE: Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
-##
-vlib work
-vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd"
-vcom -explicit -93 "../src/core/ac_out.vhd"
-vcom -explicit -93 "../src/core/ac_in.vhd"
-vcom -explicit -93 "../src/tb_ac_in.vhd"
-vsim -t 1ps -lib work tb_ac_in
-do {tb_ac_in.wdo}
-view wave
-view structure
-view signals
-run 700us
diff --git a/lib/ac97_ctrl/sim/tb_ac_in.wdo b/lib/ac97_ctrl/sim/tb_ac_in.wdo
deleted file mode 100644
index a7d0e35..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_in.wdo
+++ /dev/null
@@ -1,43 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ac_in/uut/rst
-add wave -noupdate -format Logic /tb_ac_in/uut/clk
-add wave -noupdate -format Logic /tb_ac_in/uut/sync_frame
-add wave -noupdate -format Logic /tb_ac_in/uut/sync_status
-add wave -noupdate -divider {AC97 lines}
-add wave -noupdate -format Logic /tb_ac_in/uut/ac_reset
-add wave -noupdate -format Logic /tb_ac_in/uut/ac_bit_clk
-add wave -noupdate -format Logic /tb_ac_in/uut/ac_sdata_in
-add wave -noupdate -format Logic /tb_ac_in/uut/ac_ssync
-add wave -noupdate -divider Debug
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_data
-add wave -noupdate -format Literal /tb_ac_in/uut/pcm_out_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/pcm_out_data
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ac_in/uut/data_array
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/tag
-add wave -noupdate -format Literal /tb_ac_in/uut/sac
-add wave -noupdate -format Literal /tb_ac_in/uut/bitcnt
-add wave -noupdate -format Literal /tb_ac_in/uut/slotcnt
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/rx_reg
-add wave -noupdate -format Logic /tb_ac_in/uut/stat_read
-add wave -noupdate -format Logic /tb_ac_in/uut/host_update
-add wave -noupdate -format Logic /tb_ac_in/uut/slot_end
-add wave -noupdate -format Logic /tb_ac_in/uut/sync_end
-add wave -noupdate -format Logic /tb_ac_in/uut/last_slot
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {53431686 ps} 0} {{Cursor 2} {44308511 ps} 0} {{Cursor 4} {677821715 ps} 0}
-configure wave -namecolwidth 173
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {52190046 ps} {56168939 ps}
diff --git a/lib/ac97_ctrl/sim/tb_ac_io.fdo b/lib/ac97_ctrl/sim/tb_ac_io.fdo
deleted file mode 100644
index 4b0180f..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_io.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-## NOTE: Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
-##
-vlib work
-vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
-vcom -explicit -93 "../src/core/ac_out.vhd"
-vcom -explicit -93 "../src/core/ac_in.vhd"
-vcom -explicit -93 "../src/core/ac_io.vhd"
-vcom -explicit -93 "../src/tb_ac_io.vhd"
-vsim -t 1ps -lib work tb_ac_io
-do {tb_ac_io.wdo}
-view wave
-view structure
-view signals
-run 700us
diff --git a/lib/ac97_ctrl/sim/tb_ac_io.wdo b/lib/ac97_ctrl/sim/tb_ac_io.wdo
deleted file mode 100644
index b445bdb..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_io.wdo
+++ /dev/null
@@ -1,51 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ac_io/uut/rst
-add wave -noupdate -format Logic /tb_ac_io/uut/clk
-add wave -noupdate -format Logic /tb_ac_io/uut/ready
-add wave -noupdate -format Literal /tb_ac_io/uut/slot_valid
-add wave -noupdate -format Logic /tb_ac_io/uut/sync_strobe
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_data
-add wave -noupdate -format Literal /tb_ac_io/uut/rx_pcm_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/rx_pcm_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_data
-add wave -noupdate -format Logic /tb_ac_io/uut/cmd_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_data
-add wave -noupdate -format Logic /tb_ac_io/uut/tx_pcm_we
-add wave -noupdate -divider {AC97 lines}
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_in
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_bit_clk
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_reset_n
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_out
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_ssync
-add wave -noupdate -divider Debug
-add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_in/stat_read
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/rx_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_out/tx_reg
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/bitcnt
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/sac
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/tag
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/data_array
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/bitcnt
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slotcnt
-add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_out/ssync
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slot_valid
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {0 ps} 0} {{Cursor 2} {292930000 ps} 0} {{Cursor 4} {4999959266 ps} 0}
-configure wave -namecolwidth 173
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {735 us}
diff --git a/lib/ac97_ctrl/sim/tb_ac_out.fdo b/lib/ac97_ctrl/sim/tb_ac_out.fdo
deleted file mode 100644
index ac9d3c4..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_out.fdo
+++ /dev/null
@@ -1,13 +0,0 @@
-## NOTE: Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
-##
-vlib work
-vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd"
-vcom -explicit -93 "../src/core/ac_out.vhd"
-vcom -explicit -93 "../src/tb_ac_out.vhd"
-vsim -t 1ps -lib work tb_ac_out
-do {tb_ac_out.wdo}
-view wave
-view structure
-view signals
-run 600us
diff --git a/lib/ac97_ctrl/sim/tb_ac_out.wdo b/lib/ac97_ctrl/sim/tb_ac_out.wdo
deleted file mode 100644
index b9d9a25..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_out.wdo
+++ /dev/null
@@ -1,41 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ac_out/rst
-add wave -noupdate -format Logic /tb_ac_out/clk
-add wave -noupdate -format Logic /tb_ac_out/ce
-add wave -noupdate -divider {Host hand shake}
-add wave -noupdate -format Logic /tb_ac_out/sync_tx
-add wave -noupdate -divider {Command I/F}
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_data
-add wave -noupdate -format Logic /tb_ac_out/uut/cmd_we
-add wave -noupdate -divider {PCM I/F}
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_data
-add wave -noupdate -format Logic /tb_ac_out/pcm_in_we
-add wave -noupdate -divider {AC97 I/F}
-add wave -noupdate -format Logic /tb_ac_out/ac_bit_clk
-add wave -noupdate -format Logic /tb_ac_out/ac_reset
-add wave -noupdate -format Logic /tb_ac_out/ac_sdata_out
-add wave -noupdate -format Logic /tb_ac_out/ac_ssync
-add wave -noupdate -divider Debug
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/uut/tx_reg
-add wave -noupdate -format Literal /tb_ac_out/uut/sac
-add wave -noupdate -format Literal /tb_ac_out/uut/bitcnt
-add wave -noupdate -format Literal /tb_ac_out/uut/slotcnt
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {544839100 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {532851785 ps} {556826415 ps}
diff --git a/lib/ac97_ctrl/src/core/ac97_wb.vhd b/lib/ac97_ctrl/src/core/ac97_wb.vhd
deleted file mode 100644
index 1b4fb57..0000000
--- a/lib/ac97_ctrl/src/core/ac97_wb.vhd
+++ /dev/null
@@ -1,330 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY ac97_wb IS
- Generic
- (
- fifo_depth : natural := 8
- );
- Port
- (
- -- J-Bus domain
- CLK_I : in STD_LOGIC;
- RST_I : in STD_LOGIC;
- CYC_I : in STD_LOGIC;
- STB_I : in STD_LOGIC;
- WE_I : in STD_LOGIC;
- ACK_O : out STD_LOGIC;
- SRDY_O : out STD_LOGIC;
- MRDY_I : in STD_LOGIC;
- ADDR_I : in unsigned(31 downto 0);
- DAT_I : in unsigned(31 downto 0);
- DAT_O : out unsigned(31 downto 0);
- INT_O : out STD_LOGIC;
-
- -- AC97 domain
- ac97_sdata_in : in std_logic;
- ac97_bit_clk : in std_logic;
- ac97_reset_n : out std_logic;
- ac97_sdata_out : out std_logic;
- ac97_ssync : out std_logic
- );
-END ac97_wb;
-
-ARCHITECTURE behavior OF ac97_wb IS
-
- constant ac_data_width : natural := 20;
- constant pcm_data_width : natural := 18;
- constant stat_data_width : natural := 16;
- signal cmd_reg_we : std_logic;
- signal cmd_pending : std_logic;
- signal ac_cmd_data : unsigned(ac_data_width-1 downto 0);
- signal ac_cmd_addr : unsigned(ac_data_width-1 downto 0);
- signal ac_cmd_we : std_logic;
- signal ac_tx_pcm_we : std_logic;
-
- signal stat_reg : unsigned(stat_data_width-1 downto 0);
- signal stat_reg_re : std_logic;
- signal stat_valid : std_logic;
- signal stat_pending : std_logic;
- signal ac_stat_data : unsigned(ac_data_width-1 downto 0);
- signal ac_stat_addr : unsigned(ac_data_width-1 downto 0);
- signal ac_stat_read : std_logic;
- signal ac_stat_valid : std_logic;
-
- signal ac_tx_pcm_data : unsigned(ac_data_width-1 downto 0);
- signal ac_tx_pcm_addr : unsigned (3 downto 0);
- signal ac_rx_pcm_data : unsigned(ac_data_width-1 downto 0);
- signal ac_rx_pcm_addr : unsigned (3 downto 0);
- signal ac_sync_strobe : unsigned(0 to 2);
- signal ac_slot_valid : unsigned(0 to 12);
- signal ac_ready : std_logic;
- signal rx_frame_valid : std_logic;
- signal sync_frame : std_logic;
- signal sync_tx : std_logic;
- signal sync_status : std_logic;
- signal request : unsigned(3 to 12);
-
- signal tx_data_start : std_logic;
- signal tx_fifo_din : unsigned(pcm_data_width-1 downto 0);
- signal tx_fifo_dout : unsigned(pcm_data_width-1 downto 0);
- signal tx_fifo_re : std_logic;
- signal tx_fifo_we : std_logic;
- signal tx_fifo_full : std_logic;
- signal tx_fifo_empty : std_logic;
- signal tx_fifo_almost_full : std_logic;
- signal tx_fifo_almost_empty : std_logic;
-
- signal rx_data_irq : std_logic;
- signal rx_data_ack : std_logic;
-
- signal ac97_stat : unsigned(31 downto 0);
- signal addr_reg : unsigned(31 downto 0);
- signal data_reg : unsigned(31 downto 0);
- signal int_en_frame_sync : std_logic;
- signal int_en_rx : std_logic;
- signal int_en_tx : std_logic;
- signal rx_en : std_logic;
- signal tx_en : std_logic;
- signal rx_fifo_rst : std_logic;
- signal tx_fifo_rst : std_logic;
-
- function GetRequest(slot1 : unsigned) return unsigned is
- variable res : unsigned(3 to 12);
- begin
- res := (others => '0');
- for i in res'range loop
- res(i) := not slot1(14-i);
- end loop;
- return res;
-
- end GetRequest;
-
- type ac_state_t is (reset, idle, pcm_3, pcm_4);
- signal rx_state, rx_state_n : ac_state_t;
-
-begin
-
- SRDY_O <= CYC_I;
- INT_O <= (rx_data_irq and int_en_rx) or (not tx_fifo_full and int_en_tx) or (sync_frame and int_en_frame_sync) ;
-
- rx_frame_valid <= ac_slot_valid(0);
- sync_frame <= ac_sync_strobe(0);
- sync_status <= ac_sync_strobe(1);
- sync_tx <= ac_sync_strobe(2);
- request <= GetRequest(ac_stat_addr);
-
- ac_stat_read <= not addr_reg(9);
- ac_stat_valid <= '1' when (sync_status = '1' and ac_slot_valid(0 to 2) = "111") else '0';
- ac97_stat <= ac_ready & '0' & X"00000" & '0' & int_en_rx & int_en_tx & int_en_frame_sync & '0' & tx_fifo_full & rx_data_irq & tx_fifo_almost_full & stat_valid & cmd_pending;
-
-command_logic:
- process (CLK_I)
- begin
-
- if rising_edge(CLK_I) then
- ac_cmd_we <= '0';
- if RST_I = '1' then
- cmd_pending <= '0';
- elsif cmd_reg_we = '1' and cmd_pending = '0' then
- cmd_pending <= '1';
- elsif (rx_frame_valid and sync_tx) = '1' and cmd_pending = '1' then
- ac_cmd_we <= '1';
- cmd_pending <= '0';
- end if;
- end if;
- end process;
-
-status_logic:
- process (CLK_I)
- begin
-
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- stat_pending <= '0';
- elsif cmd_reg_we = '1' and cmd_pending = '0' then
- stat_pending <= ac_stat_read;
- elsif ac_stat_valid = '1' then
- stat_pending <= '0';
- end if;
- end if;
- end process;
-
-command_register:
- process (CLK_I)
- begin
- if rising_edge(CLK_I) then
- if cmd_reg_we = '1' and cmd_pending = '0' then
- ac_cmd_addr <= ac_stat_read & addr_reg(8 downto 2) & X"000";
- ac_cmd_data <= data_reg(stat_data_width-1 downto 0) & X"0";
- end if;
- end if;
- end process;
-
-status_register:
- process (CLK_I)
- begin
-
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- stat_valid <= '0';
- elsif stat_pending = '1' and ac_stat_valid = '1' then
- stat_reg <= ac_stat_data(ac_data_width-1 downto ac_data_width-stat_data_width);
- stat_valid <= '1';
- elsif stat_reg_re = '1' then
- stat_valid <= '0';
- end if;
- end if;
- end process;
-
- -- Instantiate synchronous FIFO
-inst_tx_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => fifo_depth,
- data_width => pcm_data_width,
- almost_full_thresh => 90*(2**fifo_depth)/100,
- almost_empty_thresh => 10*(2**fifo_depth)/100
- )
- PORT MAP
- (
- rst => tx_fifo_rst,
- clk => CLK_I,
- we => tx_fifo_we,
- re => tx_fifo_re,
- fifo_full => tx_fifo_full,
- fifo_empty => tx_fifo_empty,
- fifo_afull => tx_fifo_almost_full,
- fifo_aempty => tx_fifo_almost_empty,
- data_w => tx_fifo_din,
- data_r => tx_fifo_dout
- );
- tx_fifo_rst <= not tx_en or RST_I;
-
-tx_logic:
- process (CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' or tx_en = '0' then
- ac_tx_pcm_addr <= "0011";
- tx_data_start <= '0';
- elsif sync_tx = '1' and (request(3) and request(4)) = '1' then
- ac_tx_pcm_addr <= "0011";
- tx_data_start <= '1';
- elsif ac_tx_pcm_addr /= "0100" then
- ac_tx_pcm_addr <= ac_tx_pcm_addr + 1;
- else
- tx_data_start <= '0';
- end if;
- end if;
- end process;
-
- ac_tx_pcm_we <= not tx_fifo_empty and tx_data_start;
- tx_fifo_re <= ac_tx_pcm_we;
-
- tx_fifo_din <= data_reg(pcm_data_width-1 downto 0);
-
- ac_rx_pcm_addr <= addr_reg(5 downto 2);
-
-rx_logic:
- process (CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- rx_data_irq <= '0';
- elsif rx_frame_valid = '1' and sync_frame = '1' then
- if ac_slot_valid(3) = '1' and ac_slot_valid(4) = '1' then
- rx_data_irq <= rx_en;
- end if;
- elsif rx_data_ack = '1' then
- rx_data_irq <= '0';
- end if;
- end if;
- end process;
-
-inst_ac_io : entity work.ac_io
- PORT MAP
- (
- rst => RST_I,
- clk => CLK_I,
- ready => ac_ready,
- sync_strobe => ac_sync_strobe,
- slot_valid => ac_slot_valid,
- stat_addr => ac_stat_addr,
- stat_data => ac_stat_data,
- rx_pcm_addr => ac_rx_pcm_addr,
- rx_pcm_data => ac_rx_pcm_data,
- cmd_addr => ac_cmd_addr,
- cmd_data => ac_cmd_data,
- cmd_we => ac_cmd_we,
- tx_pcm_addr => ac_tx_pcm_addr,
- tx_pcm_data => ac_tx_pcm_data,
- tx_pcm_we => ac_tx_pcm_we,
- ac_sdata_in => ac97_sdata_in,
- ac_bit_clk => ac97_bit_clk,
- ac_reset_n => ac97_reset_n,
- ac_sdata_out => ac97_sdata_out,
- ac_ssync => ac97_ssync
- );
-
- ac_tx_pcm_data <= tx_fifo_dout & (ac_data_width-pcm_data_width-1 downto 0 => '0');
-
-slave_data_out:
- process (CLK_I)
- begin
-
- if rising_edge(CLK_I) then
- tx_fifo_we <= '0';
- stat_reg_re <= '0';
- cmd_reg_we <= '0';
- rx_data_ack <= '0';
- ACK_O <= '0';
- if RST_I = '1' then
- addr_reg <= (others => '0');
- int_en_frame_sync <= '0';
- int_en_rx <= '0';
- int_en_tx <= '0';
- tx_en <= '0';
- rx_en <= '0';
- else
--- DAT_O <= (others => '-');
-
- if (STB_I and CYC_I) = '1' then
- ACK_O <= not WE_I;
-
- case ADDR_I(11 downto 10) is
-
- when "00" =>
- DAT_O <= ac97_stat;
- if WE_I = '1' then
- int_en_frame_sync <= DAT_I(0);
- int_en_tx <= DAT_I(1);
- int_en_rx <= DAT_I(2);
- tx_en <= DAT_I(4);
- rx_en <= DAT_I(5);
- end if;
- when "01" =>
- addr_reg <= ADDR_I;
- data_reg <= DAT_I;
- stat_reg_re <= not WE_I;
- cmd_reg_we <= WE_I;
- DAT_O <= (31 downto stat_data_width => '0') & stat_reg;
-
- when "10" =>
- rx_data_ack <= not WE_I;
- addr_reg <= ADDR_I;
- data_reg <= DAT_I;
- tx_fifo_we <= WE_I;
- DAT_O <= (31 downto pcm_data_width => ac_rx_pcm_data(ac_data_width-1)) & ac_rx_pcm_data(ac_data_width-1 downto ac_data_width-pcm_data_width);
-
- when others => null;
-
- end case;
- end if;
- end if;
- end if;
-
- end process;
-
-end behavior;
diff --git a/lib/ac97_ctrl/src/core/ac_in.vhd b/lib/ac97_ctrl/src/core/ac_in.vhd
deleted file mode 100644
index a072a9b..0000000
--- a/lib/ac97_ctrl/src/core/ac_in.vhd
+++ /dev/null
@@ -1,309 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 08:27:43 08/26/2006
--- Design Name:
--- Module Name: ac_out - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ac_in is
- Port (
- rst : in std_logic;
- clk : in std_logic;
- sync_frame : out std_logic;
- sync_status : out std_logic;
- slot_valid : out unsigned(0 to 12);
- stat_addr : out unsigned (19 downto 0);
- stat_data : out unsigned (19 downto 0);
- pcm_out_addr : in unsigned (3 downto 0);
- pcm_out_data : out unsigned (19 downto 0);
- ac_reset : in std_logic;
- ac_bit_clk : in std_logic;
- ac_sdata_in : in std_logic;
- ac_ssync : in std_logic
- );
-end ac_in;
-
-architecture Behavioral of ac_in is
-
-------------------------------------------------------------------
-COMPONENT singleshot
-GENERIC (mode : integer);
-PORT(
- rst : IN std_logic;
- clk : IN std_logic;
- input : IN std_logic;
- output : OUT std_logic
- );
-END COMPONENT;
-
-------------------------------------------------------------------
-type sac_t is (ac_idle, ac_tag, ac_data);
-subtype bitcnt_t is integer range 0 to 19;
-subtype slotcnt_t is integer range 0 to 12;
-subtype slot_valid_t is UNSIGNED(0 to 12);
-subtype tag_t is UNSIGNED(15 downto 0);
-subtype slot_t is UNSIGNED(19 downto 0);
-type slot_array_t is array (natural range <>) of slot_t;
-
-signal data_array : slot_array_t (1 to 12);
-signal tag : tag_t;
-
-signal sac, snac : sac_t;
-signal bitcnt : bitcnt_t;
-signal bitcnt_rst, bitcnt_en : STD_LOGIC;
-signal slotcnt : slotcnt_t;
-signal slotcnt_rst, slotcnt_en : STD_LOGIC;
-
-signal rx_reg : slot_t;
-signal stat_read, host_update : STD_LOGIC;
-signal sync_end, slot_end, last_slot, start_of_frame : STD_LOGIC;
-
-------------------------------------------------------------------
-function GetSlotValid(data : tag_t) return slot_valid_t is
-variable res : slot_valid_t := (others => '0');
-begin
- res := (others => '0');
- for i in slot_valid_t'range loop
- res(i) := data(data'left-i);
- end loop;
- return res;
-
-end GetSlotValid;
-
-------------------------------------------------------------------
-begin
-
--------------------------------------------------------------
--- proc_status_flags
--------------------------------------------------------------
-proc_status_flags:
-process (rst, clk, host_update, tag, data_array)
-begin
- if rising_edge(clk) then
- sync_status <= '0';
- if rst = '1' then
- slot_valid <= (others => '0');
- stat_addr <= (others => '0');
- stat_data <= (others => '0');
- elsif host_update = '1' then
- sync_status <= '1';
- slot_valid <= GetSlotValid(tag);
- stat_addr <= data_array(1);
- stat_data <= data_array(2);
- end if;
- end if;
-end process;
-
--------------------------------------------------------------
--- proc_pcm_data
--------------------------------------------------------------
-proc_pcm_data:
-process (clk, pcm_out_addr, data_array)
-variable slot_id : integer range 0 to 12;
-begin
- pcm_out_data <= (others => '-');
- slot_id := to_integer(pcm_out_addr);
- if (slot_id > 2) then
- pcm_out_data <= data_array(slot_id);
- end if;
-end process;
-
--------------------------------------------------------------
--- proc_read_data
--------------------------------------------------------------
-proc_read_data :
-process (ac_reset, ac_bit_clk, slot_end, slotcnt)
-begin
-
- if ac_reset = '1' then
- stat_read <= '0';
- elsif rising_edge(ac_bit_clk) then
- stat_read <= '0';
- if slot_end = '1' and slotcnt /= 0 then
- data_array(slotcnt) <= rx_reg;
- if slotcnt = 2 then
- stat_read <= '1';
- end if;
- end if;
- end if;
-end process;
-
--------------------------------------------------------------
--- proc_read_stat
--------------------------------------------------------------
-proc_read_tag :
-process (ac_reset, ac_bit_clk, sync_end)
-begin
-
- if ac_reset = '1' then
- tag <= (others => '0');
- elsif rising_edge(ac_bit_clk) then
- if sync_end = '1' then
- tag <= rx_reg(15 downto 0);
- end if;
- end if;
-
-end process;
-
--------------------------------------------------------------
--- proc_slot_count
--------------------------------------------------------------
-proc_slot_count:
-process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
-begin
- if rising_edge(ac_bit_clk) then
- if slotcnt_rst = '1' then
- slotcnt <= slotcnt_t'low;
- elsif slotcnt_en = '1' then
- if slotcnt /= slotcnt_t'high then
- slotcnt <= slotcnt + 1;
- else
- slotcnt <= slotcnt_t'low;
- end if;
- end if;
- end if;
-end process;
-
--------------------------------------------------------------
--- proc_bit_count
--------------------------------------------------------------
-proc_bit_count:
-process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
-begin
- if rising_edge(ac_bit_clk) then
- if bitcnt_rst = '1' then
- bitcnt <= bitcnt_t'low;
- elsif bitcnt_en = '1' then
- if bitcnt /= bitcnt_t'high then
- bitcnt <= bitcnt + 1;
- else
- bitcnt <= bitcnt_t'low;
- end if;
- end if;
- end if;
-end process;
-
-------------------------------------------------------------------
-proc_ac_fsm:
-process (bitcnt, slotcnt, sac, ac_ssync)
-begin
- snac <= sac;
- bitcnt_rst <= '0';
- bitcnt_en <= '1';
- slotcnt_rst <= '0';
- slotcnt_en <= '0';
- slot_end <= '0';
- sync_end <= '0';
- last_slot <= '0';
- start_of_frame <= '0';
-
- if bitcnt = 19 then
- slot_end <= '1';
- end if;
- if slotcnt = 12 and bitcnt = 19 then
- last_slot <= '1';
- end if;
-
- case sac is
-
- when ac_idle =>
- bitcnt_rst <= '1';
- slotcnt_rst <= '1';
- if (ac_ssync = '1') then
- snac <= ac_tag;
- end if;
-
- when ac_tag =>
- if (bitcnt = 0) then
- start_of_frame <= '1';
- elsif (bitcnt = 15) then
- slotcnt_en <= '1';
- bitcnt_rst <= '1';
- sync_end <= '1';
- if (ac_ssync = '0') then
- snac <= ac_data;
- else
- snac <= ac_idle;
- end if;
- end if;
-
- when ac_data =>
- if bitcnt = 19 then
- slotcnt_en <= '1';
- if slotcnt = 12 then
- slotcnt_rst <= '1';
- snac <= ac_tag;
- end if;
- end if;
- when others => null;
- end case;
-end process;
-
-proc_ac_fsm_next:
-process (ac_reset, ac_bit_clk, snac)
-begin
- if ac_reset = '1' then
- sac <= ac_idle;
- elsif rising_edge(ac_bit_clk) then
- sac <= snac;
- end if;
-end process;
-
--------------------------------------------------------------
--- Receive Shift Register
--------------------------------------------------------------
-process (ac_reset, ac_bit_clk, ac_sdata_in)
-begin
- if ac_reset = '1' then
- rx_reg <= (others => '0');
- elsif falling_edge(ac_bit_clk) then
- rx_reg <= rx_reg(rx_reg'left-1 downto 0) & ac_sdata_in;
- end if;
-end process;
-
-------------------------------------------------------------------
-singleshot_inst1: singleshot
-GENERIC MAP (
- mode => 0)
-PORT MAP(
- rst => rst,
- clk => clk,
- input => stat_read,
- output => host_update
-);
-
-singleshot_inst2: singleshot
-GENERIC MAP (
- mode => 1)
-PORT MAP(
- rst => rst,
- clk => clk,
- input => start_of_frame,
- output => sync_frame
-);
-
--------------------------------------------------------------
-
-end Behavioral;
-
diff --git a/lib/ac97_ctrl/src/core/ac_io.vhd b/lib/ac97_ctrl/src/core/ac_io.vhd
deleted file mode 100644
index 211a5ef..0000000
--- a/lib/ac97_ctrl/src/core/ac_io.vhd
+++ /dev/null
@@ -1,189 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 18:29:55 08/26/2006
--- Design Name:
--- Module Name: ac_io - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ac_io is
- Port
- (
- rst : in std_logic;
- clk : in std_logic;
- ready : out std_logic;
- sync_strobe : out unsigned(0 to 2);
- slot_valid : out unsigned(0 to 12);
- stat_addr : out unsigned (19 downto 0);
- stat_data : out unsigned (19 downto 0);
- rx_pcm_addr : in unsigned (3 downto 0);
- rx_pcm_data : out unsigned (19 downto 0);
- cmd_addr : in unsigned(19 downto 0);
- cmd_data : in unsigned(19 downto 0);
- cmd_we : in std_logic;
- tx_pcm_addr : in unsigned(3 downto 0);
- tx_pcm_data : in unsigned(19 downto 0);
- tx_pcm_we : in std_logic;
- ac_sdata_in : in std_logic;
- ac_bit_clk : in std_logic;
- ac_reset_n : out std_logic;
- ac_sdata_out : out std_logic;
- ac_ssync : out std_logic
- );
-end ac_io;
-
-architecture Behavioral of ac_io is
-
- COMPONENT ac_in
- Port
- (
- rst : in std_logic;
- clk : in std_logic;
- sync_frame : out std_logic;
- sync_status : out std_logic;
- slot_valid : out unsigned(0 to 12);
- stat_addr : out unsigned (19 downto 0);
- stat_data : out unsigned (19 downto 0);
- pcm_out_addr : in unsigned (3 downto 0);
- pcm_out_data : out unsigned (19 downto 0);
- ac_reset : in std_logic;
- ac_bit_clk : in std_logic;
- ac_sdata_in : in std_logic;
- ac_ssync : in std_logic
- );
- END COMPONENT;
-
- COMPONENT ac_out
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- sync_tx : out std_logic;
- cmd_addr : in unsigned(19 downto 0);
- cmd_data : in unsigned(19 downto 0);
- cmd_we : in std_logic;
- pcm_in_addr : in unsigned(3 downto 0);
- pcm_in_data : in unsigned(19 downto 0);
- pcm_in_we : in std_logic;
- ac_bit_clk : in std_logic;
- ac_reset : in std_logic;
- ac_sdata_out : out std_logic;
- ac_ssync : out std_logic
- );
- END COMPONENT;
-
- SIGNAL ac_reset : std_logic;
- SIGNAL ssync_rx : std_logic;
- SIGNAL ssync_tx : std_logic;
- SIGNAL sync_frame : std_logic;
- SIGNAL sync_status : std_logic;
- SIGNAL sync_tx : std_logic;
-
-begin
-
-inst_ac_in: ac_in
- PORT MAP
- (
- rst => rst,
- clk => clk,
- sync_frame => sync_frame,
- sync_status => sync_status,
- slot_valid => slot_valid,
- stat_addr => stat_addr,
- stat_data => stat_data,
- pcm_out_addr => rx_pcm_addr,
- pcm_out_data => rx_pcm_data,
- ac_reset => ac_reset,
- ac_bit_clk => ac_bit_clk,
- ac_sdata_in => ac_sdata_in,
- ac_ssync => ssync_rx
- );
-
-inst_ac_out: ac_out
- PORT MAP
- (
- rst => rst,
- clk => clk,
- sync_tx => sync_tx,
- cmd_addr => cmd_addr,
- cmd_data => cmd_data,
- cmd_we => cmd_we,
- pcm_in_addr => tx_pcm_addr,
- pcm_in_data => tx_pcm_data,
- pcm_in_we => tx_pcm_we,
- ac_reset => ac_reset,
- ac_bit_clk => ac_bit_clk,
- ac_sdata_out => ac_sdata_out,
- ac_ssync => ssync_tx
- );
-
- ------------------------------------------------------------------
- ready <= not ac_reset;
- ac_ssync <= ssync_tx;
- ssync_rx <= ssync_tx;
- sync_strobe <= sync_frame & sync_status & sync_tx;
-
- ------------------------------------------------------------------
- proc_reset_gen:
- process (rst, clk, ac_bit_clk)
- type rstate_t is (s0, s1);
- variable rstate, rstaten : rstate_t;
- subtype cnt_t is integer range 0 to 999;
- variable cnt : cnt_t;
- begin
- if rising_edge(clk) then
- if rst = '1' then
- rstate := s0;
- cnt := cnt_t'high;
- ac_reset <= '1';
- ac_reset_n <= '0';
- else
- rstaten := rstate;
- case rstate is
- when s0 =>
- if cnt /= 0 then
- cnt := cnt - 1;
- else
- ac_reset_n <= '1';
- if ac_bit_clk = '1' then
- rstaten := s1;
- cnt := cnt_t'high;
- end if;
- end if;
-
- when s1 =>
- if cnt /= 0 then
- cnt := cnt - 1;
- else
- ac_reset <= '0';
- end if;
- end case;
- rstate := rstaten;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
-
-end Behavioral;
-
diff --git a/lib/ac97_ctrl/src/core/ac_out.vhd b/lib/ac97_ctrl/src/core/ac_out.vhd
deleted file mode 100644
index a770495..0000000
--- a/lib/ac97_ctrl/src/core/ac_out.vhd
+++ /dev/null
@@ -1,276 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 15:41:12 06/05/2007
--- Design Name:
--- Module Name: ac_out - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ac_out is
- Port (
- rst : in std_logic;
- clk : in std_logic;
- sync_tx : out std_logic;
- cmd_addr : in unsigned (19 downto 0);
- cmd_data : in unsigned (19 downto 0);
- cmd_we : in std_logic;
- pcm_in_addr : in unsigned (3 downto 0);
- pcm_in_data : in unsigned (19 downto 0);
- pcm_in_we : in std_logic;
- ac_reset : in std_logic;
- ac_bit_clk : in std_logic;
- ac_sdata_out : out std_logic;
- ac_ssync : out std_logic
- );
-end ac_out;
-
-architecture Behavioral of ac_out is
-
-------------------------------------------------------------------
-COMPONENT singleshot
-GENERIC (mode : integer);
-PORT(
- rst : IN std_logic;
- clk : IN std_logic;
- input : IN std_logic;
- output : OUT std_logic
- );
-END COMPONENT;
-
-------------------------------------------------------------------
-subtype tag_t is UNSIGNED(15 downto 0);
-subtype slot_valid_t is UNSIGNED(1 to 12);
-signal slot_valid : slot_valid_t;
-subtype slot_t is UNSIGNED(19 downto 0);
-type slot_array_t is array (natural range <>) of slot_t;
-signal data_array : slot_array_t (1 to 12);
-
signal tx_reg : UNSIGNED(19 downto 0);
-signal last_slot, ssync : STD_LOGIC;
-
-type sac_t is (ac_idle, ac_tag, ac_data);
-signal sac, snac : sac_t;
-
-subtype bitcnt_t is integer range 0 to 19;
-subtype slotcnt_t is integer range 0 to 12;
-
-signal bitcnt : bitcnt_t;
-signal bitcnt_rst, bitcnt_en : STD_LOGIC;
-signal slotcnt : slotcnt_t;
-signal slotcnt_rst, slotcnt_en : STD_LOGIC;
-
-signal slot_start : STD_LOGIC;
-
-------------------------------------------------------------------
-function CreateTag(slot_valid : slot_valid_t) return tag_t is
-variable tag : tag_t := (others => '0');
-begin
-
tag := (others => '0');
- for i in slot_valid_t'range loop
- tag(15-i) := slot_valid(i);
- if slot_valid(i) = '1' then
- tag(15) := '1';
- end if;
- end loop;
- tag(0) := '0'; -- ID0
- tag(1) := '0'; -- ID1
- tag(2) := '0'; -- Reserved
--- tag(15) := '1'; -- Frame is valid
- return tag;
-
-end CreateTag;
-
-begin
-
-------------------------------------------------------------------
-proc_slot_reg:
-process (clk, cmd_addr, cmd_data, cmd_we, pcm_in_data, pcm_in_we, pcm_in_addr, last_slot)
-variable slot_id : integer range 0 to 12;
-begin
- slot_id := to_integer(pcm_in_addr);
- if rising_edge(clk) then
- if rst = '1' then
- for i in data_array'range(1) loop
- data_array(i) <= (others => '0');
- end loop;
- slot_valid <= (others => '0');
- elsif last_slot = '1' then
- slot_valid <= (others => '0');
- else
- if cmd_we = '1' then
- slot_valid(1) <= '1';
- slot_valid(2) <= '1';
- data_array(1) <= cmd_addr;
- data_array(2) <= cmd_data;
- end if;
- if pcm_in_we = '1' then
- if (slot_id > 2) then
- data_array(slot_id) <= pcm_in_data;
- slot_valid(slot_id) <= '1';
- end if;
- end if;
- end if;
- end if;
-end process;
-
--------------------------------------------------------------
--- proc_slot_count
--------------------------------------------------------------
-proc_slot_count:
-process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
-begin
- if rising_edge(ac_bit_clk) then
- if slotcnt_rst = '1' then
- slotcnt <= slotcnt_t'low;
- elsif slotcnt_en = '1' then
- if slotcnt /= slotcnt_t'high then
- slotcnt <= slotcnt + 1;
- else
- slotcnt <= slotcnt_t'low;
- end if;
- end if;
- end if;
-end process;
-
-------------------------------------------------------------------
--- proc_bit_count
-------------------------------------------------------------------
-proc_bit_count:
-process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
-begin
- if rising_edge(ac_bit_clk) then
- if bitcnt_rst = '1' then
- bitcnt <= bitcnt_t'low;
- elsif bitcnt_en = '1' then
- if bitcnt /= bitcnt_t'high then
- bitcnt <= bitcnt + 1;
- else
- bitcnt <= bitcnt_t'low;
- end if;
- end if;
- end if;
-end process;
-
-------------------------------------------------------------------
-proc_ac_fsm:
-process (bitcnt, slotcnt, sac)
-begin
- snac <= sac;
- bitcnt_rst <= '0';
- bitcnt_en <= '1';
- slotcnt_rst <= '0';
- slotcnt_en <= '0';
- slot_start <= '0';
- ssync <= '0';
-
- if bitcnt = 0 then
- slot_start <= '1';
- end if;
-
- case sac is
-
- when ac_idle =>
- bitcnt_rst <= '1';
- slotcnt_rst <= '1';
- snac <= ac_tag;
-
- when ac_tag =>
- ssync <= '1';
- if (bitcnt = 15) then
- slotcnt_en <= '1';
- bitcnt_rst <= '1';
- snac <= ac_data;
- end if;
-
- when ac_data =>
- if bitcnt = 19 then
- slotcnt_en <= '1';
- if slotcnt = 12 then
- slotcnt_rst <= '1';
- snac <= ac_tag;
- end if;
- end if;
- when others => null;
- end case;
-end process;
-
-proc_ac_fsm_next:
-process (ac_reset, ac_bit_clk, snac)
-begin
- if ac_reset = '1' then
- sac <= ac_idle;
- elsif rising_edge(ac_bit_clk) then
- sac <= snac;
- end if;
-end process;
-
-------------------------------------------------------------------
-proc_tx_shift_reg:
-process (ac_reset, ac_bit_clk, tx_reg, ssync, slot_valid, data_array)
-begin
-
- if ac_reset = '1' then
- tx_reg <= (others => '0');
- elsif rising_edge(ac_bit_clk) then
- last_slot <= '0';
- if slot_start = '1' then
- if ssync = '1' then
- tx_reg <= CreateTag(slot_valid) & "0000";
- else
- if slotcnt /= 0 then
- tx_reg <= data_array(slotcnt);
- if slotcnt = 12 then
- last_slot <= '1';
- end if;
- end if;
- end if;
- else
- tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '0';
- end if;
- end if;
-end process;
-
-------------------------------------------------------------------
-proc_ac_sync_out:
-process (ac_reset, ac_bit_clk, ssync, tx_reg)
-begin
- if ac_reset = '1' then
- ac_ssync <= '0';
- ac_sdata_out <= '0';
- elsif rising_edge(ac_bit_clk) then
- ac_ssync <= ssync;
- ac_sdata_out <= tx_reg(tx_reg'left);
- end if;
-end process;
-
-------------------------------------------------------------------
-singleshot_inst1: singleshot
-GENERIC MAP (
- mode => 0)
-PORT MAP(
- rst => rst,
- clk => clk,
- input => last_slot,
- output => sync_tx
-);
-
-end Behavioral;
diff --git a/lib/ac97_ctrl/src/tb_ac97_wb.vhd b/lib/ac97_ctrl/src/tb_ac97_wb.vhd
deleted file mode 100644
index 7ab47a4..0000000
--- a/lib/ac97_ctrl/src/tb_ac97_wb.vhd
+++ /dev/null
@@ -1,152 +0,0 @@
-
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:33:47 06/05/2007
--- Design Name: eval_ac
--- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
--- Project Name: ac_out
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: ac_out
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_ac97_wb IS
-END tb_ac97_wb;
-
-ARCHITECTURE behavior OF tb_ac97_wb IS
-
- constant SYS_CLK_PERIOD : time := 10 ns;
- CONSTANT BIT_CLK_PERIOD : time := 100 ns;
--- constant BIT_CLK_PERIOD : time := 81.38 ns;
-
- signal CLK_O : std_logic := '1';
- signal RST_O : std_logic := '1';
- signal CYC_O : std_logic := '0';
- signal STB_O : std_logic := '0';
- signal WE_O : std_logic := '0';
- signal ACK_I : std_logic;
- signal MRDY_O : std_logic := '1';
- signal SRDY_I : std_logic;
- signal INT_I : std_logic;
- signal ADDR_O : unsigned(31 downto 0) := (others => '-');
- signal DAT_I : unsigned(31 downto 0);
- signal DAT_O : unsigned(31 downto 0) := (others => '-');
-
- signal dout_rst : std_logic := '0';
- signal dout_reg : unsigned(31 downto 0);
- signal dout_cnt : natural range 0 to 255;
-
- SIGNAL ac97_bit_clk : std_logic := '0';
- SIGNAL ac97_reset_n : std_logic;
- SIGNAL ac97_sdata_out : std_logic;
- SIGNAL ac97_ssync : std_logic;
- SIGNAL ac97_sdata_in : std_logic;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
-uut : entity work.ac97_wb
- GENERIC MAP
- (
- fifo_depth => 4
- )
- PORT MAP
- (
- -- J-Bus domain
- CLK_I => CLK_O,
- RST_I => RST_O,
- CYC_I => CYC_O,
- STB_I => STB_O,
- WE_I => WE_O,
- ACK_O => ACK_I,
- SRDY_O => SRDY_I,
- MRDY_I => MRDY_O,
- ADDR_I => ADDR_O,
- DAT_I => DAT_O,
- DAT_O => DAT_I,
- INT_O => INT_I,
-
- -- AC97 domain
- ac97_sdata_in => ac97_sdata_in,
- ac97_bit_clk => ac97_bit_clk,
- ac97_reset_n => ac97_reset_n,
- ac97_sdata_out => ac97_sdata_out,
- ac97_ssync => ac97_ssync
- );
-
-
- ac97_sdata_in <= ac97_sdata_out;
-
-CLK_GEN: process
- begin
- wait for SYS_CLK_PERIOD/2;
- CLK_O <= not CLK_O;
- end process;
-
- bit_clk_gen : PROCESS
- begin
- if (ac97_reset_n = '0') then
- ac97_bit_clk <= '0';
- wait until ac97_reset_n = '1';
- wait for 150 us;
- end if;
- wait for BIT_CLK_PERIOD/2;
- ac97_bit_clk <= not ac97_bit_clk;
- END PROCESS;
-
-STIMULUS: process
-
- begin
-
- wait for 3*SYS_CLK_PERIOD;
- RST_O <= '0';
-
- wait for 200 us;
- wait until rising_edge(CLK_O);
-
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '0';
- DAT_O <= X"0000_0000";
- ADDR_O <= X"0000_0000";
- wait until rising_edge(CLK_O);
- STB_O <= '0';
- wait until rising_edge(CLK_O) and ACK_I = '1';
- CYC_O <= '0';
-
- wait until rising_edge(CLK_O);
-
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '1';
- DAT_O <= X"5555_1000";
- ADDR_O <= X"0000_0800";
- wait until rising_edge(CLK_O);
- DAT_O <= X"5555_1001";
- wait until rising_edge(CLK_O);
- STB_O <= '0';
- CYC_O <= '0';
-
- WAIT;
- END PROCESS;
-END;
diff --git a/lib/ac97_ctrl/src/tb_ac_in.vhd b/lib/ac97_ctrl/src/tb_ac_in.vhd
deleted file mode 100644
index 359e79b..0000000
--- a/lib/ac97_ctrl/src/tb_ac_in.vhd
+++ /dev/null
@@ -1,203 +0,0 @@
-
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:33:47 06/05/2007
--- Design Name: eval_ac
--- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
--- Project Name: ac_out
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: ac_out
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_ac_in IS
-END tb_ac_in;
-
-ARCHITECTURE behavior OF tb_ac_in IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT ac_in
- Port (
- rst : in std_logic;
- clk : in std_logic;
- sync_frame : out std_logic;
- sync_status : out std_logic;
- slot_valid : out unsigned(0 to 12);
- stat_addr : out unsigned (19 downto 0);
- stat_data : out unsigned (19 downto 0);
- pcm_out_addr : in unsigned (3 downto 0);
- pcm_out_data : out unsigned (19 downto 0);
- ac_reset : in std_logic;
- ac_bit_clk : in std_logic;
- ac_sdata_in : in std_logic;
- ac_ssync : in std_logic
- );
- END COMPONENT;
-
- COMPONENT ac_out
- PORT(
- rst : in std_logic;
- clk : in std_logic;
- sync_tx : out std_logic;
- cmd_addr : in unsigned(19 downto 0);
- cmd_data : in unsigned(19 downto 0);
- cmd_we : in std_logic;
- pcm_in_addr : in unsigned(3 downto 0);
- pcm_in_data : in unsigned(19 downto 0);
- pcm_in_we : in std_logic;
- ac_bit_clk : in std_logic;
- ac_reset : in std_logic;
- ac_sdata_out : out std_logic;
- ac_ssync : out std_logic
- );
- END COMPONENT;
-
- constant SYS_CLK_PERIOD : time := 10 ns;
- constant BIT_CLK_PERIOD : time := 81.38 ns;
-
- --Inputs
- SIGNAL rst : std_logic := '1';
- SIGNAL clk : std_logic := '0';
- SIGNAL cmd_we : std_logic := '0';
- SIGNAL pcm_in_we : std_logic := '0';
- SIGNAL ac_bit_clk : std_logic := '0';
- SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0');
- SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0');
- SIGNAL pcm_in_addr : unsigned(3 downto 0) := "0011";
- SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0');
- SIGNAL ac_sdata_in : std_logic;
- SIGNAL pcm_out_addr : unsigned(3 downto 0) := "0101";
- SIGNAL ac_reset : std_logic := '1';
-
- --Outputs
- SIGNAL sync_frame : std_logic;
- SIGNAL sync_status : std_logic;
- SIGNAL sync_tx : std_logic;
- SIGNAL ac_sdata_out : std_logic;
- SIGNAL ac_ssync : std_logic;
- SIGNAL stat_addr : unsigned(19 downto 0);
- SIGNAL stat_data : unsigned(19 downto 0);
- SIGNAL stat_valid : std_logic;
- SIGNAL pcm_out_data : unsigned(19 downto 0);
- SIGNAL pcm_out_valid : std_logic;
- SIGNAL pcm_out_avail : std_logic;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: ac_in PORT MAP(
- rst => rst,
- clk => clk,
- sync_frame => sync_frame,
- sync_status => sync_status,
- stat_addr => stat_addr,
- stat_data => stat_data,
- pcm_out_addr => pcm_out_addr,
- pcm_out_data => pcm_out_data,
- ac_reset => ac_reset,
- ac_bit_clk => ac_bit_clk,
- ac_sdata_in => ac_sdata_in,
- ac_ssync => ac_ssync
- );
-
- inst_ac_out: ac_out PORT MAP(
- rst => rst,
- clk => clk,
- sync_tx => sync_tx,
- cmd_addr => cmd_addr,
- cmd_data => cmd_data,
- cmd_we => cmd_we,
- pcm_in_addr => pcm_in_addr,
- pcm_in_data => pcm_in_data,
- pcm_in_we => pcm_in_we,
- ac_reset => ac_reset,
- ac_bit_clk => ac_bit_clk,
- ac_sdata_out => ac_sdata_out,
- ac_ssync => ac_ssync
- );
-
- ac_sdata_in <= ac_sdata_out;
-
- sys_clk_gen :
- PROCESS
- BEGIN
- wait for SYS_CLK_PERIOD;
- clk <= not clk;
- END PROCESS;
-
- bit_clk_gen :
- PROCESS
- BEGIN
- wait for BIT_CLK_PERIOD;
- ac_bit_clk <= not ac_bit_clk;
- END PROCESS;
-
- tb_out : PROCESS
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 100*SYS_CLK_PERIOD;
- rst <= '0';
-
- wait for 100*SYS_CLK_PERIOD;
- ac_reset <= '0';
-
- wait until rising_edge(clk) and sync_tx = '1';
- wait for 100*SYS_CLK_PERIOD;
- cmd_data <= X"12340";
- cmd_addr <= X"8B930";
-
- wait until rising_edge(clk);
- cmd_we <= '1';
- wait until rising_edge(clk);
- cmd_we <= '0';
-
- for k in 1 to 10 loop
- pcm_in_we <= '0';
- wait until rising_edge(clk) and sync_tx = '1';
- wait for 100*SYS_CLK_PERIOD;
- for i in 3 to 12 loop
- pcm_in_addr <= to_unsigned(i, 4);
- pcm_in_data <= to_unsigned(2048*k + integer(i), 20);
- pcm_in_we <= '1';
- wait until rising_edge(clk);
- end loop;
- end loop;
- pcm_in_we <= '0';
-
- -- Place stimulus here
-
- wait; -- will wait forever
- END PROCESS;
-
- tb_in : PROCESS(clk, pcm_out_addr, sync_status)
- BEGIN
- if rising_edge(clk) then
- if sync_status = '1' then
- pcm_out_addr <= "0011";
- elsif pcm_out_addr /= "1100" then
- pcm_out_addr <= pcm_out_addr + 1;
- end if;
- end if;
- END PROCESS;
-END;
diff --git a/lib/ac97_ctrl/src/tb_ac_io.vhd b/lib/ac97_ctrl/src/tb_ac_io.vhd
deleted file mode 100644
index 6f25c1d..0000000
--- a/lib/ac97_ctrl/src/tb_ac_io.vhd
+++ /dev/null
@@ -1,186 +0,0 @@
-
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:33:47 06/05/2007
--- Design Name: eval_ac
--- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
--- Project Name: ac_out
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: ac_out
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_ac_io IS
-END tb_ac_io;
-
-ARCHITECTURE behavior OF tb_ac_io IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT ac_io
- Port (
- rst : in std_logic;
- clk : in std_logic;
- ready : out std_logic;
- sync_strobe : out unsigned(0 to 2);
- slot_valid : out unsigned(0 to 12);
- stat_addr : out unsigned (19 downto 0);
- stat_data : out unsigned (19 downto 0);
- rx_pcm_addr : in unsigned (3 downto 0);
- rx_pcm_data : out unsigned (19 downto 0);
- cmd_addr : in unsigned(19 downto 0);
- cmd_data : in unsigned(19 downto 0);
- cmd_we : in std_logic;
- tx_pcm_addr : in unsigned(3 downto 0);
- tx_pcm_data : in unsigned(19 downto 0);
- tx_pcm_we : in std_logic;
- ac_sdata_in : in std_logic;
- ac_bit_clk : in std_logic;
- ac_reset_n : out std_logic;
- ac_sdata_out : out std_logic;
- ac_ssync : out std_logic
- );
- END COMPONENT;
-
- constant SYS_CLK_PERIOD : time := 10 ns;
- CONSTANT BIT_CLK_PERIOD : time := 100 ns;
--- constant BIT_CLK_PERIOD : time := 81.38 ns;
-
- --Inputs
- SIGNAL rst : std_logic := '1';
- SIGNAL clk : std_logic := '0';
- SIGNAL acio_ready : std_logic;
- SIGNAL cmd_we : std_logic := '0';
- SIGNAL tx_pcm_we : std_logic := '0';
- SIGNAL ac_bit_clk : std_logic := '0';
- SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0');
- SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0');
- SIGNAL tx_pcm_addr : unsigned(3 downto 0) := "0011";
- SIGNAL tx_pcm_data : unsigned(19 downto 0) := (others=>'0');
- SIGNAL ac_sdata_in : std_logic;
- SIGNAL rx_pcm_addr : unsigned(3 downto 0) := "0101";
-
- --Outputs
- SIGNAL slot_valid : unsigned(0 to 12);
- SIGNAL sync_strobe : unsigned(0 to 2);
- SIGNAL ac_reset_n : std_logic;
- SIGNAL ac_sdata_out : std_logic;
- SIGNAL ac_ssync : std_logic;
- SIGNAL stat_addr : unsigned(19 downto 0);
- SIGNAL stat_data : unsigned(19 downto 0);
- SIGNAL rx_pcm_data : unsigned(19 downto 0);
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: ac_io PORT MAP(
- rst => rst,
- clk => clk,
- ready => acio_ready,
- sync_strobe => sync_strobe,
- slot_valid => slot_valid,
- stat_addr => stat_addr,
- stat_data => stat_data,
- rx_pcm_addr => rx_pcm_addr,
- rx_pcm_data => rx_pcm_data,
- cmd_addr => cmd_addr,
- cmd_data => cmd_data,
- cmd_we => cmd_we,
- tx_pcm_addr => tx_pcm_addr,
- tx_pcm_data => tx_pcm_data,
- tx_pcm_we => tx_pcm_we,
- ac_sdata_in => ac_sdata_in,
- ac_bit_clk => ac_bit_clk,
- ac_reset_n => ac_reset_n,
- ac_sdata_out => ac_sdata_out,
- ac_ssync => ac_ssync
- );
-
- ac_sdata_in <= ac_sdata_out;
-
- sys_clk_gen :
- PROCESS
- BEGIN
- wait for SYS_CLK_PERIOD;
- clk <= not clk;
- END PROCESS;
-
- bit_clk_gen : PROCESS
- begin
- if (ac_reset_n = '0') then
- ac_bit_clk <= '0';
- wait until ac_reset_n = '1';
- wait for 150 us;
- end if;
- wait for BIT_CLK_PERIOD/2;
- ac_bit_clk <= not ac_bit_clk;
- END PROCESS;
-
- tb_out : PROCESS
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 100*SYS_CLK_PERIOD;
- rst <= '0';
-
- wait until (ac_reset_n = '1');
-
- wait until rising_edge(clk) and sync_strobe(2) = '1';
- wait for 100*SYS_CLK_PERIOD;
- cmd_data <= X"12340";
- cmd_addr <= X"8B930";
-
- wait until rising_edge(clk);
- cmd_we <= '1';
- wait until rising_edge(clk);
- cmd_we <= '0';
-
- for k in 1 to 10 loop
- tx_pcm_we <= '0';
- wait until rising_edge(clk) and sync_strobe(2) = '1';
- wait for 10*BIT_CLK_PERIOD;
- for i in 3 to 12 loop
- tx_pcm_addr <= to_unsigned(i, 4);
- tx_pcm_data <= to_unsigned(2048*k + integer(i), 20);
- tx_pcm_we <= '1';
- wait until rising_edge(clk);
- end loop;
- end loop;
- tx_pcm_we <= '0';
-
- -- Place stimulus here
-
- wait; -- will wait forever
- END PROCESS;
-
- tb_in : PROCESS(clk, rx_pcm_addr, sync_strobe)
- BEGIN
- if rising_edge(clk) then
- if sync_strobe(1) = '1' then
- rx_pcm_addr <= "0011";
- elsif rx_pcm_addr /= "1100" then
- rx_pcm_addr <= rx_pcm_addr + 1;
- end if;
- end if;
- END PROCESS;
-
-END;
diff --git a/lib/ac97_ctrl/src/tb_ac_out.vhd b/lib/ac97_ctrl/src/tb_ac_out.vhd
deleted file mode 100644
index 6f6cb42..0000000
--- a/lib/ac97_ctrl/src/tb_ac_out.vhd
+++ /dev/null
@@ -1,149 +0,0 @@
-
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:33:47 06/05/2007
--- Design Name: eval_ac
--- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
--- Project Name: ac_out
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: ac_out
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_ac_out IS
-END tb_ac_out;
-
-ARCHITECTURE behavior OF tb_ac_out IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT ac_out
- PORT(
- rst : IN std_logic;
- clk : IN std_logic;
- sync_tx : OUT std_logic;
- cmd_addr : IN unsigned(19 downto 0);
- cmd_data : IN unsigned(19 downto 0);
- cmd_we : IN std_logic;
- pcm_in_addr : IN unsigned(3 downto 0);
- pcm_in_data : IN unsigned(19 downto 0);
- pcm_in_we : IN std_logic;
- ac_bit_clk : IN std_logic;
- ac_reset : in std_logic;
- ac_sdata_out : OUT std_logic;
- ac_ssync : OUT std_logic
- );
- END COMPONENT;
-
- constant SYS_CLK_PERIOD : time := 10 ns;
- constant BIT_CLK_PERIOD : time := 81.38 ns;
-
- --Inputs
- SIGNAL rst : std_logic := '1';
- SIGNAL clk : std_logic := '0';
- SIGNAL ce : std_logic := '0';
- SIGNAL cmd_we : std_logic := '0';
- SIGNAL pcm_in_we : std_logic := '0';
- SIGNAL ac_bit_clk : std_logic := '0';
- SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0');
- SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0');
- SIGNAL pcm_in_addr : unsigned(3 downto 0) := (others=>'0');
- SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0');
-
- --Outputs
- SIGNAL sync_tx : std_logic;
- SIGNAL ac_reset : std_logic;
- SIGNAL ac_sdata_out : std_logic;
- SIGNAL ac_ssync : std_logic;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: ac_out PORT MAP(
- rst => rst,
- clk => clk,
- sync_tx => sync_tx,
- cmd_addr => cmd_addr,
- cmd_data => cmd_data,
- cmd_we => cmd_we,
- pcm_in_addr => pcm_in_addr,
- pcm_in_data => pcm_in_data,
- pcm_in_we => pcm_in_we,
- ac_reset => ac_reset,
- ac_bit_clk => ac_bit_clk,
- ac_sdata_out => ac_sdata_out,
- ac_ssync => ac_ssync
- );
-
- sys_clk_gen :
- PROCESS
- BEGIN
- wait for SYS_CLK_PERIOD;
- clk <= not clk;
- END PROCESS;
-
- bit_clk_gen :
- PROCESS
- BEGIN
- wait for BIT_CLK_PERIOD;
- ac_bit_clk <= not ac_bit_clk;
- END PROCESS;
-
- tb : PROCESS
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 100*SYS_CLK_PERIOD;
- rst <= '0';
-
- wait for 100*SYS_CLK_PERIOD;
- ac_reset <= '0';
-
- wait until rising_edge(clk) and sync_tx = '1';
- wait for 100*SYS_CLK_PERIOD;
- cmd_data <= X"aaaa0";
- cmd_addr <= X"1DFC0";
-
- wait until rising_edge(clk);
- cmd_we <= '1';
- wait until rising_edge(clk);
- cmd_we <= '0';
-
- for k in 1 to 10 loop
- pcm_in_we <= '0';
- wait until rising_edge(clk) and sync_tx = '1';
- wait for 100*SYS_CLK_PERIOD;
- for i in 3 to 12 loop
- pcm_in_addr <= to_unsigned(i, 4);
- pcm_in_data <= to_unsigned(2048*k + integer(i), 20);
- pcm_in_we <= '1';
- wait until rising_edge(clk);
- end loop;
- end loop;
- pcm_in_we <= '0';
-
- -- Place stimulus here
-
- wait; -- will wait forever
- END PROCESS;
-
-END;
diff --git a/lib/emac/.directory_history b/lib/emac/.directory_history
deleted file mode 100644
index 86afba5..0000000
--- a/lib/emac/.directory_history
+++ /dev/null
@@ -1,2 +0,0 @@
-VHDL/lib/emac/emac_jb.vhd
-
diff --git a/lib/emac/sim/.directory_history b/lib/emac/sim/.directory_history
deleted file mode 100644
index d6ce5c8..0000000
--- a/lib/emac/sim/.directory_history
+++ /dev/null
@@ -1,8 +0,0 @@
-VHDL/lib/emac/sim/tb_emac_jb.fdo
-VHDL/lib/emac/sim/tb_serdes.fdo
-VHDL/lib/emac/sim/tb_emac_jb.wdo
-VHDL/lib/emac/sim/tb_serdes.wdo
-VHDL/lib/emac/sim/tb_serdes.fdo
-
-VHDL/lib/emac/sim/tb_serdes.wdo
-
diff --git a/lib/emac/sim/tb_crc32.fdo b/lib/emac/sim/tb_crc32.fdo
deleted file mode 100644
index 241deb5..0000000
--- a/lib/emac/sim/tb_crc32.fdo
+++ /dev/null
@@ -1,14 +0,0 @@
-## NOTE: Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit -93 "../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/crc32.vhd"
-vcom -explicit -93 "../src/tb_crc32.vhd"
-vsim -t 1ps -lib work tb_crc32
-view wave
-do {tb_crc32.wdo}
-view structure
-view signals
-
-run 1 us
diff --git a/lib/emac/sim/tb_crc32.wdo b/lib/emac/sim/tb_crc32.wdo
deleted file mode 100644
index dca5016..0000000
--- a/lib/emac/sim/tb_crc32.wdo
+++ /dev/null
@@ -1,25 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_crc32/clk
-add wave -noupdate -format Logic /tb_crc32/rst
-add wave -noupdate -format Logic /tb_crc32/din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/crc32
-add wave -noupdate -format Logic /tb_crc32/crc32_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/test_data
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {667016 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {1050 ns}
diff --git a/lib/emac/sim/tb_emac_jb.fdo b/lib/emac/sim/tb_emac_jb.fdo
deleted file mode 100644
index dc5d8f1..0000000
--- a/lib/emac/sim/tb_emac_jb.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-## NOTE: Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit -93 "../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/piso.vhd"
-vcom -explicit -93 "../src/sipo.vhd"
-vcom -explicit -93 "../src/tb_serdes.vhd"
-vsim -t 1ps -lib work tb_serdes
-view wave
-do {tb_serdes.wdo}
-view structure
-view signals
-
-run 20 us
diff --git a/lib/emac/sim/tb_emac_jb.wdo b/lib/emac/sim/tb_emac_jb.wdo
deleted file mode 100644
index 6137fb4..0000000
--- a/lib/emac/sim/tb_emac_jb.wdo
+++ /dev/null
@@ -1,58 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/rst
-add wave -noupdate -divider PiSo
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/piso_din_vld
-add wave -noupdate -format Logic /tb_serdes/piso_din_rdy
-add wave -noupdate -format Literal /tb_serdes/piso_din_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_din
-add wave -noupdate -format Logic /tb_serdes/piso_dout_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_dout
-add wave -noupdate -format Logic /tb_serdes/piso_dout_en
-add wave -noupdate -divider SiPo
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/sipo_enable
-add wave -noupdate -format Logic /tb_serdes/sipo_rst
-add wave -noupdate -format Logic /tb_serdes/sipo_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_din
-add wave -noupdate -format Logic /tb_serdes/sipo_dout_vld
-add wave -noupdate -format Logic /tb_serdes/sipo_dout_en
-add wave -noupdate -format Literal /tb_serdes/sipo_dout_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_dout
-add wave -noupdate -divider PiSo
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/piso2_din_vld
-add wave -noupdate -format Logic /tb_serdes/piso2_din_rdy
-add wave -noupdate -format Literal /tb_serdes/piso2_din_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_din
-add wave -noupdate -format Logic /tb_serdes/piso2_dout_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_dout
-add wave -noupdate -format Logic /tb_serdes/piso2_dout_en
-add wave -noupdate -divider SiPo
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/sipo2_enable
-add wave -noupdate -format Logic /tb_serdes/sipo2_rst
-add wave -noupdate -format Logic /tb_serdes/sipo2_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_din
-add wave -noupdate -format Logic /tb_serdes/sipo2_dout_vld
-add wave -noupdate -format Logic /tb_serdes/sipo2_dout_en
-add wave -noupdate -format Literal /tb_serdes/sipo2_dout_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_dout
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {19757882 ps} 0} {{Cursor 2} {49999912163 ps} 0} {{Cursor 3} {49999529250 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {21 us}
diff --git a/lib/emac/sim/tb_emac_top_jb.fdo b/lib/emac/sim/tb_emac_top_jb.fdo
deleted file mode 100644
index d050525..0000000
--- a/lib/emac/sim/tb_emac_top_jb.fdo
+++ /dev/null
@@ -1,29 +0,0 @@
-## NOTE: Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit -93 "../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
-vcom -explicit -93 "../../misc/dpram_2w2r.vhd"
-vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd"
-vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
-vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
-vcom -explicit -93 "../src/piso.vhd"
-vcom -explicit -93 "../src/sipo.vhd"
-vcom -explicit -93 "../src/crc32.vhd"
-vcom -explicit -93 "../src/emac_types.vhd"
-vcom -explicit -93 "../src/emac_rx.vhd"
-vcom -explicit -93 "../src/emac_tx.vhd"
-vcom -explicit -93 "../src/emac_top_jb.vhd"
-vcom -explicit -93 "../src/pkt_gen.vhd"
-vcom -explicit -93 "../src/tb_emac_top_jb.vhd"
-vsim -t 1ps -lib work tb_emac_top_jb
-view wave
-do {tb_emac_top_jb.wdo}
-view structure
-view signals
-
-run 50000 us
diff --git a/lib/emac/sim/tb_emac_top_jb.wdo b/lib/emac/sim/tb_emac_top_jb.wdo
deleted file mode 100644
index dd68f73..0000000
--- a/lib/emac/sim/tb_emac_top_jb.wdo
+++ /dev/null
@@ -1,207 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Ethernet MAC}
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/clk_i
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/rst_i
-add wave -noupdate -format Logic -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/int_o
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/cyc_i
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/stb_i
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/sel_i
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/we_i
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/ack_o
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/srdy_o
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mrdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/addr_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_o
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_er
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_rx
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_clk
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_er
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_tx
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_gtx_clk
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_crs
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/status_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/size_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg
-add wave -noupdate -format Literal /tb_emac_top_jb/emac_action
-add wave -noupdate -format Logic /tb_emac_top_jb/dat_o_cnt_rst
-add wave -noupdate -format Literal /tb_emac_top_jb/dat_o_cnt
-add wave -noupdate -format Literal /tb_emac_top_jb/pkt_count
-add wave -noupdate -divider {Packet generator}
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/host_s
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_in
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_out
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_size
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_cnt
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_set
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_pkt_gen/tx_din
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/tx_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/pktgen_tx
-add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_en
-add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_er
-add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_en
-add wave -noupdate -divider RX
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
-add wave -noupdate -format Literal -radix unsigned -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_clk
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_dv
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_er
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_crs
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_col
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ptr
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_limit
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_base
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/commit_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_limit
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_a
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_be
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_rst
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_rst
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_en
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_ok
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_chk_ok
-add wave -noupdate -divider TX
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_re
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_empty
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_full
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_pre_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_bsy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_set
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_base
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_size
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_remain
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ok
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_req
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ack
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/nwords_free
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_size
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_alloc_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/commit_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/uncommit_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_bsy
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_size
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_set
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_a
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_a
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_be
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re_dly
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_rst
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_din_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_clk
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_er
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {242561800 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {42725669958 ps} 0} {{Cursor 4} {16290550071 ps} 0} {{Cursor 5} {4181100 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {52500 us}
diff --git a/lib/emac/src/.directory_history b/lib/emac/src/.directory_history
deleted file mode 100644
index 787df57..0000000
--- a/lib/emac/src/.directory_history
+++ /dev/null
@@ -1,8 +0,0 @@
-VHDL/lib/emac/emac_jb.vhd
-VHDL/lib/emac/src/emac_jb.vhd
-VHDL/lib/emac/src/emac_jb.vhd
-
-VHDL/lib/emac/src/tb_emac_jb.vhd
-VHDL/lib/emac/src/tb_serdes.vhd
-VHDL/lib/emac/src/tb_serdes.vhd
-
diff --git a/lib/emac/src/crc32.vhd b/lib/emac/src/crc32.vhd
deleted file mode 100644
index 629b585..0000000
--- a/lib/emac/src/crc32.vhd
+++ /dev/null
@@ -1,64 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-use work.utils_pkg.all; -- Imports the standard textio package.
-
-ENTITY crc32 IS
- Generic
- (
- crc32_init : unsigned(31 downto 0) := X"00000000"
- );
- Port
- (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- din_vld : in STD_LOGIC;
- din : in unsigned(7 downto 0);
- crc32_vld : out STD_LOGIC;
- crc32_out : out unsigned(31 downto 0)
-
- );
-END crc32;
-
-ARCHITECTURE behavior OF crc32 IS
-
- type crc_table_t is array (0 to 15) of unsigned(31 downto 0);
-
- constant crc_table : crc_table_t :=
- (
- X"4DBDF21C", X"500AE278", X"76D3D2D4", X"6B64C2B0",
- X"3B61B38C", X"26D6A3E8", X"000F9344", X"1DB88320",
- X"A005713C", X"BDB26158", X"9B6B51F4", X"86DC4190",
- X"D6D930AC", X"CB6E20C8", X"EDB71064", X"F0000000"
- );
-
- signal crc0 : unsigned(31 downto 0);
- signal crc1 : unsigned(31 downto 0);
- signal crc2 : unsigned(31 downto 0);
-
---------------------------------------------------------------------------
-begin
-
- crc1 <= X"0" & crc0(31 downto 4) xor crc_table(to_integer(crc0(3 downto 0) xor din(3 downto 0)));
- crc2 <= X"0" & crc1(31 downto 4) xor crc_table(to_integer(crc1(3 downto 0) xor din(7 downto 4)));
-
- crc32_out <= crc0;
-
---------------------------------------------------------------------------
-process(clk)
-begin
- if rising_edge(clk) then
- if rst = '1' then
- crc0 <= crc32_init;
- crc32_vld <= '0';
- elsif din_vld = '1' then
- crc0 <= crc2;
- crc32_vld <= '1';
- end if;
- end if;
-end process;
-
---------------------------------------------------------------------------
-end behavior;
diff --git a/lib/emac/src/emac_rx.vhd b/lib/emac/src/emac_rx.vhd
deleted file mode 100644
index 3c1ef2b..0000000
--- a/lib/emac/src/emac_rx.vhd
+++ /dev/null
@@ -1,559 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-use work.emac_types.all;
-use work.utils_pkg.all;
-
-ENTITY emac_rx IS
- Generic
- (
- f_sysclk : real := 100.0;
- RAM_SIZE : natural := 2048
- );
- Port
- (
- clk : in STD_LOGIC;
- rst : in STD_LOGIC;
- dout_vld : out STD_LOGIC;
- dout : out unsigned(31 downto 0);
- ctrl_in : in rx_ctrl_in_t;
- ctrl_out : out rx_ctrl_out_t;
- mii_rx_clk : in STD_LOGIC;
- mii_rx_dv : in STD_LOGIC;
- mii_rx_er : in STD_LOGIC;
- mii_rx : in unsigned(7 downto 0);
- mii_crs : in STD_LOGIC;
- mii_col : in STD_LOGIC
-
- );
-END emac_rx;
-
-ARCHITECTURE behavior OF emac_rx IS
-
- constant RAM_ADDR_WIDTH : natural := NextExpBaseTwo(RAM_SIZE);
-
- subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
-
- -- Signals for EMAC connections
- signal cmd_fifo_din : unsigned(2*word_ptr_t'length+2 downto 0);
- signal cmd_fifo_dout : unsigned(2*word_ptr_t'length+2 downto 0);
- signal cmd_fifo_we : std_logic;
- signal cmd_fifo_re : std_logic;
- signal cmd_fifo_empty : std_logic;
- signal cmd_fifo_full : std_logic;
-
- signal reset_en : std_logic;
-
- signal host_ptr : word_ptr_t;
- signal host_ram_limit : word_ptr_t;
- signal host_ram_base : word_ptr_t;
-
- signal commit_en : std_logic;
-
- signal xfer_ram_limit : word_ptr_t;
- signal xfer_ram_full : std_logic;
- signal xfer_base : word_ptr_t;
- signal xfer_ptr : word_ptr_t;
- signal xfer_en : std_logic;
- signal xfer_set : std_logic;
- signal xfer_vld : std_logic;
- signal xfer_promiscious : std_logic;
-
- signal ram_en_a : std_logic;
- signal ram_we_a : std_logic;
- signal ram_addr_a : word_ptr_t;
- signal ram_din_a : unsigned(31 downto 0);
- signal ram_dout_b : unsigned(31 downto 0);
- signal ram_en_b : std_logic;
- signal ram_addr_b : word_ptr_t;
-
- signal sipo32_din : unsigned(7 downto 0);
- signal sipo32_din_vld : std_logic;
- signal sipo32_dout : unsigned(31 downto 0);
- signal sipo32_dout_be : unsigned(3 downto 0);
- signal sipo32_dout_vld : std_logic;
- signal sipo32_dout_en : std_logic;
- signal sipo32_en : std_logic;
- signal sipo32_rst : std_logic;
-
- signal sipo8_dout : unsigned(7 downto 0);
- signal sipo8_rst : std_logic;
- signal sipo8_dout_vld : std_logic;
- signal sipo8_dout_en : std_logic;
- signal sipo8_en : std_logic;
-
- signal byte_count_rst : std_logic;
- signal byte_count : word_ptr_t;
-
- signal reset_pipe : unsigned(31 downto 0);
-
- signal preamble_en : std_logic;
- signal preamble_rdy : std_logic;
- signal preamble_bsy : std_logic;
- signal preamble_OK : std_logic;
-
- signal mac_chk_rdy : std_logic;
- signal mac_chk_BC : std_logic;
- signal mac_chk_OK : std_logic;
- signal mac_chk_num_OK : natural range 0 to 6;
- signal mac_chk_num_BC : natural range 0 to 6;
- signal mac_chk_cnt : natural range 0 to 5;
- signal mac_addr : mac_addr_t;
- signal mac_chk_addr : mac_addr_t;
-
- signal Gbps_en : std_logic;
- signal fcs_chk_en : std_logic;
- signal rx_en : std_logic;
-
- signal fcs_vld : std_logic;
- signal fcs_din_vld : std_logic;
- signal fcs_din : unsigned(7 downto 0);
- signal fcs : unsigned(31 downto 0);
- signal fcs_chk_OK : std_logic;
-
- type host_state_t is (host_init, host_flush, host_idle);
- signal host_s, host_sn : host_state_t;
-
- type xfer_state_t is (xfer_init, xfer_idle, xfer_preamble, xfer_setup, xfer_active, xfer_finish, xfer_commit);
- signal xfer_s, xfer_sn : xfer_state_t;
-
- alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left);
- alias cmd_bcast_in is cmd_fifo_din(cmd_fifo_din'left-1);
- alias cmd_pkt_valid_in is cmd_fifo_din(cmd_fifo_din'left-2);
- alias cmd_nbytes_in is cmd_fifo_din(word_ptr_t'length-1 downto 0);
- alias cmd_base_in is cmd_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
-
- alias cmd_mac_ok_out is cmd_fifo_dout(cmd_fifo_dout'left);
- alias cmd_bcast_out is cmd_fifo_dout(cmd_fifo_dout'left-1);
- alias cmd_pkt_valid_out is cmd_fifo_dout(cmd_fifo_dout'left-2);
- alias cmd_nbytes_out is cmd_fifo_dout(word_ptr_t'length-1 downto 0);
- alias cmd_base_out is cmd_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
-
-begin
-
- ctrl_out.rx_size <= resize(cmd_nbytes_out, 16);
- ctrl_out.pkt_avail <= not cmd_fifo_empty;
- ctrl_out.pkt_valid <= cmd_pkt_valid_out;
- ctrl_out.pkt_bcast <= cmd_bcast_out;
- ctrl_out.pkt_mac_match <= cmd_mac_ok_out;
- ctrl_out.reset_busy <= reset_en;
-
- dout <= ram_dout_b;
-
- ram_en_b <= '1';
- ram_addr_b <= host_ptr;
-
- ram_en_a <= '1';
- ram_din_a <= sipo32_dout;
- ram_addr_a <= xfer_ptr;
- ram_we_a <= xfer_en and sipo32_dout_vld;
-
- xfer_vld <= (mac_chk_OK or mac_chk_BC or xfer_promiscious) and (not fcs_chk_en or fcs_chk_OK);
- cmd_fifo_we <= commit_en and xfer_vld;
- cmd_fifo_re <= ctrl_in.pkt_free_en;
-
- cmd_pkt_valid_in <= fcs_chk_OK;
- cmd_mac_ok_in <= mac_chk_OK;
- cmd_bcast_in <= mac_chk_BC;
- cmd_nbytes_in <= byte_count;
- cmd_base_in <= xfer_base;
-
-
- reset_en <= reset_pipe(reset_pipe'left);
-
-------------------------------------------------------------------
-reset_gen:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' or ctrl_in.reset = '1' then
- reset_pipe <= (others => '1');
- else
- reset_pipe <= reset_pipe(reset_pipe'left-1 downto 0) & '0';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
--- Fill stuff
-------------------------------------------------------------------
-fill_pointer:
- process(clk)
- begin
- if rising_edge(clk) then
- dout_vld <= ctrl_in.pkt_read_en;
- if ctrl_in.pkt_req_en = '1' then
- host_ptr <= cmd_base_out;
- elsif ctrl_in.pkt_read_en = '1' then
- host_ptr <= host_ptr + 1;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
--- Transfer stuff
-------------------------------------------------------------------
-host2xfer_sync_register:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- xfer_promiscious <= ctrl_in.promiscious;
- Gbps_en <= ctrl_in.Gbps_en;
- fcs_chk_en <= ctrl_in.fcs_chk_en;
- mac_addr <= ctrl_in.mac_addr;
- xfer_ram_limit <= host_ram_limit;
- end if;
- end process;
-
-host_limit_register:
- process(clk)
- begin
- if rising_edge(clk) then
- host_ram_base <= xfer_base;
- if cmd_fifo_empty = '1' then
- host_ram_limit <= host_ram_base - 1;
- else
- host_ram_limit <= cmd_base_out - 1;
- end if;
- end if;
-
- end process;
-
-xfer_ram_full_detect:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- if xfer_set = '1' or reset_en = '1' then
- xfer_ram_full <= '0';
- elsif xfer_en = '1' and sipo32_dout_vld = '1' then
- if xfer_ptr = xfer_ram_limit then
- xfer_ram_full <= '1';
- end if;
- end if;
- end if;
-
- end process;
-
-xfer_base_logic:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- if reset_en = '1' then
- xfer_base <= (others => '0');
- elsif commit_en = '1' and xfer_vld = '1' then
- xfer_base <= xfer_ptr;
- end if;
- end if;
- end process;
-
-xfer_pointer:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- if xfer_set = '1' then
- xfer_ptr <= xfer_base;
- elsif xfer_en = '1' and sipo32_dout_vld = '1' then
- xfer_ptr <= xfer_ptr + 1;
- end if;
- end if;
-
- end process;
-
-------------------------------------------------------------------
-byte_counter:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- if byte_count_rst = '1' then
- if fcs_chk_en = '0' then
- byte_count <= to_unsigned(0, RAM_ADDR_WIDTH);
- else
- byte_count <= unsigned(to_signed(-4, RAM_ADDR_WIDTH));
- end if;
- elsif sipo32_en = '1' and sipo32_din_vld = '1' then
- byte_count <= byte_count + 1;
- end if;
- end if;
- end process;
-
-preamble_sync_logic:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- if preamble_en = '0' then
- preamble_rdy <= '0';
- preamble_bsy <= '0';
- preamble_OK <= '0';
- elsif sipo32_din_vld = '1' then
- if preamble_bsy = '1' then
- if sipo32_din = X"D5" then
- preamble_OK <= '1';
- end if;
- end if;
- if sipo32_din /= X"55" then
- preamble_bsy <= '0';
- preamble_rdy <= preamble_bsy;
- else
- preamble_bsy <= '1';
- end if;
- end if;
- end if;
- end process;
-
-mac_check_logic:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- if byte_count_rst = '1' then
- mac_chk_rdy <= '0';
- mac_chk_OK <= '0';
- mac_chk_BC <= '0';
- mac_chk_cnt <= 0;
- mac_chk_num_OK <= 0;
- mac_chk_num_BC <= 0;
- mac_chk_addr <= mac_addr;
- elsif mac_chk_rdy = '1' then
- if mac_chk_num_OK = 6 then
- mac_chk_OK <= '1';
- end if;
- if mac_chk_num_BC = 6 then
- mac_chk_BC <= '1';
- end if;
- elsif sipo32_din_vld = '1' and sipo32_en = '1' then
- if sipo32_din = mac_chk_addr(mac_chk_cnt) then
- mac_chk_num_OK <= mac_chk_num_OK + 1;
- end if;
- if sipo32_din = X"FF" then
- mac_chk_num_BC <= mac_chk_num_BC + 1;
- end if;
- if mac_chk_cnt /= 5 then
- mac_chk_cnt <= mac_chk_cnt + 1;
- else
- mac_chk_rdy <= '1';
- end if;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-xfer_state_next:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- if reset_en = '1' then
- xfer_s <= xfer_init;
- else
- xfer_s <= xfer_sn;
- end if;
- end if;
- end process;
-
-xfer_state:
- process(xfer_s, rx_en, sipo32_dout_en, preamble_bsy, preamble_OK, xfer_ram_full)
- begin
-
- commit_en <= '0';
- xfer_set <= '0';
- xfer_en <= '0';
- sipo32_rst <= '0';
- sipo32_en <= '0';
- byte_count_rst <= '0';
- preamble_en <= '0';
-
- xfer_sn <= xfer_s;
-
- case xfer_s is
-
- when xfer_init =>
- sipo32_rst <= '1';
- if rx_en = '0' then
- xfer_sn <= xfer_idle;
- end if;
-
- when xfer_idle =>
- preamble_en <= rx_en;
- if preamble_bsy = '1' then
- xfer_sn <= xfer_preamble;
- end if;
-
- when xfer_preamble =>
- preamble_en <= rx_en;
- byte_count_rst <= preamble_bsy;
- sipo32_en <= rx_en and not preamble_bsy;
- if preamble_bsy = '0' then
- xfer_sn <= xfer_init;
- if preamble_OK = '1' then
- xfer_sn <= xfer_setup;
- end if;
- end if;
-
- when xfer_setup =>
- xfer_set <= '1';
- sipo32_en <= rx_en;
- xfer_en <= sipo32_dout_en;
- xfer_sn <= xfer_active;
-
- when xfer_active =>
- xfer_en <= sipo32_dout_en;
- sipo32_en <= rx_en;
- if xfer_ram_full = '1' then
- xfer_sn <= xfer_init;
- elsif rx_en = '0' then
- xfer_sn <= xfer_finish;
- end if;
-
- when xfer_finish =>
- xfer_en <= sipo32_dout_en;
- if sipo32_dout_en = '0' then
- xfer_sn <= xfer_commit;
- end if;
-
- when xfer_commit =>
- commit_en <= '1';
- xfer_sn <= xfer_init;
-
- when others =>
- xfer_sn <= xfer_init;
- end case;
-
- end process;
-
-------------------------------------------------------------------
--- Instantiate synchronous FIFO
-inst_cmd_fifo: entity work.fifo_async
- GENERIC MAP
- (
- addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
- data_width => cmd_fifo_din'length,
- do_last_read_update => false
- )
- PORT MAP
- (
- rst => reset_en,
- clk_w => mii_rx_clk,
- clk_r => clk,
- we => cmd_fifo_we,
- re => cmd_fifo_re,
- fifo_full => cmd_fifo_full,
- fifo_empty => cmd_fifo_empty,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => cmd_fifo_din,
- data_r => cmd_fifo_dout
- );
-
-inst_ram : entity work.dpram_1w1r
- GENERIC MAP
- (
- addr_width => RAM_ADDR_WIDTH,
- data_width => 32
- )
- PORT MAP
- (
- clka => mii_rx_clk,
- clkb => clk,
- en_a => ram_en_a,
- en_b => ram_en_b,
- we_a => ram_we_a,
- addr_a => ram_addr_a,
- addr_b => ram_addr_b,
- din_a => ram_din_a,
- dout_b => ram_dout_b
- );
-
-inst_sipo32 : entity work.sipo
- GENERIC MAP
- (
- data_width_in => 8,
- data_width_out => 32,
- msb_first => true
- )
- PORT MAP
- (
- rst => sipo32_rst,
- clk => mii_rx_clk,
- din_vld => sipo32_din_vld,
- din_en => sipo32_en,
- din => sipo32_din,
- dout_be => sipo32_dout_be,
- dout_vld => sipo32_dout_vld,
- dout => sipo32_dout,
- dout_en => sipo32_dout_en
-
- );
-
-inst_fcs: entity work.crc32
- GENERIC MAP
- (
- crc32_init => X"00000000"
- )
- PORT MAP
- (
- rst => byte_count_rst,
- clk => mii_rx_clk,
- din_vld => fcs_din_vld,
- din => fcs_din,
- crc32_vld => fcs_vld,
- crc32_out => fcs
-
- );
-
- fcs_din <= sipo32_din;
- fcs_din_vld <= sipo32_en and sipo32_din_vld;
-
-fcs_chk_register:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- if fcs_vld = '1' then
- fcs_chk_OK <= '0';
- if fcs = X"2144DF1C" then
- fcs_chk_OK <= '1';
- end if;
- end if;
- end if;
- end process;
-
-mii_input_register:
- process(mii_rx_clk)
- begin
- if rising_edge(mii_rx_clk) then
- if Gbps_en = '1' then
- sipo32_din <= mii_rx;
- sipo32_din_vld <= not mii_rx_er;
- rx_en <= mii_rx_dv;
- else
- sipo32_din <= sipo8_dout;
- sipo32_din_vld <= sipo8_dout_vld;
- rx_en <= sipo8_dout_en;
- end if;
- end if;
- end process;
-
-inst_sipo_8bit : entity work.sipo
- GENERIC MAP
- (
- data_width_in => 4,
- data_width_out => 8,
- msb_first => false
- )
- PORT MAP
- (
- rst => sipo8_rst,
- clk => mii_rx_clk,
- din_vld => mii_rx_dv,
- din_en => mii_rx_dv,
- din => mii_rx(3 downto 0),
- dout_be => open,
- dout_vld => sipo8_dout_vld,
- dout => sipo8_dout,
- dout_en => sipo8_dout_en
-
- );
-
- sipo8_rst <= reset_en or not (mii_rx_dv or sipo8_dout_en);
- sipo8_en <= not mii_rx_er;
-
-end behavior;
diff --git a/lib/emac/src/emac_top_jb.vhd b/lib/emac/src/emac_top_jb.vhd
deleted file mode 100644
index 44c2e8d..0000000
--- a/lib/emac/src/emac_top_jb.vhd
+++ /dev/null
@@ -1,305 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-use work.emac_types.all;
-use work.utils_pkg.all;
-
-ENTITY emac_top_jb IS
- Generic
- (
- f_sysclk : real := 100.0;
- TX_RAM_SIZE : natural := 2048;
- RX_RAM_SIZE : natural := 2048
- );
- Port
- (
- CLK_I : in STD_LOGIC;
- RST_I : in STD_LOGIC;
- INT_O : out STD_LOGIC;
- CYC_I : in STD_LOGIC;
- STB_I : in STD_LOGIC;
- SEL_I : in unsigned(3 downto 0);
- WE_I : in STD_LOGIC;
- ACK_O : out STD_LOGIC;
- SRDY_O : out STD_LOGIC;
- MRDY_I : in STD_LOGIC;
- ADDR_I : in unsigned(31 downto 0);
- DAT_I : in unsigned(31 downto 0);
- DAT_O : out unsigned(31 downto 0);
- mii_rx_clk : in STD_LOGIC;
- mii_rx_dv : in STD_LOGIC;
- mii_rx_er : in STD_LOGIC;
- mii_rx : in unsigned(7 downto 0);
- mii_tx_clk : in STD_LOGIC;
- mii_tx_en : out STD_LOGIC;
- mii_tx_er : out STD_LOGIC;
- mii_tx : out unsigned(7 downto 0);
- mii_gtx_clk : out STD_LOGIC;
- mii_crs : in STD_LOGIC;
- mii_col : in STD_LOGIC
-
- );
-END emac_top_jb;
-
-ARCHITECTURE behavior OF emac_top_jb IS
-
- -- Signals for EMAC connections
- signal tx_ctrl_in : tx_ctrl_in_t;
- signal tx_ctrl_out : tx_ctrl_out_t;
- signal tx_din : unsigned(31 downto 0);
- signal tx_din_vld : std_logic;
-
- signal rx_ctrl_in : rx_ctrl_in_t;
- signal rx_ctrl_out : rx_ctrl_out_t;
-
- signal rx_dout : unsigned(31 downto 0);
- signal rx_dout_vld : std_logic;
-
- signal rx_int_en : std_logic;
- signal tx_int_en : std_logic;
- signal irq_rx : std_logic;
- signal irq_tx : std_logic;
-
- signal ready : std_logic;
-
- signal read : std_logic;
- signal write : std_logic;
- signal data_read : std_logic;
- signal data_write : std_logic;
- signal reg_read : std_logic;
- signal reg_write : std_logic;
-
- signal reg_addr : unsigned(3 downto 0);
-
-begin
-
- mii_gtx_clk <= '0';
-
- SRDY_O <= CYC_I and ready;
- read <= STB_I and CYC_I and not WE_I;
- write <= STB_I and CYC_I and WE_I;
- data_read <= read and ADDR_I(15);
- data_write <= write and ADDR_I(15);
- reg_read <= read and not ADDR_I(15);
- reg_write <= write and not ADDR_I(15);
- reg_addr <= ADDR_I(5 downto 2);
-
- ready <= not tx_ctrl_in.pkt_alloc_en;
-
- tx_din_vld <= data_write;
- tx_din <= DAT_I;
-
- rx_ctrl_in.pkt_read_en <= data_read;
-
-------------------------------------------------------------------
-registers_write:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- tx_ctrl_in.pkt_alloc_en <= '0';
- tx_ctrl_in.pkt_commit_en <= '0';
- tx_ctrl_in.reset <= '0';
- rx_ctrl_in.pkt_free_en <= '0';
- rx_ctrl_in.pkt_req_en <= '0';
- rx_ctrl_in.reset <= '0';
- if RST_I = '1' then
- rx_int_en <= '0';
- tx_int_en <= '0';
- tx_ctrl_in.tx_size <= (others => '0');
- rx_ctrl_in.mac_addr <= (X"03", X"02", X"01", X"00", X"07", X"06");
- rx_ctrl_in.promiscious <= '0';
- tx_ctrl_in.Gbps_en <= '0';
- rx_ctrl_in.Gbps_en <= '0';
- tx_ctrl_in.fcs_gen_en <= '0';
- rx_ctrl_in.fcs_chk_en <= '0';
- elsif reg_write = '1' then
-
- -- 0x0000 .. 0x003C
- case reg_addr is
-
- -- 0x0000
- when "0000" =>
- rx_ctrl_in.reset <= DAT_I(31);
- rx_ctrl_in.Gbps_en <= DAT_I(30);
- rx_ctrl_in.fcs_chk_en <= DAT_I(29);
- rx_ctrl_in.promiscious <= DAT_I(23);
- rx_ctrl_in.pkt_req_en <= DAT_I(17);
- rx_ctrl_in.pkt_free_en <= DAT_I(16);
- rx_int_en <= DAT_I(4);
-
- -- 0x0004
- -- rx_size R/O
-
- -- 0x0008
- when "0010" =>
- tx_ctrl_in.reset <= DAT_I(31);
- tx_ctrl_in.Gbps_en <= DAT_I(30);
- tx_ctrl_in.fcs_gen_en <= DAT_I(29);
- tx_ctrl_in.pkt_alloc_en <= DAT_I(17);
- tx_ctrl_in.pkt_commit_en <= DAT_I(16);
- tx_int_en <= DAT_I(4);
-
- -- 0x000C
- when "0011" =>
- tx_ctrl_in.tx_size <= DAT_I(15 downto 0);
-
- -- 0x0010
- -- Gap
-
- -- 0x0014
- -- Gap
-
- -- 0x0018
- when "0110" =>
- rx_ctrl_in.mac_addr(0) <= DAT_I(31 downto 24);
- rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16);
- rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8);
- rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0);
-
- -- 0x001C
- when "0111" =>
- rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24);
- rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16);
-
- -- 0x0020 .. 0x003C
- -- Gap
- when others => null;
-
- end case;
-
- end if;
- end if;
- end process;
-
-registers_read:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- ACK_O <= rx_dout_vld;
- DAT_O <= rx_dout;
- if reg_read = '1' then
-
- -- 0x0000 .. 0x003C
- case reg_addr is
-
- -- 0x0000
- when "0000" =>
- ACK_O <= ready;
- DAT_O <= (others => '0');
- DAT_O(31) <= rx_ctrl_out.reset_busy;
- DAT_O(30) <= rx_ctrl_in.Gbps_en;
- DAT_O(29) <= rx_ctrl_in.fcs_chk_en;
- DAT_O(23) <= rx_ctrl_in.promiscious;
- DAT_O(19) <= rx_ctrl_out.pkt_bcast;
- DAT_O(18) <= rx_ctrl_out.pkt_mac_match;
- DAT_O(17) <= rx_ctrl_out.pkt_valid;
- DAT_O(16) <= rx_ctrl_out.pkt_avail;
- DAT_O(4) <= rx_int_en;
-
- -- 0x0004
- when "0001" =>
- ACK_O <= '1';
- DAT_O <= X"0000" & rx_ctrl_out.rx_size;
-
- -- 0x0008
- when "0010" =>
- ACK_O <= ready;
- DAT_O <= (others => '0');
- DAT_O(31) <= tx_ctrl_out.reset_busy;
- DAT_O(30) <= tx_ctrl_in.Gbps_en;
- DAT_O(29) <= tx_ctrl_in.fcs_gen_en;
- DAT_O(24) <= tx_ctrl_out.pkt_done;
- DAT_O(17) <= tx_ctrl_out.pkt_alloc_req;
- DAT_O(16) <= tx_ctrl_out.pkt_armed;
- DAT_O(4) <= tx_int_en;
-
- -- 0x000C
- when "0011" =>
- ACK_O <= '1';
- DAT_O <= X"0000" & tx_ctrl_out.tx_size;
-
- -- 0x0010
- -- Gap
-
- -- 0x0014
- -- Gap
-
- -- 0x0018
- when "0110" =>
- ACK_O <= '1';
- DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
-
- -- 0x001C
- when "0111" =>
- ACK_O <= '1';
- DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
-
- -- 0x0020 .. 0x003C
- -- Gap
- when others => null;
-
- end case;
-
- end if;
- end if;
- end process;
-
-irq_register:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- INT_O <= irq_rx or irq_tx;
- irq_tx <= tx_int_en and tx_ctrl_out.pkt_done;
- irq_rx <= rx_int_en and rx_ctrl_out.pkt_avail;
- end if;
- end process;
-
-inst_emac_rx : entity work.emac_rx
- GENERIC MAP
- (
- f_sysclk => f_sysclk,
- RAM_SIZE => RX_RAM_SIZE
- )
- PORT MAP
- (
- clk => CLK_I,
- rst => RST_I,
- dout_vld => rx_dout_vld,
- dout => rx_dout,
- ctrl_in => rx_ctrl_in,
- ctrl_out => rx_ctrl_out,
- mii_rx_clk => mii_rx_clk,
- mii_rx_dv => mii_rx_dv,
- mii_rx_er => mii_rx_er,
- mii_rx => mii_rx,
- mii_crs => mii_crs,
- mii_col => mii_col
-
- );
-
-
-inst_emac_tx : entity work.emac_tx
- GENERIC MAP
- (
- f_sysclk => f_sysclk,
- RAM_SIZE => TX_RAM_SIZE
- )
- PORT MAP
- (
- clk => CLK_I,
- rst => RST_I,
- din_vld => tx_din_vld,
- din => tx_din,
- ctrl_in => tx_ctrl_in,
- ctrl_out => tx_ctrl_out,
- mii_tx_clk => mii_tx_clk,
- mii_tx_en => mii_tx_en,
- mii_tx_er => mii_tx_er,
- mii_tx => mii_tx
-
- );
-
-
-end behavior;
diff --git a/lib/emac/src/emac_tx.vhd b/lib/emac/src/emac_tx.vhd
deleted file mode 100644
index e397843..0000000
--- a/lib/emac/src/emac_tx.vhd
+++ /dev/null
@@ -1,751 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-use work.emac_types.all;
-use work.utils_pkg.all;
-
-ENTITY emac_tx IS
- Generic
- (
- f_sysclk : real := 100.0;
- RAM_SIZE : natural := 2048
- );
- Port
- (
- clk : in STD_LOGIC;
- rst : in STD_LOGIC;
- din_vld : in STD_LOGIC;
- din : in unsigned(31 downto 0);
- ctrl_in : in tx_ctrl_in_t;
- ctrl_out : out tx_ctrl_out_t;
- mii_tx_clk : in STD_LOGIC;
- mii_tx_en : out STD_LOGIC;
- mii_tx_er : out STD_LOGIC;
- mii_tx : out unsigned(7 downto 0)
-
- );
-END emac_tx;
-
-ARCHITECTURE behavior OF emac_tx IS
-
- constant RAM_ADDR_WIDTH : natural := NextExpBaseTwo(RAM_SIZE);
-
- subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
-
- signal cmd_fifo_din : unsigned(2*word_ptr_t'length-1 downto 0);
- signal cmd_fifo_dout : unsigned(2*word_ptr_t'length-1 downto 0);
- signal cmd_fifo_we : std_logic;
- signal cmd_fifo_re : std_logic;
- signal cmd_fifo_empty : std_logic;
- signal cmd_fifo_full : std_logic;
-
- signal reset_en : std_logic;
-
- signal fill_base : word_ptr_t;
- signal fill_size : word_ptr_t;
- signal fill_cnt : word_ptr_t;
- signal fill_ptr : word_ptr_t;
- signal fill_pre_rdy : std_logic;
- signal fill_bsy : std_logic;
- signal fill_remain : unsigned(1 downto 0);
- signal fill_set : std_logic;
- signal fill_en : std_logic;
- signal fill_cnt_en : std_logic;
-
- signal alloc_OK : std_logic;
- signal alloc_req : std_logic;
- signal alloc_ack : std_logic;
- signal alloc_size : word_ptr_t;
- signal alloc_remain : unsigned(1 downto 0);
-
- signal commit_en : std_logic;
- signal uncommit_en : std_logic;
- signal mem_alloc_en : std_logic;
- signal mem_free_en : std_logic;
- signal nwords_free : word_ptr_t;
- signal mem_free_req : std_logic;
- signal mem_free_ack : unsigned(1 downto 0);
-
- signal xfer_size : word_ptr_t;
- signal xfer_ptr : word_ptr_t;
- signal xfer_cnt : word_ptr_t;
- signal xfer_set : std_logic;
- signal xfer_en : std_logic;
- signal xfer_cnt_en : std_logic;
- signal xfer_bsy : std_logic;
- signal xfer_free_en : std_logic;
-
- signal ram_en_a : std_logic;
- signal ram_we_a : std_logic;
- signal ram_addr_a : word_ptr_t;
- signal ram_din_a : unsigned(35 downto 0);
- signal ram_en_b : std_logic;
- signal ram_addr_b : word_ptr_t;
- signal ram_dout_b : unsigned(35 downto 0);
-
- signal piso32_din : unsigned(31 downto 0);
- signal piso32_din_be : unsigned(3 downto 0);
- signal piso32_din_rdy : std_logic;
- signal piso32_din_vld : std_logic;
-
- signal piso32_dout : unsigned(7 downto 0);
- signal piso32_dout_vld : std_logic;
- signal piso32_dout_en : std_logic;
-
- signal piso8_dout_vld : std_logic;
- signal piso8_din_rdy : std_logic;
- signal piso8_din_vld : std_logic;
- signal piso8_dout : unsigned(3 downto 0);
- signal piso8_din : unsigned(7 downto 0);
-
- signal reset_pipe : unsigned(31 downto 0);
- signal Gbps_en : std_logic;
- signal fcs_gen_en : std_logic;
-
- signal fcs_inject_en : std_logic;
- signal fcs_rst : std_logic;
- signal fcs_en : unsigned(7 downto 0);
- signal fcs_vld : std_logic;
- signal fcs_din_vld : std_logic;
- signal fcs : unsigned(31 downto 0);
- signal fcs_rev_endian : unsigned(31 downto 0);
-
- signal mii_fifo_we : std_logic;
- signal mii_fifo_re : std_logic;
- signal mii_fifo_full : std_logic;
- signal mii_fifo_empty : std_logic;
- signal mii_fifo_re_dly : unsigned(23 downto 0);
-
- signal mii_bsy : std_logic;
-
- type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
- signal host_s, host_sn : host_state_t;
-
- type xfer_state_t is (xfer_init, xfer_idle, xfer_start, xfer_preamble0, xfer_preamble1, xfer_active, xfer_crc, xfer_stop, xfer_finish);
- signal xfer_s, xfer_sn : xfer_state_t;
-
- type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
- constant piso_byte_mask_rom : piso_byte_mask_array_t :=
- (
- "1111",
- "1000",
- "1100",
- "1110"
- );
-
- signal preamble_en : std_logic;
- signal preamble_addr : natural range 0 to 1;
- type preamble_t is array (0 to 1) of unsigned(31 downto 0);
- constant preamble : preamble_t :=
- (
- X"55555555",
- X"555555D5"
- );
-
-
-begin
-
- ctrl_out.pkt_alloc_req <= alloc_req;
- ctrl_out.pkt_done <= cmd_fifo_empty;
- ctrl_out.reset_busy <= reset_en;
-
- ram_en_a <= din_vld;
- ram_we_a <= fill_bsy;
- ram_din_a(31 downto 0) <= din;
- ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
- ram_addr_a <= fill_ptr;
-
- piso32_din <= preamble(preamble_addr) when preamble_en = '1' else fcs_rev_endian when fcs_inject_en = '1' else ram_dout_b(31 downto 0);
- piso32_din_be <= "1111" when (preamble_en = '1' or fcs_inject_en = '1') else ram_dout_b(35 downto 32);
-
- cmd_fifo_we <= commit_en;
- cmd_fifo_re <= uncommit_en;
- cmd_fifo_din <= fill_size & fill_base;
- ram_en_b <= piso32_din_rdy;
- ram_addr_b <= xfer_ptr;
-
- reset_en <= reset_pipe(reset_pipe'left);
-
- xfer_cnt_en <= xfer_bsy and piso32_din_rdy;
- fill_cnt_en <= fill_bsy and din_vld;
- mem_free_en <= not mem_free_ack(0) and mem_free_ack(1);
-
- fcs_rev_endian <= fcs(7 downto 0) & fcs(15 downto 8) & fcs(23 downto 16) & fcs(31 downto 24);
-
-------------------------------------------------------------------
-reset_gen:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' or ctrl_in.reset = '1' then
- reset_pipe <= (others => '1');
- else
- reset_pipe <= reset_pipe(reset_pipe'left-1 downto 0) & '0';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-host_state_next:
- process(clk)
- begin
- if rising_edge(clk) then
- if reset_en = '1' then
- host_s <= host_init;
- else
- host_s <= host_sn;
- end if;
- end if;
- end process;
-
-host_state:
- process(host_s, alloc_OK, fill_bsy, ctrl_in.pkt_commit_en, alloc_req, mem_free_ack)
- begin
-
- fill_set <= '0';
- fill_en <= '0';
- commit_en <= '0';
- alloc_ack <= '0';
- mem_alloc_en <= '0';
-
- host_sn <= host_s;
-
- case host_s is
-
- when host_init =>
- host_sn <= host_idle;
-
- when host_idle =>
- if alloc_req = '1' then
- host_sn <= host_alloc;
- end if;
-
- when host_alloc =>
- if alloc_OK = '1' then
- host_sn <= host_setup;
- else
- host_sn <= host_idle;
- alloc_ack <= '1';
- end if;
-
- when host_setup =>
- fill_set <= '1';
- host_sn <= host_arm;
-
- when host_arm =>
- fill_en <= '1';
- alloc_ack <= '1';
- host_sn <= host_fill;
-
- when host_fill =>
- fill_en <= '1';
- if alloc_req = '1' then
- host_sn <= host_alloc;
- elsif ctrl_in.pkt_commit_en = '1' then
- host_sn <= host_commit;
- end if;
-
- when host_commit =>
- if mem_free_ack = "00" then
- commit_en <= '1';
- mem_alloc_en <= '1';
- host_sn <= host_idle;
- end if;
-
- when others =>
- host_sn <= host_idle;
- end case;
-
- end process;
-
-------------------------------------------------------------------
--- Allocation stuff
-------------------------------------------------------------------
-alloc_request_logic:
- process(clk)
- begin
- if rising_edge(clk) then
- if reset_en = '1' then
- alloc_req <= '0';
- elsif ctrl_in.pkt_alloc_en = '1' and alloc_req = '0' then
- alloc_req <= '1';
- alloc_remain <= ctrl_in.tx_size(1 downto 0);
- alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2);
- if ctrl_in.tx_size(1 downto 0) /= "00" then
- alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1;
- end if;
- ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16);
- elsif alloc_ack = '1' then
- alloc_req <= '0';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-host_alloc_armed_register:
- process(clk)
- begin
- if rising_edge(clk) then
- if reset_en = '1' or commit_en = '1' then
- ctrl_out.pkt_armed <= '0';
- elsif alloc_ack = '1' then
- ctrl_out.pkt_armed <= alloc_OK;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-alloc_eval_logic:
- process(clk)
- begin
- if rising_edge(clk) then
- alloc_OK <= '0';
- if alloc_size < nwords_free then
- alloc_OK <= '1';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-fill_base_logic:
- process(clk)
- begin
- if rising_edge(clk) then
- if reset_en = '1' then
- fill_base <= (others => '0');
- elsif commit_en = '1' then
- fill_base <= fill_ptr;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-mem_free_counter:
- process(clk)
- begin
- if rising_edge(clk) then
- if reset_en = '1' then
- nwords_free <= (others => '1');
- elsif mem_alloc_en = '1' then
- nwords_free <= nwords_free - fill_size;
- elsif mem_free_en = '1' then
- nwords_free <= nwords_free + xfer_size;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-mem_free_mii:
- process(mii_tx_clk)
- begin
- if rising_edge(mii_tx_clk) then
- if reset_en = '1' then
- mem_free_req <= '0';
- elsif mem_free_ack(0) = '0' then
- if xfer_free_en = '1' then
- mem_free_req <= '1';
- end if;
- else
- mem_free_req <= '0';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-mem_free_host:
- process(clk)
- begin
- if rising_edge(clk) then
- mem_free_ack(1) <= mem_free_ack(0);
- if reset_en = '1' then
- mem_free_ack <= "00";
- elsif mem_free_req = '1' then
- if mem_alloc_en = '0' then
- mem_free_ack(0) <= '1';
- end if;
- else
- mem_free_ack(0) <= '0';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
--- Fill stuff
-------------------------------------------------------------------
-fill_counter:
- process(clk)
- begin
- if rising_edge(clk) then
- if fill_set = '1' then
- fill_bsy <= '0';
- fill_pre_rdy <= '0';
- fill_cnt <= alloc_size;
- fill_size <= alloc_size;
- fill_remain <= alloc_remain;
- elsif fill_en = '1' then
- fill_bsy <= '1';
- if fill_cnt_en = '1' or fill_bsy = '0' then
- if fill_cnt /= 1 then
- fill_cnt <= fill_cnt - 1;
- else
- fill_pre_rdy <= '1';
- end if;
- if fill_pre_rdy = '1' then
- fill_bsy <= '0';
- end if;
- end if;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-fill_pointer:
- process(clk)
- begin
- if rising_edge(clk) then
- if fill_set = '1' then
- fill_ptr <= fill_base;
- elsif fill_cnt_en = '1' then
- fill_ptr <= fill_ptr + 1;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
--- Transfer stuff
-------------------------------------------------------------------
-host2xfer_sync_register:
- process(mii_tx_clk)
- begin
- if rising_edge(mii_tx_clk) then
- Gbps_en <= ctrl_in.Gbps_en;
- fcs_gen_en <= ctrl_in.fcs_gen_en;
- end if;
- end process;
-
-------------------------------------------------------------------
-xfer_counter:
- process(mii_tx_clk)
- begin
- if rising_edge(mii_tx_clk) then
- xfer_bsy <= '0';
- if xfer_set = '1' then
- xfer_cnt <= cmd_fifo_dout(cmd_fifo_dout'left downto word_ptr_t'length);
- xfer_size <= (others => '0');
- elsif xfer_en = '1' then
- xfer_bsy <= '1';
- if xfer_cnt_en = '1' or xfer_bsy = '0' then
- if xfer_cnt /= 0 then
- xfer_cnt <= xfer_cnt - 1;
- xfer_size <= xfer_size + 1;
- else
- xfer_bsy <= '0';
- end if;
- end if;
- end if;
- end if;
-
- end process;
-
-------------------------------------------------------------------
-xfer_pointer:
- process(mii_tx_clk)
- begin
- if rising_edge(mii_tx_clk) then
- if xfer_set = '1' then
- xfer_ptr <= cmd_fifo_dout(xfer_ptr'left downto 0);
- elsif xfer_en = '1' then
- if xfer_bsy = '0' or xfer_cnt_en = '1' then
- xfer_ptr <= xfer_ptr + 1;
- end if;
- end if;
- end if;
-
- end process;
-
-------------------------------------------------------------------
-xfer_state_next:
- process(mii_tx_clk)
- begin
- if rising_edge(mii_tx_clk) then
- if reset_en = '1' then
- xfer_s <= xfer_init;
- else
- xfer_s <= xfer_sn;
- end if;
- end if;
- end process;
-
-xfer_state:
- process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en)
- begin
-
- piso32_din_vld <= '0';
- preamble_en <= '0';
- preamble_addr <= 0;
- xfer_set <= '0';
- xfer_en <= '0';
- xfer_free_en <= '0';
- fcs_rst <= '0';
- fcs_inject_en <= '0';
- uncommit_en <= '0';
-
- xfer_sn <= xfer_s;
-
- case xfer_s is
-
- when xfer_init =>
- xfer_sn <= xfer_idle;
-
- when xfer_idle =>
- if cmd_fifo_empty = '0' and mii_bsy = '0' then
- xfer_sn <= xfer_start;
- end if;
-
- when xfer_start =>
- if cmd_fifo_empty = '0' then
- xfer_sn <= xfer_preamble0;
- end if;
-
- when xfer_preamble0 =>
- xfer_set <= '1';
- fcs_rst <= '1';
- preamble_addr <= 0;
- preamble_en <= '1';
- piso32_din_vld <= '1';
- if piso32_din_rdy = '1' then
- xfer_sn <= xfer_preamble1;
- end if;
-
- when xfer_preamble1 =>
- preamble_addr <= 1;
- preamble_en <= '1';
- piso32_din_vld <= '1';
- if piso32_din_rdy = '1' then
- xfer_sn <= xfer_active;
- xfer_en <= '1';
- end if;
-
- when xfer_active =>
- piso32_din_vld <= xfer_bsy;
- xfer_en <= '1';
- if xfer_bsy = '0' then
- xfer_sn <= xfer_stop;
- end if;
-
- when xfer_stop =>
- if piso32_dout_vld = '0' then
- xfer_sn <= xfer_finish;
- if fcs_gen_en = '1' then
- xfer_sn <= xfer_crc;
- end if;
- end if;
-
- when xfer_crc =>
- fcs_inject_en <= piso32_din_rdy;
- piso32_din_vld <= '1';
- if piso32_din_rdy = '1' then
- xfer_sn <= xfer_finish;
- end if;
-
- when xfer_finish =>
- uncommit_en <= '1';
- xfer_free_en <= '1';
- xfer_sn <= xfer_idle;
-
- when others =>
- xfer_sn <= xfer_idle;
- end case;
-
- end process;
-
-------------------------------------------------------------------
-inst_ram : entity work.dpram_1w1r
- GENERIC MAP
- (
- addr_width => RAM_ADDR_WIDTH,
- data_width => ram_din_a'length
- )
- PORT MAP
- (
- clka => clk,
- clkb => mii_tx_clk,
- en_a => ram_en_a,
- en_b => ram_en_b,
- we_a => ram_we_a,
- addr_a => ram_addr_a,
- addr_b => ram_addr_b,
- din_a => ram_din_a,
- dout_b => ram_dout_b
- );
-
-------------------------------------------------------------------
--- Instantiate synchronous FIFO
-inst_cmd_fifo: entity work.fifo_async
- GENERIC MAP
- (
- addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
- data_width => cmd_fifo_din'length,
- do_last_read_update => true
- )
- PORT MAP
- (
- rst => reset_en,
- clk_w => clk,
- clk_r => mii_tx_clk,
- we => cmd_fifo_we,
- re => cmd_fifo_re,
- fifo_full => cmd_fifo_full,
- fifo_empty => cmd_fifo_empty,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => cmd_fifo_din,
- data_r => cmd_fifo_dout
- );
-
-------------------------------------------------------------------
-inst_piso32 : entity work.piso
- GENERIC MAP
- (
- data_width_in => 32,
- data_width_out => 8,
- msb_first => true
- )
- PORT MAP
- (
- rst => reset_en,
- clk => mii_tx_clk,
- din_vld => piso32_din_vld,
- din_rdy => piso32_din_rdy,
- din_be => piso32_din_be,
- din => piso32_din,
- dout_vld => piso32_dout_vld,
- dout_en => piso32_dout_en,
- dout => piso32_dout
-
- );
-
- piso32_dout_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy;
-
-------------------------------------------------------------------
-fcs_enable_gen:
- process(mii_tx_clk)
- begin
- if rising_edge(mii_tx_clk) then
- if fcs_rst = '1' then
- fcs_en <= (others => '0');
- elsif piso32_dout_vld = '1' then
- fcs_en <= fcs_en(fcs_en'left-1 downto 0) & '1';
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-inst_fcs: entity work.crc32
- GENERIC MAP
- (
- crc32_init => X"00000000"
- )
- PORT MAP
- (
- rst => fcs_rst,
- clk => mii_tx_clk,
- din_vld => fcs_din_vld,
- din => piso32_dout,
- crc32_vld => fcs_vld,
- crc32_out => fcs
-
- );
-
- fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en;
-
-------------------------------------------------------------------
--- ensures continous MII-data stream and also acts as Inter Frame Gap delay
-mii_fifo_re_dly_gen:
- process(mii_tx_clk)
- begin
- if rising_edge(mii_tx_clk) then
- if mii_fifo_empty = '1' then
- if Gbps_en = '0' then
- mii_fifo_re_dly <= X"000000"; -- 100 mbps
- else
- mii_fifo_re_dly <= X"000FFF"; -- Gigabit
- end if;
- else
- mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty;
- end if;
- end if;
- end process;
-
- mii_bsy <= mii_fifo_re_dly(mii_fifo_re_dly'left);
-
-------------------------------------------------------------------
--- Instantiate synchronous FIFO
-inst_mii_fifo: entity work.fifo_sync
- GENERIC MAP
- (
- addr_width => 4,
- data_width => piso32_dout'length,
- do_last_read_update => true
- )
- PORT MAP
- (
- rst => reset_en,
- clk => mii_tx_clk,
- we => mii_fifo_we,
- re => mii_fifo_re,
- fifo_full => mii_fifo_full,
- fifo_empty => mii_fifo_empty,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => piso32_dout,
- data_r => piso8_din
- );
-
- mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_rdy and mii_bsy);
- mii_fifo_we <= piso32_dout_vld;
-
-------------------------------------------------------------------
-inst_piso8 : entity work.piso
- GENERIC MAP
- (
- data_width_in => 8,
- data_width_out => 4,
- msb_first => false
- )
- PORT MAP
- (
- rst => reset_en,
- clk => mii_tx_clk,
- din_vld => piso8_din_vld,
- din_rdy => piso8_din_rdy,
- din_be => "11",
- din => piso8_din,
- dout_vld => piso8_dout_vld,
- dout_en => '1',
- dout => piso8_dout
-
- );
-
- piso8_din_vld <= not mii_fifo_empty and mii_bsy;
-
-------------------------------------------------------------------
-mii_output_register:
- process(mii_tx_clk)
- begin
- if rising_edge(mii_tx_clk) then
- mii_tx_er <= '0';
- if Gbps_en = '1' then
- mii_tx_en <= piso8_din_vld;
- mii_tx <= piso8_din;
- else
- mii_tx_en <= piso8_dout_vld;
- mii_tx <= "0000" & piso8_dout;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-end behavior;
diff --git a/lib/emac/src/emac_types.vhd b/lib/emac/src/emac_types.vhd
deleted file mode 100644
index 450d5be..0000000
--- a/lib/emac/src/emac_types.vhd
+++ /dev/null
@@ -1,64 +0,0 @@
--- Package File Template
---
--- Purpose: This package defines supplemental types, subtypes,
--- constants, and functions
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
-package emac_types is
-
- -- Constants
- type mac_addr_t is array (0 to 5) of unsigned (7 downto 0);
-
- -- Types
- type tx_ctrl_in_t is record
- Gbps_en : std_logic;
- reset : std_logic;
- fcs_gen_en : std_logic;
- tx_size : unsigned(15 downto 0);
- pkt_commit_en : std_logic;
- pkt_alloc_en : std_logic;
- end record;
-
- type tx_ctrl_out_t is record
- tx_size : unsigned(15 downto 0);
- pkt_done : std_logic;
- pkt_alloc_req : std_logic;
- pkt_armed : std_logic;
- reset_busy : std_logic;
- end record;
-
- type rx_ctrl_in_t is record
- Gbps_en : std_logic;
- reset : std_logic;
- fcs_chk_en : std_logic;
- pkt_read_en : std_logic;
- pkt_req_en : std_logic;
- pkt_free_en : std_logic;
- mac_addr : mac_addr_t;
- promiscious : std_logic;
- end record;
-
- type rx_ctrl_out_t is record
- pkt_avail : std_logic;
- pkt_valid : std_logic;
- pkt_bcast : std_logic;
- pkt_mac_match : std_logic;
- rx_size : unsigned(15 downto 0);
- reset_busy : std_logic;
- end record;
-
- -- Functions
-
-end emac_types;
-
-
-package body emac_types is
-
-end emac_types;
-
-
diff --git a/lib/emac/src/piso.vhd b/lib/emac/src/piso.vhd
deleted file mode 100644
index 1c27e8d..0000000
--- a/lib/emac/src/piso.vhd
+++ /dev/null
@@ -1,124 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-use work.utils_pkg.all; -- Imports the standard textio package.
-
-ENTITY piso IS
- Generic
- (
- data_width_in : natural := 32;
- data_width_out : natural := 8;
- msb_first : boolean := false
- );
- Port
- (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- din_vld : in STD_LOGIC;
- din_rdy : out STD_LOGIC;
- din_be : in unsigned(data_width_in/data_width_out-1 downto 0);
- din : in unsigned(data_width_in-1 downto 0);
- dout_vld : out STD_LOGIC;
- dout_en : in STD_LOGIC;
- dout : out unsigned(data_width_out-1 downto 0)
-
- );
-END piso;
-
-ARCHITECTURE behavior OF piso IS
-
- constant num_shifts : natural := data_width_in/data_width_out;
- signal pre_fin : STD_LOGIC;
- signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0);
- signal shift_pipe : unsigned(data_width_in-1 downto 0);
- signal vld_pipe : unsigned(num_shifts-1 downto 0);
- signal din_reg : unsigned(data_width_in-1 downto 0);
- signal din_be_reg : unsigned(num_shifts-1 downto 0);
- signal din_reg_empty : STD_LOGIC;
-
---------------------------------------------------------------------------
-begin
-
- pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1);
- din_rdy <= din_reg_empty;
- dout_vld <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
- dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
- else shift_pipe(data_width_out-1 downto 0);
-
---------------------------------------------------------------------------
-process(clk)
-begin
- if rising_edge(clk) then
- if rst = '1' then
- din_reg_empty <= '1';
- elsif din_reg_empty = '1' then
- if din_vld = '1' then
- din_reg_empty <= '0';
- end if;
- elsif pre_fin = '1' and dout_en = '1' then
- din_reg_empty <= '1';
- end if;
- end if;
-end process;
-
-process(clk)
-begin
- if rising_edge(clk) then
- if din_vld = '1' and din_reg_empty = '1' then
- din_reg <= din;
- din_be_reg <= din_be;
- end if;
- end if;
-end process;
-
-process(clk)
-begin
- if rising_edge(clk) then
- if rst = '1' then
- shift_cnt_pipe <= (others => '1');
- elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
- shift_cnt_pipe <= (others => '0');
- elsif dout_en = '1' then
- shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1';
- end if;
- end if;
-end process;
-
---------------------------------------------------------------------------
-process(clk)
-begin
- if rising_edge(clk) then
- if (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
- shift_pipe <= din_reg;
- elsif dout_en = '1' then
- if (msb_first) then
- shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
- else
- shift_pipe <= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
- end if;
- end if;
- end if;
-end process;
-
---------------------------------------------------------------------------
-process(clk)
-begin
- if rising_edge(clk) then
- if rst = '1' then
- vld_pipe <= (others => '0');
- elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
- vld_pipe <= din_be_reg;
- elsif dout_en = '1' then
- if (msb_first) then
- vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0';
- else
- vld_pipe <= '0' & vld_pipe(vld_pipe'left downto 1);
- end if;
- end if;
- end if;
-end process;
-
---------------------------------------------------------------------------
-end behavior;
diff --git a/lib/emac/src/pkt_gen.vhd b/lib/emac/src/pkt_gen.vhd
deleted file mode 100644
index fb4b303..0000000
--- a/lib/emac/src/pkt_gen.vhd
+++ /dev/null
@@ -1,230 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE IEEE.MATH_REAL.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-use work.emac_types.all;
-use work.utils_pkg.all;
-
-ENTITY pkt_gen IS
- Generic
- (
- f_sysclk : real := 100.0;
- TX_RAM_SIZE : natural := 2048;
- PKT_SIZE_MIN : natural := 64;
- PKT_SIZE_MAX : natural := 1518
-
- );
- Port
- (
- clk : in STD_LOGIC;
- rst : in STD_LOGIC;
- en : in STD_LOGIC;
- gigabit_en : in STD_LOGIC;
- fcs_gen_en : in STD_LOGIC;
- mii_tx_clk : in STD_LOGIC;
- mii_tx_en : out STD_LOGIC;
- mii_tx_er : out STD_LOGIC;
- mii_tx : out unsigned(7 downto 0)
-
- );
-END pkt_gen;
-
-ARCHITECTURE behavior OF pkt_gen IS
-
- subtype word_ptr_t is unsigned(15 downto 0);
-
- signal pkt_data : unsigned(31 downto 0);
- signal pkt_nbytes : word_ptr_t := X"0040";
- signal pkt_nwords : word_ptr_t := X"0010";
-
- signal fill_size : word_ptr_t;
- signal fill_cnt : word_ptr_t;
- signal fill_rdy : std_logic;
- signal fill_set : std_logic;
- signal fill_en : std_logic;
-
- signal tx_packets : natural;
- signal tx_bytes : natural;
-
- signal tx_ctrl_in : tx_ctrl_in_t;
- signal tx_ctrl_out : tx_ctrl_out_t;
- signal tx_din : unsigned(31 downto 0);
- signal tx_din_vld : std_logic;
-
- type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
- signal host_s, host_sn : host_state_t;
-
-begin
-
-------------------------------------------------------------------
-host_state_next:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- host_s <= host_init;
- else
- host_s <= host_sn;
- end if;
- end if;
- end process;
-
-host_state:
- process(host_s, tx_ctrl_out, pkt_nbytes, fill_rdy, en, gigabit_en, fcs_gen_en)
- begin
-
- tx_ctrl_in.pkt_alloc_en <= '0';
- tx_ctrl_in.pkt_commit_en <= '0';
- tx_ctrl_in.reset <= '0';
- tx_ctrl_in.Gbps_en <= gigabit_en;
- tx_ctrl_in.fcs_gen_en <= fcs_gen_en;
- tx_ctrl_in.tx_size <= pkt_nbytes;
- fill_set <= '0';
- fill_en <= '0';
-
- host_sn <= host_s;
-
- case host_s is
-
- when host_init =>
- if tx_ctrl_out.reset_busy = '0' then
- host_sn <= host_idle;
- end if;
-
- when host_idle =>
- if tx_ctrl_out.pkt_alloc_req = '0' and en = '1' then
- tx_ctrl_in.pkt_alloc_en <= '1';
- host_sn <= host_alloc;
- end if;
-
- when host_alloc =>
- if tx_ctrl_out.pkt_alloc_req = '0' then
- if tx_ctrl_out.pkt_armed = '1' then
- host_sn <= host_setup;
- else
- host_sn <= host_idle;
- end if;
- end if;
-
- when host_setup =>
- fill_set <= '1';
- host_sn <= host_fill;
-
- when host_fill =>
- fill_en <= '1';
- if fill_rdy = '1' then
- host_sn <= host_commit;
- end if;
-
- when host_commit =>
- tx_ctrl_in.pkt_commit_en <= '1';
- host_sn <= host_idle;
-
- when others =>
- host_sn <= host_idle;
- end case;
-
- end process;
-
-------------------------------------------------------------------
-pkt_generator:
- process(clk)
- variable size : word_ptr_t;
- variable krand : real;
- variable seed1 : integer;
- variable seed2 : integer;
-
- begin
- if rising_edge(clk) then
- if rst = '1' then
- size := to_unsigned(PKT_SIZE_MIN, word_ptr_t'length);
- seed1 := 31101970;
- seed2 := 12586901;
- tx_packets <= 0;
- tx_bytes <= 0;
- elsif tx_ctrl_in.pkt_commit_en = '1' then
- uniform(seed1, seed2, krand);
- size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
- tx_packets <= tx_packets + 1;
- tx_bytes <= tx_bytes + to_integer(pkt_nbytes);
- end if;
- pkt_nbytes <= size;
- if size(1 downto 0) = 0 then
- pkt_nwords <= "00" & size(word_ptr_t'left downto 2);
- else
- pkt_nwords <= "00" & size(word_ptr_t'left downto 2) + 1;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------
-pkt_data_gen:
- process(clk)
- variable data : unsigned(7 downto 0);
- begin
- if rising_edge(clk) then
- tx_din_vld <= fill_en;
- if fill_set = '1' then
- data := X"00";
- tx_din <= X"03020100";
- elsif fill_en = '1' then
- tx_din(7 downto 0) <= data;
- data := data + 1;
- tx_din(15 downto 8) <= data;
- data := data + 1;
- tx_din(23 downto 16) <= data;
- data := data + 1;
- tx_din(31 downto 24) <= data;
- data := data + 1;
- end if;
- end if;
-
- end process;
-
-------------------------------------------------------------------
-pkt_data_counter:
- process(clk)
- begin
- if rising_edge(clk) then
- if fill_set = '1' then
- fill_size <= (others => '0');
- fill_rdy <= '0';
- fill_cnt <= pkt_nwords;
- elsif fill_en = '1' then
- if fill_cnt /= 0 then
- fill_cnt <= fill_cnt - 1;
- fill_size <= fill_size + 1;
- else
- fill_rdy <= '1';
- end if;
- end if;
- end if;
-
- end process;
-
-------------------------------------------------------------------
-inst_emac_tx : entity work.emac_tx
- GENERIC MAP
- (
- f_sysclk => f_sysclk,
- RAM_SIZE => TX_RAM_SIZE
- )
- PORT MAP
- (
- clk => clk,
- rst => rst,
- din_vld => tx_din_vld,
- din => tx_din,
- ctrl_in => tx_ctrl_in,
- ctrl_out => tx_ctrl_out,
- mii_tx_clk => mii_tx_clk,
- mii_tx_en => mii_tx_en,
- mii_tx_er => mii_tx_er,
- mii_tx => mii_tx
-
- );
-
-
-end behavior;
diff --git a/lib/emac/src/shifter.vhd b/lib/emac/src/shifter.vhd
deleted file mode 100644
index e988e63..0000000
--- a/lib/emac/src/shifter.vhd
+++ /dev/null
@@ -1,111 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-use work.utils_pkg.all; -- Imports the standard textio package.
-
-ENTITY shifter IS
- Generic
- (
- data_width : natural := 32;
- aggregate_size : natural := 8;
- do_pipelined : boolean := true
- );
- Port
- (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- sa : in integer;
- din_vld : in STD_LOGIC;
- din : in unsigned(data_width-1 downto 0);
- dout_vld : out STD_LOGIC;
- dout : out unsigned(data_width-1 downto 0)
-
- );
-END shifter;
-
-ARCHITECTURE behavior OF shifter IS
-
- constant num_rounds : natural := NextExpBaseTwo(data_width/aggregate_size);
- subtype sa_rnd_t is signed(num_rounds-1 downto 0);
- subtype word_t is unsigned(data_width-1 downto 0);
- type word_array_t is array (0 to num_rounds) of word_t;
-
- signal rot_data : word_array_t;
- signal sa_rnd : sa_rnd_t;
-
- type sa_rnd_array_t is array (0 to num_rounds) of sa_rnd_t;
- signal sa_rnd_pipe : sa_rnd_array_t;
- signal dout_vld_pipe : unsigned(0 to num_rounds);
-
---------------------------------------------------------------------------
-function rol_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
- variable result : unsigned(x'range);
- constant sa : natural := (2**stage_num) * size;
- begin
- if en = '1' then
- result := x(x'left-sa downto 0) & x(x'left downto x'length-sa);
- else
- result := x;
- end if;
- return result;
-end rol_stage;
-
---------------------------------------------------------------------------
-begin
-
---------------------------------------------------------------------------
-gen_non_pipelined:
-if do_pipelined = false generate
-begin
-
- rot_data(0) <= din;
-
-gen_rotate_right:
- for stage in 0 to num_rounds-1 generate
- begin
- rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size);
- end generate;
-
- sa_rnd <= to_signed(sa, num_rounds);
- dout <= rot_data(num_rounds);
- dout_vld <= din_vld;
-
-end generate;
-
---------------------------------------------------------------------------
-gen_pipelined:
-if do_pipelined = true generate
-begin
-
- rot_data(0) <= din;
- sa_rnd_pipe(0) <= to_signed(sa, num_rounds);
- dout_vld_pipe(0) <= din_vld;
-
-gen_rotate_right:
- for stage in 0 to num_rounds-1 generate
- begin
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- dout_vld_pipe(stage+1) <= '0';
- else
- dout_vld_pipe(stage+1) <= dout_vld_pipe(stage);
- if dout_vld_pipe(stage) = '1' then
- sa_rnd_pipe(stage+1) <= sa_rnd_pipe(stage);
- rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- dout <= rot_data(num_rounds);
- dout_vld <= dout_vld_pipe(num_rounds);
-
-end generate;
-
---------------------------------------------------------------------------
-end behavior;
diff --git a/lib/emac/src/sipo.vhd b/lib/emac/src/sipo.vhd
deleted file mode 100644
index 03c1005..0000000
--- a/lib/emac/src/sipo.vhd
+++ /dev/null
@@ -1,118 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-use work.utils_pkg.all; -- Imports the standard textio package.
-
-ENTITY sipo IS
- Generic
- (
- data_width_in : natural := 8;
- data_width_out : natural := 32;
- msb_first : boolean := false
- );
- Port
- (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- din_en : in STD_LOGIC;
- din_vld : in STD_LOGIC;
- din : in unsigned(data_width_in-1 downto 0);
- dout_en : out STD_LOGIC;
- dout_vld : out STD_LOGIC;
- dout : out unsigned(data_width_out-1 downto 0);
- dout_be : out unsigned(data_width_out/data_width_in-1 downto 0)
-
- );
-END sipo;
-
-ARCHITECTURE behavior OF sipo IS
-
- constant num_shifts : natural := data_width_out/data_width_in;
- signal pre_fin : STD_LOGIC;
- signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0);
- signal shift_pipe : unsigned(data_width_out-1 downto 0);
- signal out_en : STD_LOGIC;
- signal out_vld : STD_LOGIC;
- signal din_vld_r : STD_LOGIC;
- signal abort : STD_LOGIC;
-
---------------------------------------------------------------------------
-begin
-
- pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left) when msb_first else shift_cnt_pipe(0);
- dout_en <= out_en;
- dout_vld <= out_vld;
-
---------------------------------------------------------------------------
-process(clk)
-begin
- if rising_edge(clk) then
- if rst = '1' or pre_fin = '1' then
- abort <= '0';
- elsif din_vld_r = '1' and din_en = '0' then
- abort <= '1';
- end if;
- end if;
-end process;
-
-process(clk)
-begin
- if rising_edge(clk) then
- din_vld_r <= din_vld and din_en;
- if rst = '1' then
- out_en <= '0';
- elsif out_en = '0' then
- out_en <= pre_fin and din_en;
- elsif out_vld = '1' then
- out_en <= din_en;
- end if;
- end if;
-end process;
-
-process(clk)
-begin
- if rising_edge(clk) then
- out_vld <= pre_fin;
- if pre_fin = '1' then
- dout <= shift_pipe;
- dout_be <= shift_cnt_pipe;
- end if;
- end if;
-end process;
-
-process(clk)
-begin
- if rising_edge(clk) then
- if rst = '1' or pre_fin = '1' then
- if (msb_first) then
- shift_cnt_pipe <= (shift_cnt_pipe'left downto 1 => '0') & (din_en and din_vld);
- else
- shift_cnt_pipe <= (din_en and din_vld) & (shift_cnt_pipe'left downto 1 => '0');
- end if;
- elsif din_vld = '1' or abort = '1' then
- if (msb_first) then
- shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & din_en;
- else
- shift_cnt_pipe <= din_en & shift_cnt_pipe(shift_cnt_pipe'left downto 1);
- end if;
- end if;
- end if;
-end process;
-
-process(clk)
-begin
- if rising_edge(clk) then
- if din_vld = '1' or abort = '1' then
- if (msb_first) then
- shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
- else
- shift_pipe <= din & shift_pipe(shift_pipe'left downto data_width_in);
- end if;
- end if;
- end if;
-end process;
-
---------------------------------------------------------------------------
-end behavior;
diff --git a/lib/emac/src/tb_crc32.vhd b/lib/emac/src/tb_crc32.vhd
deleted file mode 100644
index ad49ca3..0000000
--- a/lib/emac/src/tb_crc32.vhd
+++ /dev/null
@@ -1,106 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_crc32 IS
-END tb_crc32;
-
-ARCHITECTURE behavior OF tb_crc32 IS
-
- constant CLK_PERIOD : time := 10 ns;
-
- signal CLK : std_logic := '1';
- signal RST : std_logic := '1';
-
- signal din_vld : std_logic := '0';
- signal din : unsigned(7 downto 0) := (others => '-');
- signal crc32 : unsigned(31 downto 0);
- signal crc32_vld : std_logic;
-
-
- type byte_array_t is array (0 to 61) of unsigned(7 downto 0);
-
- signal test_data : byte_array_t :=
- (
- X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12",
- X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
- X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11",
- X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
- X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C",
- X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
- X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D",
- X"0E", X"0F", X"10", X"11", X"12", X"13"
- );
-
-BEGIN
-
-inst_crc32: entity work.crc32
- PORT MAP
- (
- rst => RST,
- clk => CLK,
- din_vld => din_vld,
- din => din,
- crc32_vld => crc32_vld,
- crc32_out => crc32
-
- );
-
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- CLK <= not CLK;
- end process;
-
-
--- Master
-STIMULUS: process
-
-
- begin
-
- wait for 6*CLK_PERIOD;
- RST <= '0';
- wait for 6*CLK_PERIOD;
-
- wait until rising_edge(CLK);
-
- for i in 0 to 61 loop
- din_vld <= '1';
- din <= test_data(i);
- wait until rising_edge(CLK);
- end loop;
-
- din <= (others => '-');
- din_vld <= '0';
-
- wait;
-
- end process;
-
-END;
diff --git a/lib/emac/src/tb_emac_jb.vhd b/lib/emac/src/tb_emac_jb.vhd
deleted file mode 100644
index 1f16310..0000000
--- a/lib/emac/src/tb_emac_jb.vhd
+++ /dev/null
@@ -1,224 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_serdes IS
-END tb_serdes;
-
-ARCHITECTURE behavior OF tb_serdes IS
-
- constant CLK_PERIOD : time := 10 ns;
-
- signal CLK : std_logic := '1';
- signal RST : std_logic := '1';
-
- signal piso_din_vld : std_logic := '0';
- signal piso_din_rdy : std_logic;
- signal piso_din_be : unsigned(3 downto 0) := (others => '0');
- signal piso_din : unsigned(31 downto 0) := (others => '-');
- signal piso_dout_vld : std_logic;
- signal piso_dout : unsigned(7 downto 0);
- signal piso_dout_en : std_logic;
-
- signal piso2_din_vld : std_logic := '0';
- signal piso2_din_rdy : std_logic;
- signal piso2_din_be : unsigned(1 downto 0) := (others => '1');
- signal piso2_din : unsigned(7 downto 0) := (others => '-');
- signal piso2_dout_vld : std_logic;
- signal piso2_dout : unsigned(3 downto 0);
- signal piso2_dout_en : std_logic;
-
- signal sipo_enable : std_logic := '0';
- signal sipo_rst : std_logic := '0';
- signal sipo_din_vld : std_logic := '0';
- signal sipo_din : unsigned(7 downto 0) := (others => '-');
- signal sipo_dout_vld : std_logic;
- signal sipo_dout_en : std_logic;
- signal sipo_dout_be : unsigned(3 downto 0);
- signal sipo_dout : unsigned(31 downto 0);
-
- signal sipo2_enable : std_logic := '0';
- signal sipo2_rst : std_logic := '0';
- signal sipo2_din_vld : std_logic := '0';
- signal sipo2_din : unsigned(3 downto 0) := (others => '-');
- signal sipo2_dout_vld : std_logic;
- signal sipo2_dout_en : std_logic;
- signal sipo2_dout_be : unsigned(1 downto 0);
- signal sipo2_dout : unsigned(7 downto 0);
-
-
-BEGIN
-
-inst_piso : entity work.piso
- GENERIC MAP
- (
- data_width_in => 32,
- data_width_out => 8,
- msb_first => true
- )
- PORT MAP
- (
- rst => RST,
- clk => CLK,
- din_vld => piso_din_vld,
- din_rdy => piso_din_rdy,
- din_be => piso_din_be,
- din => piso_din,
- dout_vld => piso_dout_vld,
- dout_en => piso_dout_en,
- dout => piso_dout
-
- );
-
- piso_dout_en <= piso2_din_rdy;
-
-inst_piso2 : entity work.piso
- GENERIC MAP
- (
- data_width_in => 8,
- data_width_out => 4,
- msb_first => true
- )
- PORT MAP
- (
- rst => RST,
- clk => CLK,
- din_vld => piso2_din_vld,
- din_rdy => piso2_din_rdy,
- din_be => piso2_din_be,
- din => piso2_din,
- dout_vld => piso2_dout_vld,
- dout_en => piso2_dout_en,
- dout => piso2_dout
-
- );
-
- piso2_din_vld <= piso_dout_vld;
- piso2_dout_en <= '1';
- piso2_din <= piso_dout;
-
-inst_sipo : entity work.sipo
- GENERIC MAP
- (
- data_width_in => 8,
- data_width_out => 32,
- msb_first => true
- )
- PORT MAP
- (
- rst => RST,
- clk => CLK,
- din_en => sipo_enable,
- din_vld => sipo_din_vld,
- din => sipo_din,
- dout_be => sipo_dout_be,
- dout_vld => sipo_dout_vld,
- dout => sipo_dout,
- dout_en => sipo_dout_en
-
- );
- sipo_din <= sipo2_dout;
- sipo_din_vld <= sipo2_dout_vld;
- sipo_enable <= sipo2_dout_en;
- sipo_rst <= RST or not piso2_dout_vld;
-
-inst_sipo2 : entity work.sipo
- GENERIC MAP
- (
- data_width_in => 4,
- data_width_out => 8,
- msb_first => true
- )
- PORT MAP
- (
- rst => RST,
- clk => CLK,
- din_en => sipo2_enable,
- din_vld => sipo2_din_vld,
- din => sipo2_din,
- dout_be => sipo2_dout_be,
- dout_vld => sipo2_dout_vld,
- dout => sipo2_dout,
- dout_en => sipo2_dout_en
-
- );
- sipo2_din <= piso2_dout;
- sipo2_din_vld <= piso2_dout_vld;
- sipo2_enable <= sipo2_din_vld;
- sipo_rst <= RST or not piso2_dout_vld;
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- CLK <= not CLK;
- end process;
-
-
--- Master
-STIMULUS: process
-
-
- begin
-
- wait for 600*CLK_PERIOD;
- RST <= '0';
- wait for 60*CLK_PERIOD;
-
- for i in 1 to 10 loop
-
- wait until rising_edge(CLK);
- piso_din_vld <= '1';
- piso_din <= X"12345678";
- piso_din_be <= "1111";
- wait until rising_edge(CLK) and piso_din_rdy = '1';
- piso_din <= piso_din + X"12345678";
- piso_din_be <= "1111";
- wait until rising_edge(CLK) and piso_din_rdy = '1';
- piso_din <= piso_din + X"12345678";
- piso_din_be <= "1111";
- wait until rising_edge(CLK) and piso_din_rdy = '1';
- piso_din <= piso_din + X"12345678";
- piso_din_be <= "1100";
- wait until rising_edge(CLK) and piso_din_rdy = '1';
- piso_din <= (others => '-');
- piso_din_vld <= '0';
-
-
- wait until rising_edge(CLK) and piso_dout_vld = '0';
-
--- wait until rising_edge(CLK);
--- wait until rising_edge(CLK) and sipo_dout_vld = '1';
---
- wait for 33*CLK_PERIOD;
-
- end loop;
-
- wait;
-
- end process;
-
-END;
diff --git a/lib/emac/src/tb_emac_top_jb.vhd b/lib/emac/src/tb_emac_top_jb.vhd
deleted file mode 100644
index b32ae9c..0000000
--- a/lib/emac/src/tb_emac_top_jb.vhd
+++ /dev/null
@@ -1,655 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_emac_top_jb IS
-END tb_emac_top_jb;
-
-ARCHITECTURE behavior OF tb_emac_top_jb IS
-
- constant CLK_PERIOD : time := 10 ns;
- constant MII_CLK_PERIOD : time := 37.7 ns;
-
- signal CLK : std_logic := '1';
- signal RST : std_logic := '1';
-
- -- Slave
- signal CYC_I : std_logic := '0';
- signal STB_I : std_logic := '0';
- signal WE_I : std_logic := '0';
- signal SEL_I : unsigned(3 downto 0) := (others => '1');
- signal ACK_O : std_logic;
- signal INT_O : std_logic;
- signal MRDY_I : std_logic := '0';
- signal SRDY_O : std_logic;
- signal ADDR_I : unsigned(31 downto 0) := (others => '-');
- signal DAT_I : unsigned(31 downto 0) := (others => '-');
- signal DAT_O : unsigned(31 downto 0) := (others => '-');
- signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
- signal status_reg : unsigned(31 downto 0) := (others => '0');
- signal size_reg : unsigned(31 downto 0) := (others => '0');
-
- -- MII signals
- signal mii_rx_clk_board : std_logic := '1';
- signal mii_tx_clk_board : std_logic := '1';
- signal mii_rx_clk : std_logic := '1';
- signal mii_tx_clk : std_logic := '1';
- signal mii_rx : unsigned(7 downto 0) := (others => '-');
- signal mii_tx : unsigned(7 downto 0);
- signal mii_rx_dv : std_logic := '0';
- signal mii_rx_er : std_logic := '0';
- signal mii_tx_en : std_logic;
- signal mii_tx_er : std_logic;
- signal mii_crs : std_logic := '0';
- signal mii_col : std_logic := '0';
- signal mii_gtx_clk : std_logic;
-
- signal loop_back_en : std_logic := '0';
-
- signal pktgen_tx : unsigned(7 downto 0);
- signal pktgen_tx_en : std_logic;
- signal pktgen_tx_er : std_logic;
- signal pktgen_en : std_logic := '0';
- signal pktgen_gigabit : std_logic := '0';
- signal pktgen_fcs_en : std_logic := '0';
- signal dat_o_cnt_en : std_logic := '0';
- signal dat_o_cnt_rst : std_logic := '1';
- signal dat_o_cnt : natural;
- signal pkt_count : natural;
-
- type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
- signal emac_action : emac_action_t;
-
- constant RX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0000";
- constant RX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_0004";
- constant TX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0008";
- constant TX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_000C";
- constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_8000";
-
-BEGIN
-
-inst_emac_top_jb : entity work.emac_top_jb
- GENERIC MAP
- (
- f_sysclk => 100.0,
- RX_RAM_SIZE => 2048,
- TX_RAM_SIZE => 2048
- )
- PORT MAP
- (
- CLK_I => CLK,
- RST_I => RST,
- INT_O => INT_O,
- CYC_I => CYC_I,
- STB_I => STB_I,
- SEL_I => SEL_I,
- WE_I => WE_I,
- ACK_O => ACK_O,
- SRDY_O => SRDY_O,
- MRDY_I => MRDY_I,
- ADDR_I => ADDR_I,
- DAT_I => DAT_I,
- DAT_O => DAT_O,
- mii_rx_clk => mii_rx_clk_board,
- mii_rx_dv => mii_rx_dv,
- mii_rx_er => mii_rx_er,
- mii_rx => mii_rx,
- mii_tx_clk => mii_tx_clk_board,
- mii_tx_en => mii_tx_en,
- mii_tx_er => mii_tx_er,
- mii_tx => mii_tx,
- mii_gtx_clk => mii_gtx_clk,
- mii_crs => mii_crs,
- mii_col => mii_col
-
- );
-
-inst_pkt_gen : entity work.pkt_gen
- GENERIC MAP
- (
- f_sysclk => 100.0,
- PKT_SIZE_MIN => 64,
- PKT_SIZE_MAX => 1512
-
- )
- PORT MAP
- (
- clk => CLK,
- rst => RST,
- en => pktgen_en,
- gigabit_en => pktgen_gigabit,
- fcs_gen_en => pktgen_fcs_en,
- mii_tx_clk => mii_tx_clk_board,
- mii_tx_en => pktgen_tx_en,
- mii_tx_er => pktgen_tx_er,
- mii_tx => pktgen_tx
-
- );
-
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- CLK <= not CLK;
- end process;
-
-MII_CLK_GEN: process
- begin
- wait for MII_CLK_PERIOD/2;
- mii_rx_clk <= not mii_rx_clk;
- mii_tx_clk <= not mii_tx_clk;
- end process;
-
- mii_rx_clk_board <= mii_rx_clk;
- mii_tx_clk_board <= mii_tx_clk;
-
-DAT_O_register:
- process(CLK)
- begin
- if rising_edge(CLK) then
- if ACK_O = '1' then
- DAT_O_reg <= DAT_O;
- end if;
- end if;
- end process;
-
-DAT_O_count_register:
- process(CLK)
- begin
- if rising_edge(CLK) then
- if dat_o_cnt_rst = '1' then
- dat_o_cnt <= 0;
- elsif ACK_O = '1' and dat_o_cnt_en = '1' then
- dat_o_cnt <= dat_o_cnt + 1;
- end if;
- end if;
- end process;
-
- mii_rx <= mii_tx when loop_back_en = '1' else pktgen_tx;
- mii_rx_dv <= mii_tx_en when loop_back_en = '1' else pktgen_tx_en;
- mii_rx_er <= mii_tx_er when loop_back_en = '1' else pktgen_tx_er;
- mii_crs <= '0';
- mii_col <= '0';
-
--- Master
-STIMULUS: process
-
- procedure emac_tx_reset_100mbps is
- begin
-
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- DAT_I <= X"A000_0000";
- STB_I <= '1';
- WE_I <= '1';
- ADDR_I <= TX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- WE_I <= '0';
-
- end procedure emac_tx_reset_100mbps;
-
- procedure emac_rx_reset_100mbps is
- begin
-
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- DAT_I <= X"A000_0000";
- STB_I <= '1';
- WE_I <= '1';
- ADDR_I <= RX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- WE_I <= '0';
-
- end procedure emac_rx_reset_100mbps;
-
- procedure emac_tx_reset_1000mbps is
- begin
-
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- DAT_I <= X"E000_0000";
- STB_I <= '1';
- WE_I <= '1';
- ADDR_I <= TX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- WE_I <= '0';
-
- end procedure emac_tx_reset_1000mbps;
-
- procedure emac_rx_reset_1000mbps is
- begin
-
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- DAT_I <= X"E000_0000";
- STB_I <= '1';
- WE_I <= '1';
- ADDR_I <= RX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- WE_I <= '0';
-
- end procedure emac_rx_reset_1000mbps;
-
- procedure emac_alloc (size : natural) is
- begin
-
- -- TX-ALLOCATION
- -- set TX-size
- emac_action <= emac_alloc;
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- DAT_I <= to_unsigned(size, 32);
- STB_I <= '1';
- WE_I <= '1';
- ADDR_I <= TX_SIZE_REG_ADDR;
-
- check_alloc_ok:
- while(true) loop
-
- -- set alloc request
- wait until rising_edge(CLK) and SRDY_O = '1';
- WE_I <= '0';
- STB_I <= '1';
- ADDR_I <= TX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- wait until rising_edge(CLK) and ACK_O = '1';
- status_reg <= DAT_O;
- wait until rising_edge(CLK) and SRDY_O = '1';
- DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
- STB_I <= '1';
- WE_I <= '1';
- ADDR_I <= TX_STATUS_REG_ADDR;
-
- check_bsy:
- while (true) loop
- wait until rising_edge(CLK) and SRDY_O = '1';
- WE_I <= '0';
- STB_I <= '1';
- ADDR_I <= TX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- wait until rising_edge(CLK) and ACK_O = '1';
- status_reg <= DAT_O;
- wait until rising_edge(CLK);
- if status_reg(17) = '0' then
- exit check_bsy;
- end if;
- end loop;
- if status_reg(16) = '1' then
- exit check_alloc_ok;
- end if;
- end loop;
- CYC_I <= '0';
-
- emac_action <= emac_idle;
-
- end procedure emac_alloc;
-
- procedure emac_commit is
- begin
-
- -- RX- DEALLOCATION
- emac_action <= emac_commit;
-
- -- set free request
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- WE_I <= '0';
- STB_I <= '1';
- ADDR_I <= TX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- wait until rising_edge(CLK) and ACK_O = '1';
- status_reg <= DAT_O;
- wait until rising_edge(CLK) and SRDY_O = '1';
- DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
- STB_I <= '1';
- WE_I <= '1';
- ADDR_I <= TX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- WE_I <= '0';
-
- emac_action <= emac_idle;
-
- end procedure emac_commit;
-
- procedure emac_write (size : natural) is
- variable data : unsigned (7 downto 0);
- variable num_words : natural;
- begin
-
- -- FILL TX data
- emac_action <= emac_write;
- if (size mod 4) = 0 then
- num_words := size/4;
- else
- num_words := size/4 + 1;
- end if;
-
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- data := X"00";
- ADDR_I <= DATA_REG_ADDR;
- WE_I <= '1';
- for i in 1 to num_words loop
- STB_I <= '1';
- DAT_I(7 downto 0) <= data;
- data := data + 1;
- DAT_I(15 downto 8) <= data;
- data := data + 1;
- DAT_I(23 downto 16) <= data;
- data := data + 1;
- DAT_I(31 downto 24) <= data;
- data := data + 1;
- wait until rising_edge(CLK) and SRDY_O = '1';
- end loop;
-
- STB_I <= '0';
- wait until rising_edge(CLK) and SRDY_O = '1';
-
- emac_commit;
-
- emac_action <= emac_idle;
-
- end procedure emac_write;
-
- procedure emac_read (size_in : natural) is
- variable data : unsigned (7 downto 0);
- variable size, num_words : natural;
- begin
-
- emac_action <= emac_wait_data;
-
- -- check if data available
- check_data_avail:
- while (true) loop
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- WE_I <= '0';
- STB_I <= '1';
- ADDR_I <= RX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- wait until rising_edge(CLK) and ACK_O = '1';
- status_reg <= DAT_O;
- wait until rising_edge(CLK);
- if status_reg(17) = '1' and status_reg(16) = '1' then
- exit check_data_avail;
- end if;
- end loop;
-
- read_size:
- dat_o_cnt_rst <= '1';
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- WE_I <= '0';
- STB_I <= '1';
- ADDR_I <= RX_SIZE_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- wait until rising_edge(CLK) and ACK_O = '1';
- size_reg <= DAT_O;
- wait until rising_edge(CLK);
-
- -- set packet request
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- WE_I <= '0';
- STB_I <= '1';
- ADDR_I <= RX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- wait until rising_edge(CLK) and ACK_O = '1';
- status_reg <= DAT_O;
- wait until rising_edge(CLK) and SRDY_O = '1';
- DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
- STB_I <= '1';
- WE_I <= '1';
- ADDR_I <= RX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- WE_I <= '0';
-
- emac_action <= emac_read;
- -- Read RX data
- size := size_in;
- if (size_in = 0) then
- size := to_integer(size_reg(15 downto 0));
- end if;
-
- if (size mod 4) = 0 then
- num_words := size/4;
- else
- num_words := size/4 + 1;
- end if;
-
- dat_o_cnt_rst <= '0';
- dat_o_cnt_en <= '1';
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- ADDR_I <= DATA_REG_ADDR;
- WE_I <= '0';
- STB_I <= '1';
- for i in 1 to num_words loop
- wait until rising_edge(CLK) and SRDY_O = '1';
- end loop;
- STB_I <= '0';
- wait until rising_edge(CLK) and dat_o_cnt = num_words;
- dat_o_cnt_en <= '0';
- emac_action <= emac_idle;
-
- end procedure emac_read;
-
- procedure emac_free is
- begin
-
- -- RX- DEALLOCATION
- emac_action <= emac_free;
-
- -- set free request
- CYC_I <= '1';
- wait until rising_edge(CLK) and SRDY_O = '1';
- WE_I <= '0';
- STB_I <= '1';
- ADDR_I <= RX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- wait until rising_edge(CLK) and ACK_O = '1';
- status_reg <= DAT_O;
- wait until rising_edge(CLK) and SRDY_O = '1';
- DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
- STB_I <= '1';
- WE_I <= '1';
- ADDR_I <= RX_STATUS_REG_ADDR;
- wait until rising_edge(CLK) and SRDY_O = '1';
- STB_I <= '0';
- WE_I <= '0';
-
- emac_action <= emac_idle;
-
- end procedure emac_free;
-
- begin
-
- wait for 6*MII_CLK_PERIOD;
- RST <= '0';
- wait for 60*CLK_PERIOD;
- emac_rx_reset_100mbps;
- emac_tx_reset_100mbps;
- pktgen_gigabit <= '0';
- pktgen_fcs_en <= '1';
- wait for 60*CLK_PERIOD;
-
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
- emac_alloc (1004);
-
- for i in 1 to 10 loop
- for j in 1 to 100 loop
- emac_alloc (72);
- emac_write (72);
- end loop;
- wait for 1 ms;
- end loop;
-
- wait until rising_edge(mii_tx_clk) and mii_tx_en = '0';
- wait for 6000*CLK_PERIOD;
-
- loop_back_en <= '1';
-
- emac_alloc (74);
- emac_write (74);
-
- emac_alloc (105);
- emac_write (105);
-
- emac_read (0);
- emac_free;
-
- emac_read (0);
- emac_free;
-
- emac_alloc (103);
- emac_write (103);
-
- emac_read (0);
- emac_free;
-
- emac_alloc (71);
- emac_write (71);
-
- emac_read (0);
- emac_free;
-
- emac_alloc (82);
- emac_write (82);
-
- emac_alloc (86);
- emac_write (86);
-
- emac_read (0);
- emac_free;
-
- emac_read (0);
- emac_free;
-
- emac_alloc (77);
- emac_write (77);
-
- emac_alloc (99);
- emac_write (99);
-
- emac_alloc (65);
- emac_write (65);
-
- emac_alloc (321);
- emac_write (321);
-
- emac_read (0);
- emac_free;
-
- emac_alloc (1111);
- emac_write (1111);
-
- emac_read (0);
- emac_free;
-
- emac_alloc (73);
- emac_write (73);
-
- emac_alloc (107);
- emac_write (107);
-
- emac_alloc (83);
- emac_write (83);
-
- emac_read (0);
- emac_free;
-
- emac_alloc (72);
- emac_write (72);
-
- emac_alloc (1003);
- emac_write (1003);
-
- emac_read (0);
- emac_free;
-
- emac_read (0);
- emac_free;
-
- emac_read (0);
- emac_free;
-
- emac_read (0);
- emac_free;
-
- emac_read (0);
- emac_free;
-
- emac_read (0);
- emac_free;
-
- emac_read (0);
- emac_free;
-
- wait for 6000*CLK_PERIOD;
-
- loop_back_en <= '0';
- pktgen_en <= '1';
- pkt_count <= 0;
- for i in 1 to 500 loop
- wait for 1 us;
- emac_read (0);
- emac_free;
- pkt_count <= pkt_count + 1;
- end loop;
- pktgen_en <= '0';
- emac_read (0);
- emac_free;
-
-
- wait;
-
- end process;
-
-END;
diff --git a/lib/filter/sim/eval_lowpass.m b/lib/filter/sim/eval_lowpass.m
deleted file mode 100644
index ccac021..0000000
--- a/lib/filter/sim/eval_lowpass.m
+++ /dev/null
@@ -1,37 +0,0 @@
-function eval_filter(N)
-omega_lp = 0.15
-omega_hp = 0.05
-
-omega_bp_m = 0.02;
-bw2_bp = 0.02;
-
-lp = lowpass(N, omega_lp, 1.0);
-coef_lp = hann(N)'.*lp./sum(lp.^2);
-
-hp = lowpass(N, 0.5-omega_hp, 1.0).*cos(pi*(0:N-1));
-coef_hp = hp./sum(hp.^2).*hann(N)';
-
-bp = lowpass(N, bw2_bp/2, 1.0).*cos(2*pi*omega_bp_m*(0:N-1));
-coef_bp = bp./sum(bp.^2).*hann(N)';
-
-abs_lp = 20*log10(abs(fft(coef_lp)));
-abs_hp = 20*log10(abs(fft(coef_hp)));
-abs_bp = 20*log10(abs(fft(coef_bp)));
-
-close all;
-plot((0:N/2)/N, abs_lp(1:N/2+1));grid;
-figure
-plot((0:N/2)/N, abs_hp(1:N/2+1));grid;
-figure
-plot((0:N/2)/N, abs_bp(1:N/2+1));grid;
-
-figure
-plot((0:N-1), coef_lp);grid;
-figure
-plot((0:N-1), coef_hp);grid;
-figure
-plot((0:N-1), coef_bp);grid;
-
-mean_lp = mean(coef_lp-mean(coef_lp))
-mean_hp = mean(coef_hp)
-mean_bp = mean(coef_bp)
diff --git a/lib/filter/sim/lowpass.m b/lib/filter/sim/lowpass.m
deleted file mode 100644
index 292964d..0000000
--- a/lib/filter/sim/lowpass.m
+++ /dev/null
@@ -1,20 +0,0 @@
-function coef = lowpass(N, omega, scale)
-
-phi = 0;
-dphi = 2*omega;
-if (mod(N, 2) == 0)
- M = N/2;
- for i=0:M-1,
- phi = phi + dphi;
- coef(M+i+1) = scale*sinc(phi);
- coef(M-i-1+1) = coef(M+i+1);
- end;
-else
- M = (N-1)/2;
- for i=1:M,
- phi = phi + dphi;
- coef(M+i+1) = scale*sinc(phi);
- coef(M-i+1) = coef(M+i+1);
- end;
- coef(M+1) = scale*Sinc(0.0);
-end;
diff --git a/lib/filter/sim/tb_fir_iterative.fdo b/lib/filter/sim/tb_fir_iterative.fdo
deleted file mode 100644
index 5260669..0000000
--- a/lib/filter/sim/tb_fir_iterative.fdo
+++ /dev/null
@@ -1,18 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/filter_pkg.vhd"
-vcom -explicit -93 "../src/fir_pkg.vhd"
-vcom -explicit -93 "../src/fir_stage.vhd"
-vcom -explicit -93 "../src/fir_iterative.vhd"
-vcom -explicit -93 "../src/tb_fir_iterative.vhd"
-vsim -t 1ps -lib work tb_fir_iterative
-do {tb_fir_iterative.wdo}
-view wave
-view structure
-view signals
-run 20us
diff --git a/lib/filter/sim/tb_fir_iterative.wdo b/lib/filter/sim/tb_fir_iterative.wdo
deleted file mode 100644
index cb193af..0000000
--- a/lib/filter/sim/tb_fir_iterative.wdo
+++ /dev/null
@@ -1,144 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
-add wave -noupdate -format Literal /tb_fir_iterative/coeffs
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
-add wave -noupdate -format Literal /tb_fir_iterative/xi
-add wave -noupdate -format Literal /tb_fir_iterative/yo
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem
-add wave -noupdate -divider {Xmem Dual}
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
-add wave -noupdate -format Literal /tb_fir_iterative/coeffs
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
-add wave -noupdate -format Logic /tb_fir_iterative/y_valid
-add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
-add wave -noupdate -divider {FIR Stage}
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
-add wave -noupdate -format Literal /tb_fir_iterative/coeffs
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
-add wave -noupdate -format Literal /tb_fir_iterative/xi
-add wave -noupdate -format Literal /tb_fir_iterative/yo
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem
-add wave -noupdate -divider {Xmem Dual}
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
-add wave -noupdate -format Literal /tb_fir_iterative/coeffs
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
-add wave -noupdate -format Logic /tb_fir_iterative/y_valid
-add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
-add wave -noupdate -divider {FIR Stage}
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {5100000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {42 us}
diff --git a/lib/filter/sim/tb_fir_parallel b/lib/filter/sim/tb_fir_parallel
deleted file mode 100644
index f784c1a..0000000
Binary files a/lib/filter/sim/tb_fir_parallel and /dev/null differ
diff --git a/lib/filter/sim/tb_fir_parallel.fdo b/lib/filter/sim/tb_fir_parallel.fdo
deleted file mode 100644
index 6bee97f..0000000
--- a/lib/filter/sim/tb_fir_parallel.fdo
+++ /dev/null
@@ -1,18 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/filter_pkg.vhd"
-vcom -explicit -93 "../src/fir_pkg.vhd"
-vcom -explicit -93 "../src/fir_stage.vhd"
-vcom -explicit -93 "../src/fir_parallel.vhd"
-vcom -explicit -93 "../src/tb_fir_parallel.vhd"
-vsim -t 1ps -lib work tb_fir_parallel
-do {tb_fir_parallel.wdo}
-view wave
-view structure
-view signals
-run 1000us
diff --git a/lib/filter/sim/tb_fir_parallel.wdo b/lib/filter/sim/tb_fir_parallel.wdo
deleted file mode 100644
index f0e20ce..0000000
--- a/lib/filter/sim/tb_fir_parallel.wdo
+++ /dev/null
@@ -1,29 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_parallel/clk
-add wave -noupdate -format Logic /tb_fir_parallel/srst
-add wave -noupdate -format Logic /tb_fir_parallel/in_valid
-add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/x_in
-add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/y_out
-add wave -noupdate -format Logic /tb_fir_parallel/out_valid
-add wave -noupdate -format Logic /tb_fir_parallel/fileout_enable
-add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/xi
-add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/yo
-add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/coeff_in
-add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/uut_fir_parallel/h
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {19450000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {25152750 ps}
diff --git a/lib/filter/sim/tb_fir_results.m b/lib/filter/sim/tb_fir_results.m
deleted file mode 100644
index 75a542c..0000000
--- a/lib/filter/sim/tb_fir_results.m
+++ /dev/null
@@ -1,10 +0,0 @@
-% Read data
-function tb_fir_results()
-fir = TEXTREAD('fir.txt')';
-
-N= length(fir);
-
-% Output
-close all;
-plot(0:N-1, fir); grid;
-
diff --git a/lib/filter/sim/tb_fir_semi_parallel.fdo b/lib/filter/sim/tb_fir_semi_parallel.fdo
deleted file mode 100644
index 63079c8..0000000
--- a/lib/filter/sim/tb_fir_semi_parallel.fdo
+++ /dev/null
@@ -1,20 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd"
-vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/filter_pkg.vhd"
-vcom -explicit -93 "../src/fir_pkg.vhd"
-vcom -explicit -93 "../src/fir_stage_sys.vhd"
-vcom -explicit -93 "../src/delay_line.vhd"
-vcom -explicit -93 "../src/fir_semi_parallel.vhd"
-vcom -explicit -93 "../src/tb_fir_semi_parallel.vhd"
-vsim -t 1ps -lib work tb_fir_semi_parallel
-do {tb_fir_semi_parallel.wdo}
-view wave
-view structure
-view signals
-run 50us
diff --git a/lib/filter/sim/tb_fir_semi_parallel.wdo b/lib/filter/sim/tb_fir_semi_parallel.wdo
deleted file mode 100644
index aba8fb1..0000000
--- a/lib/filter/sim/tb_fir_semi_parallel.wdo
+++ /dev/null
@@ -1,57 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/rst
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/clk
-add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/h_addr
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/h_we
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/h_in
-add wave -noupdate -format Logic /tb_fir_semi_parallel/dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_in
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_out
-add wave -noupdate -format Logic /tb_fir_semi_parallel/rdy
-add wave -noupdate -divider {Real out}
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/xi
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/yo
-add wave -noupdate -divider -height 50
-add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/count0
-add wave -noupdate -format Logic /tb_fir_semi_parallel/din_vld
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/start
-add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/count_array
-add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/en_array
-add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/ce_array
-add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/h_addr
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/h_we
-add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/x
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/accu_load
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/accu
-add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/y
-add wave -noupdate -divider {stage 1}
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/clk
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/y_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__0/inst_delay_line/inst_dpram_1w1r/ram
-add wave -noupdate -divider {stage 2}
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/clk
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/y_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__1/inst_delay_line/inst_dpram_1w1r/ram
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {486552931 ps} 0} {{Cursor 2} {49902384 ps} 0} {{Cursor 3} {148250000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {52500 ns}
diff --git a/lib/filter/sim/tb_fir_stage.fdo b/lib/filter/sim/tb_fir_stage.fdo
deleted file mode 100644
index e9fefb8..0000000
--- a/lib/filter/sim/tb_fir_stage.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/filter_pkg.vhd"
-vcom -explicit -93 "../src/fir_pkg.vhd"
-vcom -explicit -93 "../src/fir_stage.vhd"
-vcom -explicit -93 "../src/tb_fir_stage.vhd"
-vsim -t 1ps -lib work tb_fir_stage
-do {tb_fir_stage.wdo}
-view wave
-view structure
-view signals
-run 2us
diff --git a/lib/filter/sim/tb_fir_stage.wdo b/lib/filter/sim/tb_fir_stage.wdo
deleted file mode 100644
index 916de83..0000000
--- a/lib/filter/sim/tb_fir_stage.wdo
+++ /dev/null
@@ -1,31 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_stage/clk
-add wave -noupdate -format Logic /tb_fir_stage/srst
-add wave -noupdate -divider Input
-add wave -noupdate -format Logic /tb_fir_stage/in_valid
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x_in
-add wave -noupdate -format Literal /tb_fir_stage/xi
-add wave -noupdate -divider Output
-add wave -noupdate -format Logic /tb_fir_stage/out_valid
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y_out
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_stage/yo
-add wave -noupdate -divider {Stage signals}
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1655000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {2100 ns}
diff --git a/lib/filter/sim/tb_fir_stage_sys.fdo b/lib/filter/sim/tb_fir_stage_sys.fdo
deleted file mode 100644
index b2417c3..0000000
--- a/lib/filter/sim/tb_fir_stage_sys.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/filter_pkg.vhd"
-vcom -explicit -93 "../src/fir_pkg.vhd"
-vcom -explicit -93 "../src/fir_stage_sys.vhd"
-vcom -explicit -93 "../src/tb_fir_stage_sys.vhd"
-vsim -t 1ps -lib work tb_fir_stage_sys
-do {tb_fir_stage_sys.wdo}
-view wave
-view structure
-view signals
-run 2us
diff --git a/lib/filter/sim/tb_fir_stage_sys.wdo b/lib/filter/sim/tb_fir_stage_sys.wdo
deleted file mode 100644
index 21e822e..0000000
--- a/lib/filter/sim/tb_fir_stage_sys.wdo
+++ /dev/null
@@ -1,28 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_stage_sys/clk
-add wave -noupdate -divider Input
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x_in
-add wave -noupdate -format Literal /tb_fir_stage_sys/xi
-add wave -noupdate -divider Output
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y_out
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_stage_sys/yo
-add wave -noupdate -divider {Stage signals}
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1060000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {706931 ps} {1268317 ps}
diff --git a/lib/filter/src/delay_line.vhd b/lib/filter/src/delay_line.vhd
deleted file mode 100644
index a05e317..0000000
--- a/lib/filter/src/delay_line.vhd
+++ /dev/null
@@ -1,129 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_parallel - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-
-entity delay_line is
-Generic
-(
- nbits : integer := 12;
- nbits_frac : integer := 11;
- ntaps : integer := 4;
- delay_fix : integer := 1
-);
-Port
-(
- rst : in std_logic;
- clk : in std_logic;
- shift_en : in std_logic;
- delay : in natural range 0 to ntaps-1;
- din : in sfixed;
- dout : out sfixed
-);
-end delay_line;
-
-architecture ram_based of delay_line is
-
- -------------------------------------------------------------------------------
- signal count : natural range 0 to ntaps-1;
- signal addr_w : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
- signal addr_r : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
- signal ram_w : unsigned(nbits-1 downto 0);
- signal ram_r : unsigned(nbits-1 downto 0);
-
- -------------------------------------------------------------------------------
-begin
-
- addr_w <= to_unsigned(count, addr_w'length);
- addr_r <= addr_w + not to_unsigned(delay, addr_w'length);
-
- ram_w <= unsigned(din);
- dout <= sfixed(ram_r);
-
-counter:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- count <= 0;
- elsif shift_en = '1' then
- if count /= ntaps-1 then
- count <= count + 1;
- else
- count <= 0;
- end if;
- end if;
- end if;
- end process;
-
- inst_dpram_1w1r: entity work.dpram_1w1r
- GENERIC MAP
- (
- addr_width => NextExpBaseTwo(ntaps),
- data_width => nbits
- )
- PORT MAP (
- clka => clk,
- clkb => clk,
- en_a => '1',
- en_b => '1',
- we_a => shift_en,
- addr_a => addr_w,
- addr_b => addr_r,
- din_a => ram_w,
- dout_b => ram_r
- );
-
-end ram_based;
-
-architecture reg_based of delay_line is
-
- -------------------------------------------------------------------------------
- subtype word_t is sfixed(shi(nbits, nbits_frac) downto slo(nbits, nbits_frac));
- type delay_pipe_t is array (ntaps-1 downto 0) of word_t;
- type delay_fix_pipe_t is array (delay_fix downto 0) of word_t;
-
- -------------------------------------------------------------------------------
-begin
-
-shift_register:
- process(clk)
- variable delay_pipe : delay_pipe_t;
- begin
- if rising_edge(clk) then
- dout <= delay_pipe(delay);
- if shift_en = '1' then
- delay_pipe := delay_pipe(delay_pipe'left-1 downto 0) & din;
- end if;
- end if;
- end process;
-
-end reg_based;
-
diff --git a/lib/filter/src/filter_pkg.vhd b/lib/filter/src/filter_pkg.vhd
deleted file mode 100644
index 1359d25..0000000
--- a/lib/filter/src/filter_pkg.vhd
+++ /dev/null
@@ -1,219 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use IEEE.MATH_REAL.ALL;
-
-library work;
-use work.fixed_util_pkg.all;
-
--------------------------------------------------------------------------------
-package filter_pkg is
-
- function FilterCoef_Lowpass (N : positive; omega, gain : real) return real_array_t;
- function FilterCoef_Highpass (N : positive; omega, gain : real) return real_array_t;
- function FilterCoef_Bandpass (N : positive; bw2, omega_m, gain : real) return real_array_t;
- function FilterCoef_Delta (N:positive; delay:natural; gain:real) return real_array_t;
- function Window_Hamming (x : real_array_t) return real_array_t;
- function Window_VonHann (x : real_array_t) return real_array_t;
- function Window_Blackman (x : real_array_t) return real_array_t;
- function Sinc (x : real) return real;
- function FilterEnergy (x : real_array_t) return real;
- function FilterMean (x : real_array_t) return real;
- function FilterScale (x : real_array_t; scale : real) return real_array_t;
- function FilterTestCoef (N : positive) return real_array_t;
-
-end; -- package filter_pkg;
-
--------------------------------------------------------------------------------
-package body filter_pkg is
-
- function Prototype_Lowpass (N : positive; omega : real) return real_array_t is
- variable res : real_array_t(0 to N-1);
- variable M : positive;
- variable phi : real := 0.0;
- variable dphi : real := pi*omega;
- begin
- if (N mod 2) = 0 then
- M := N/2;
- for i in 0 to M-1 loop
- phi := phi + dphi;
- res(M+i) := Sinc(phi);
- res(M-i-1) := res(M+i);
- end loop;
- else
- M := (N-1)/2;
- for i in 1 to M loop
- phi := phi + dphi;
- res(M+i) := Sinc(phi);
- res(M-i) := res(M+i);
- end loop;
- res(M) := Sinc(0.0);
- end if;
- return res;
-
- end Prototype_Lowpass;
-
- -------------------------------------------------------------------------------
- function FilterCoef_Lowpass (N : positive; omega, gain : real) return real_array_t is
- variable lp : real_array_t(0 to N-1);
- begin
- lp := Prototype_Lowpass(N, omega);
-
- return Window_VonHann(FilterScale(lp, gain/FilterEnergy(lp)));
-
- end FilterCoef_Lowpass;
-
- -------------------------------------------------------------------------------
- function FilterCoef_Highpass (N : positive; omega, gain : real) return real_array_t is
- variable lp, res : real_array_t(0 to N-1);
- variable phi : real := 0.0;
- variable dphi : real := pi;
- begin
- lp := Prototype_Lowpass(N, 0.5-omega);
-
- for i in 0 to N-1 loop
- res(i) := lp(i) * cos(phi);
- phi := phi + dphi;
- end loop;
-
- return Window_VonHann(FilterScale(res, gain/FilterEnergy(lp)));
-
- end FilterCoef_Highpass;
-
- -------------------------------------------------------------------------------
- function FilterCoef_Bandpass (N : positive; bw2, omega_m, gain : real) return real_array_t is
- variable lp, res, mean, sum : real_array_t(0 to N-1);
- variable phi : real := 0.0;
- variable dphi : real := 2.0*pi*omega_m;
- begin
- lp := Prototype_Lowpass(N, bw2/2.0);
-
- for i in 0 to N-1 loop
- res(i) := lp(i) * cos(phi);
- phi := phi + dphi;
- end loop;
-
- return Window_VonHann(FilterScale(res, gain/FilterEnergy(lp)));
-
- end FilterCoef_Bandpass;
-
- -------------------------------------------------------------------------------
- function FilterCoef_Delta (N:positive; delay:natural; gain:real) return real_array_t is
- variable res : real_array_t(0 to N-1);
- begin
- for i in 0 to N-1 loop
- res(i) := 0.0;
- end loop;
- res(delay) := gain;
-
- return res;
-
- end FilterCoef_Delta;
-
- -------------------------------------------------------------------------------
- function FilterTestCoef (N : positive) return real_array_t is
- variable phi : real := 0.0;
- variable dphi : real := 1.0/real(N);
- variable res : real_array_t(0 to N-1);
- begin
- for i in 0 to N-1 loop
- res(i) := phi;
- phi := phi + dphi;
- end loop;
- return res;
-
- end FilterTestCoef;
-
- -------------------------------------------------------------------------------
- function Window_Hamming (x : real_array_t) return real_array_t is
- variable res : real_array_t(x'range);
- variable phi : real := 0.0;
- variable dphi : real := 2.0*pi/real(x'length-1);
- begin
- for i in x'range loop
- res(i) := x(i) * (0.54 - 0.46*(cos(phi)));
- phi := phi + dphi;
- end loop;
- return res;
-
- end Window_Hamming;
-
- -------------------------------------------------------------------------------
- function Window_VonHann (x : real_array_t) return real_array_t is
- variable res : real_array_t(x'range);
- variable phi : real := 0.0;
- variable dphi : real := 2.0*pi/real(x'length-1);
- begin
- for i in x'range loop
- res(i) := 0.5 * x(i) * (1.0 - (cos(phi)));
- phi := phi + dphi;
- end loop;
- return res;
-
- end Window_VonHann;
-
- -------------------------------------------------------------------------------
- function Window_Blackman (x : real_array_t) return real_array_t is
- variable res : real_array_t(0 to x'length-1);
- variable phi : real := 0.0;
- variable dphi : real := 2.0*pi/real(x'length-1);
- begin
- for i in x'range loop
- res(i) := x(i) * (0.42 - 0.5*cos(phi) + 0.08*cos(2.0*phi));
- phi := phi + dphi;
- end loop;
- return res;
-
- end Window_Blackman;
-
- -------------------------------------------------------------------------------
- function Sinc (x : real) return real is
- variable res : real := 1.0;
- begin
- if x /= 0.0 then
- res := sin(x)/x;
- end if;
-
- return res;
-
- end Sinc;
-
- -------------------------------------------------------------------------------
- function FilterScale (x : real_array_t; scale : real) return real_array_t is
- variable res : real_array_t(x'range);
- begin
- for i in x'range loop
- res(i) := scale * x(i);
- end loop;
-
- return res;
-
- end FilterScale;
-
- -------------------------------------------------------------------------------
- function FilterEnergy (x : real_array_t) return real is
- variable res : real := 0.0;
- begin
- for i in x'range loop
- res := res + x(i)*x(i);
- end loop;
-
- return res;
-
- end FilterEnergy;
-
- -------------------------------------------------------------------------------
- function FilterMean (x : real_array_t) return real is
- variable res : real := 0.0;
- begin
- for i in x'range loop
- res := res + x(i);
- end loop;
-
- return res/real(x'length);
-
- end FilterMean;
-
--------------------------------------------------------------------------------
-end; -- package filter_pkg;
diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd
deleted file mode 100644
index bc1dba5..0000000
--- a/lib/filter/src/fir_iterative.vhd
+++ /dev/null
@@ -1,323 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_parallel - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_iterative is
-Generic
-(
- ntaps : integer := 33;
- nbits_in : integer := 12;
- nbits_in_frac : integer := 11;
- nbits_stages : integer := 13;
- nbits_stages_frac : integer := 11;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 11;
- fir_mode : fir_iterative_mode_t := normal;
- rounding : boolean := true;
- saturating : boolean := true
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- h_din : in sfixed;
- h_addr_out : out natural;
- ready : out std_logic;
- x_valid : in std_logic;
- x_din : in sfixed;
- y_dout_valid : out std_logic;
- y_dout : out sfixed
-);
-end fir_iterative;
-
-architecture Behavioral of fir_iterative is
-
--------------------------------------------------------------------------------
- constant fir_stage_mode : fir_stage_mode_t := transposed;
- constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
- constant h_addr_bits : integer := taps_nbits(ntaps, fir_mode);
-
- subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- subtype stage_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- type state_t is (init, idle, start, proc, p1, p2, output);
- signal s, sn : state_t;
- signal x_stage, xo, y_stage : stage_t;
- signal stage_en, cnt_en, new_round : std_logic;
-
- subtype tap_cnt_t is natural range 0 to ntaps-1;
- signal htap_cnt : tap_cnt_t;
- signal xtap_cnt_w : tap_cnt_t;
- signal xtap_cnt_r : tap_cnt_t;
- signal stage_valid, clr_xmem, valid, fir_stage_clr, fir_stage_en, cnt_reset : std_logic;
- subtype tap_range_t is natural range 0 to ntaps_addr(ntaps, fir_mode)-1;
- signal h_addr : tap_range_t;
- signal xmem_din, xmem_dout : in_t;
- signal xmem_we, y_valid : std_logic;
-
- type xmem_t is array (0 to ntaps-1) of in_t;
- signal xmem : xmem_t;
- signal y_out_reg : out_t;
- signal y_reg_valid : std_logic;
-
- -------------------------------------------------------------------------------
-begin
-
- h_addr_out <= h_addr;
- x_stage <= resize(xmem_dout, x_stage, fixed_wrap, fixed_truncate);
-
- ----------------------------------------
- process (clk)
- begin
- if rising_edge(clk) then
- y_reg_valid <= '0';
- if srst = '1' then
- y_out_reg <= to_sfixed(0, y_out_reg);
- elsif y_valid = '1' then
- y_out_reg <= resize(y_stage, y_out_reg);
- y_reg_valid <= '1';
- end if;
- end if;
- end process;
-
- process (clk)
- begin
- if rising_edge(clk) then
- y_dout_valid <= '0';
- if srst = '1' then
- y_dout <= to_sfixed(0, sproto(nbits_out, nbits_out_frac));
- elsif y_reg_valid = '1' then
- y_dout <= resize(y_out_reg, sproto(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
- y_dout_valid <= '1';
- end if;
- end if;
- end process;
-
- ----------------------------------------
- proc_xmem_rw: process (clk)
- begin
- if rising_edge(clk) then
- if xmem_we = '1' then
- xmem(xtap_cnt_w) <= xmem_din;
- end if;
- xmem_dout <= xmem(xtap_cnt_r);
- end if;
- end process;
-
- ----------------------------------------
- proc_xmem_dinmux: process(new_round, clr_xmem, x_din, xmem_dout)
- begin
- xmem_din <= to_sfixed(0, xmem_din);
- if new_round = '1' and clr_xmem = '0' then
- xmem_din <= sfixed(x_din);
- end if;
- end process;
-
- ----------------------------------------
- proc_xmem_pointer: process(clk, new_round ,clr_xmem)
- begin
- xmem_we <= clr_xmem or new_round;
- if rising_edge(clk) then
- if srst = '1' then
- xtap_cnt_w <= tap_cnt_t'high;
- elsif xmem_we = '1' then
- if xtap_cnt_w /= tap_cnt_t'low then
- xtap_cnt_w <= xtap_cnt_w - 1;
- else
- xtap_cnt_w <= tap_cnt_t'high;
- end if;
- end if;
- end if;
- end process;
-
- ----------------------------------------
- proc_h_addr: process(htap_cnt)
- begin
- if fir_mode = symmetric then
- if ntaps_is_even then
- if htap_cnt > ntaps/2-1 then
- h_addr <= ntaps - htap_cnt - 1;
- else
- h_addr <= htap_cnt;
- end if;
- else
- if htap_cnt > (ntaps-1)/2 then
- h_addr <= ntaps - htap_cnt - 1;
- else
- h_addr <= htap_cnt;
- end if;
- end if;
- else
- h_addr <= htap_cnt;
- end if;
- end process;
-
- ----------------------------------------
- proc_tap_counter: process(cnt_reset, clk, htap_cnt, xtap_cnt_r, xtap_cnt_w, cnt_en)
- begin
- if rising_edge(clk) then
- if cnt_reset = '1' then
- htap_cnt <= tap_cnt_t'low;
- xtap_cnt_r <= xtap_cnt_w;
- elsif cnt_en = '1' then
- if htap_cnt /= tap_cnt_t'high then
- htap_cnt <= htap_cnt + 1;
- else
- htap_cnt <= tap_cnt_t'low;
- end if;
- if xtap_cnt_r /= tap_cnt_t'high then
- xtap_cnt_r <= xtap_cnt_r + 1;
- else
- xtap_cnt_r <= tap_cnt_t'low;
- end if;
- end if;
- end if;
- end process;
-
- ----------------------------------------
- proc_valid_out: process(srst, clk, valid, new_round)
- variable val_pipe : unsigned(4 downto 0);
- variable ctrl_pipe : unsigned(2 downto 0);
-
- begin
- if rising_edge(clk) then
- if srst = '1' then
- ctrl_pipe := (others => '0');
- fir_stage_en <= '0';
- fir_stage_clr <= '0';
- else
- ctrl_pipe := ctrl_pipe(ctrl_pipe'left-1 downto ctrl_pipe'right) & new_round;
- fir_stage_en <= stage_en;
- fir_stage_clr <= ctrl_pipe(2);
- end if;
- end if;
- cnt_reset <= new_round;
- end process;
-
- ----------------------------------------
- proc_fsm: process(s, x_valid, htap_cnt, xtap_cnt_w)
- begin
- clr_xmem <= '0';
- new_round <= '0';
- cnt_en <= '0';
- ready <= '0';
- valid <= '0';
- sn <= s;
- stage_en <= '0';
- y_valid <= '0';
-
- case s is
- when init =>
- clr_xmem <= '1';
- if xtap_cnt_w = tap_cnt_t'low then
- sn <= idle;
- end if;
-
- when idle =>
- ready <= '1';
- if x_valid = '1' then
- sn <= start;
- end if;
-
- when start =>
- new_round <= '1';
- sn <= proc;
-
- when proc =>
- stage_en <= '1';
- cnt_en <= '1';
- if htap_cnt = tap_cnt_t'high then
- sn <= p1;
- end if;
-
- when p1 =>
- sn <= p2;
-
- when p2 =>
- sn <= output;
- ready <= '1';
-
- when output =>
- sn <= idle;
- y_valid <= '1';
- ready <= '1';
- if x_valid = '1' then
- sn <= start;
- end if;
-
- when others => null;
- end case;
- end process;
-
- proc_fsm_next: process(srst, clk, sn)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- s <= init;
- else
- s <= sn;
- end if;
- end if;
- end process;
-
- ----------------------------------------
- inst_fir_stage: entity work.fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- input_latency => 1,
- coef_latency => 1,
- pipe_latency => 3
- )
- PORT MAP
- (
- rst => fir_stage_clr,
- clk => clk,
- x_in => x_stage,
- y_in => y_stage,
- h_in => h_din,
- x_out => xo,
- y_out => y_stage
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
-
-end Behavioral;
diff --git a/lib/filter/src/fir_iterative_pkg.vhd b/lib/filter/src/fir_iterative_pkg.vhd
deleted file mode 100644
index af8bb68..0000000
--- a/lib/filter/src/fir_iterative_pkg.vhd
+++ /dev/null
@@ -1,52 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-
--------------------------------------------------------------------------------
-package fir_iterative_pkg is
-
- type fir_iterative_mode_t is (normal, symmetric);
-
- function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer;
- function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer;
-
-end; -- package fir_iterative_pkg;
-
--------------------------------------------------------------------------------
-package body fir_iterative_pkg is
-
- function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is
- variable res : integer;
- begin
- res := integer(NextExpBaseTwo(real(ntaps_addr(ntaps, mode))));
- return res;
- end taps_nbits;
-
- function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is
- constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
- variable res : integer := ntaps;
- begin
- if mode = symmetric then
- if ntaps_is_even then
- res := ntaps/2;
- else
- res := (ntaps-1)/2 + 1;
- end if;
- end if;
- return res;
- end ntaps_addr;
-
-end; -- package fir_iterative_pkg;
-
--------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_parallel.vhd b/lib/filter/src/fir_parallel.vhd
deleted file mode 100644
index 2561848..0000000
--- a/lib/filter/src/fir_parallel.vhd
+++ /dev/null
@@ -1,218 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_parallel - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_parallel is
-Generic
-(
- ntaps : integer := 33;
- nbits_in : integer := 12;
- nbits_in_frac : integer := 11;
- nbits_stages : integer := 13;
- nbits_stages_frac : integer := 11;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 11;
- has_in_reg : boolean := false;
- has_pipe_reg : boolean := false;
- has_out_reg : boolean := false;
- fir_mode : fir_parallel_mode_t := transposed;
- rounding : boolean := true;
- saturating : boolean := true
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- h_in : in sfixed_array_t;
- in_valid : in std_logic;
- d_in : in sfixed;
- out_valid : out std_logic;
- d_out : out sfixed
-);
-end fir_parallel;
-
-architecture Behavioral of fir_parallel is
-
--------------------------------------------------------------------------------
- -- Component Declaration for FIR stage
- COMPONENT fir_stage
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- has_in_reg : boolean;
- has_pipe_reg : boolean;
- has_out_reg : boolean;
- fir_mode : fir_stage_mode_t;
- rounding : boolean;
- saturating : boolean
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- out_valid : out std_logic;
- x_out : out sfixed;
- y_out : out sfixed;
- y_out_clr : in std_logic
- );
- END COMPONENT;
-
- -------------------------------------------------------------------------------
- type coeff_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- type stages_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
- constant fir_stage_mode : fir_stage_mode_t := transposed;
-
- SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
- SIGNAL x : stages_array_t(0 to ntaps-2);
- SIGNAL y : stages_array_t(0 to ntaps-2);
- SIGNAL h : coeff_array_t(0 to ntaps-1);
-
- -------------------------------------------------------------------------------
-begin
-
- -- Assign coefficients
- assign_coeffs:
- for i in 0 to ntaps-1 generate
- h(i) <= to_sfixed(h_in, i);
- end generate;
-
- ----------------------------------------
- -- Instantiate the FIR stages
- ----------------------------------------
- uut_first_stage: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_stage_mode,
- rounding => false,
- saturating => false
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- in_valid => in_valid,
- x_in => d_in,
- y_in => zero_in,
- h_in => h(ntaps-1),
- out_valid => out_valid,
- x_out => x(0),
- y_out => y(0),
- y_out_clr => '0'
- );
-
- ----------------------------------------
- gen_stages:
- for i in 1 to ntaps-2 generate
- uut_stages: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_stage_mode,
- rounding => false,
- saturating => false
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- in_valid => in_valid,
- x_in => x(i-1),
- y_in => y(i-1),
- h_in => h(ntaps-i-1),
- out_valid => open,
- x_out => x(i),
- y_out => y(i),
- y_out_clr => '0'
- );
- end generate;
-
- ----------------------------------------
- uut_last_stage: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_stage_mode,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- in_valid => in_valid,
- x_in => x(ntaps-2),
- y_in => y(ntaps-2),
- h_in => h(0),
- out_valid => open,
- x_out => x_out,
- y_out => d_out,
- y_out_clr => '0'
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
-
-end Behavioral;
diff --git a/lib/filter/src/fir_parallel_pkg.vhd b/lib/filter/src/fir_parallel_pkg.vhd
deleted file mode 100644
index 9243d8c..0000000
--- a/lib/filter/src/fir_parallel_pkg.vhd
+++ /dev/null
@@ -1,29 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_stage_pkg.all;
-
--------------------------------------------------------------------------------
-package fir_parallel_pkg is
-
- type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym);
-
-end; -- package fir_parallel_pkg;
-
--------------------------------------------------------------------------------
-package body fir_parallel_pkg is
-
-
-end; -- package fir_parallel_pkg;
-
--------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_pkg.vhd b/lib/filter/src/fir_pkg.vhd
deleted file mode 100644
index 9e904b5..0000000
--- a/lib/filter/src/fir_pkg.vhd
+++ /dev/null
@@ -1,54 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-
--------------------------------------------------------------------------------
-package fir_pkg is
-
- type fir_stage_mode_t is (transposed, systolic);
- type fir_iterative_mode_t is (normal, symmetric);
- type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym);
-
- function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer;
- function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer;
-
-end; -- package fir_pkg;
-
--------------------------------------------------------------------------------
-package body fir_pkg is
-
- function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is
- variable res : integer;
- begin
- res := integer(NextExpBaseTwo(real(ntaps_addr(ntaps, mode))));
- return res;
- end taps_nbits;
-
- function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is
- constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
- variable res : integer := ntaps;
- begin
- if mode = symmetric then
- if ntaps_is_even then
- res := ntaps/2;
- else
- res := (ntaps-1)/2 + 1;
- end if;
- end if;
- return res;
- end ntaps_addr;
-
-end; -- package fir_pkg;
-
--------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd
deleted file mode 100644
index 68493c1..0000000
--- a/lib/filter/src/fir_semi_parallel.vhd
+++ /dev/null
@@ -1,300 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_parallel - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_semi_parallel is
-Generic
-(
- ntaps_per_stage : integer := 32;
- nstages : integer := 2;
- pipe_latency : integer := 4;
- nbits_in : integer := 12;
- nbits_in_frac : integer := 11;
- nbits_stages : integer := 13;
- nbits_stages_frac : integer := 11;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 11
-);
-Port
-(
- rst : in std_logic;
- clk : in std_logic;
- h_addr : in natural range 0 to nstages*ntaps_per_stage-1;
- h_we : in std_logic;
- h_in : in sfixed;
- din_vld : in std_logic;
- din : in sfixed;
- dout_vld : out std_logic;
- start : in std_logic;
- rdy : out std_logic;
- dout : out sfixed
-);
-end fir_semi_parallel;
-
-architecture Behavioral of fir_semi_parallel is
-
- -------------------------------------------------------------------------------
- constant coef_addr_nbits : natural := NextExpBaseTwo(ntaps_per_stage) + NextExpBaseTwo(nstages);
-
- subtype coef_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- subtype count_t is natural range 0 to ntaps_per_stage-1;
- type count_array_t is array (nstages-1 downto 0) of count_t;
-
- subtype stage_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- type stage_array_t is array (0 to nstages) of stage_t;
-
- signal count_array : count_array_t;
- signal count0 : count_t;
- signal ce_array : unsigned(nstages downto 0);
- signal en_array : unsigned(nstages downto 0);
- signal coef_addr : unsigned(coef_addr_nbits-1 downto 0);
-
- SIGNAL x : stage_array_t;
- SIGNAL xo : stage_array_t;
- SIGNAL y : stage_array_t;
- SIGNAL accu : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- SIGNAL act : std_logic := '0';
- SIGNAL start_r : std_logic := '0';
- signal accu_load : std_logic;
- signal accu_ld_pipe : unsigned(nstages+pipe_latency-1 downto 0);
-
- signal din_r : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- signal coef_we : unsigned(nstages-1 downto 0);
-
- type coef_array_t is array (0 to nstages-1) of unsigned(nbits_stages-1 downto 0);
- signal coef_din : unsigned(nbits_stages-1 downto 0);
- signal coef_dout : coef_array_t;
-
- -------------------------------------------------------------------------------
-begin
-
- assert ntaps_per_stage = NextPowerOfTwo(ntaps_per_stage) report "ntaps_per_stage must be of form 2**R!" severity failure;
- assert ntaps_per_stage >= 4 report "ntaps_per_stage must be greater than 4" severity failure;
-
- x(0) <= resize(din_r, x(0));
- y(0) <= to_sfixed(0.0, y(0));
-
- accu_load <= accu_ld_pipe(accu_ld_pipe'left);
- start_r <= act and ce_array(ce_array'left) and not ce_array(ce_array'left-1);
-
-din_register:
- process(clk)
- begin
- if rising_edge(clk) then
- if din_vld = '1' then
- din_r <= din;
- end if;
- end if;
- end process;
-
-accu_load_pipe:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- accu_ld_pipe <= (others => '0');
- else
- accu_ld_pipe <= accu_ld_pipe(accu_ld_pipe'left-1 downto 0) & start_r;
- end if;
- end if;
- end process;
-
-coef_we_gen:
- process(clk)
- variable i : natural range 0 to nstages-1;
- variable caddr : unsigned(coef_addr_nbits-1 downto 0);
- variable saddr : unsigned(NextExpBaseTwo(nstages)-1 downto 0);
- begin
- if rising_edge(clk) then
- caddr := to_unsigned(h_addr, coef_addr_nbits);
- saddr := caddr(caddr'left downto NextExpBaseTwo(ntaps_per_stage));
- i := to_integer(saddr);
- coef_we <= (others => '0');
- coef_we(i) <= '1';
- coef_din <= unsigned(h_in);
- coef_addr <= caddr;
- end if;
- end process;
-
-rdy_logic:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- rdy <= '1';
- act <= '0';
- elsif start = '1' then
- rdy <= '0';
- act <= '1';
- elsif count0 = count_t'high-2 then
- rdy <= '1';
- act <= '0';
- end if;
- end if;
- end process;
-
-counter:
- process(clk)
- variable cnt : count_t;
- variable enable : std_logic;
- begin
- if rising_edge(clk) then
- if rst = '1' then
- cnt := count_t'high;
- elsif cnt /= count_t'high then
- cnt := cnt + 1;
- else
- enable := '0';
- if start_r = '1' then
- enable := '1';
- cnt := 0;
- end if;
- end if;
- count0 <= cnt;
- count_array <= count_array(count_array'left-1 downto 0) & cnt;
- en_array <= en_array(en_array'left-1 downto 0) & enable;
- end if;
- end process;
-
-ce_pipe:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- ce_array <= (others => '0');
- else
- ce_array <= ce_array(ce_array'left-1 downto 0) & din_vld;
- end if;
- end if;
- end process;
-
-gen_coef_ram:
- for i in 0 to nstages-1 generate
- signal addr_a : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0);
- signal addr_b : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0);
- begin
- addr_a <= coef_addr(addr_a'length-1 downto 0);
- addr_b <= to_unsigned(count_array(i), addr_b'length);
- inst_coef_ram: entity work.dpram_1w1r
- GENERIC MAP
- (
- addr_width => NextExpBaseTwo(ntaps_per_stage),
- data_width => nbits_stages
- )
- PORT MAP (
- clka => clk,
- clkb => clk,
- en_a => '1',
- en_b => '1',
- we_a => coef_we(i),
- addr_a => addr_a,
- addr_b => addr_b,
- din_a => coef_din,
- dout_b => coef_dout(i)
- );
- end generate;
-
-
-gen_stages:
- for i in 0 to nstages-1 generate
- signal h_in : coef_t;
- begin
- h_in <= sfixed(coef_dout(i));
- inst_fir_stage: entity work.fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- pipe_latency => pipe_latency
- )
- PORT MAP
- (
- clk => clk,
- ce => en_array(i),
- x_in => x(i+1),
- y_in => y(i),
- h_in => h_in,
- x_out => xo(i+1),
- y_out => y(i+1)
- );
- end generate;
-
-
-gen_delays:
- for i in 0 to nstages-1 generate
- begin
- inst_delay_line : entity work.delay_line(ram_based)
- GENERIC MAP
- (
- nbits => nbits_stages,
- nbits_frac => nbits_stages_frac,
- ntaps => ntaps_per_stage,
- delay_fix => 0
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- shift_en => ce_array(i),
- delay => count_array(i),
- din => x(i),
- dout => x(i+1)
- );
- end generate;
-
-acumulator:
- process(clk)
- begin
- if rising_edge(clk) then
- dout_vld <= accu_load;
- if rst = '1' then
- dout_vld <= '0';
- elsif en_array(en_array'left) = '1' then
- if accu_load = '1' then
- dout <= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
- accu <= y(nstages);
- else
- accu <= resize(accu + y(nstages), accu);
- end if;
- end if;
- end if;
- end process;
-
-
-end Behavioral;
diff --git a/lib/filter/src/fir_stage.vhd b/lib/filter/src/fir_stage.vhd
deleted file mode 100644
index a519cf4..0000000
--- a/lib/filter/src/fir_stage.vhd
+++ /dev/null
@@ -1,157 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_stage is
-Generic
-(
- nbits_in : integer := 12;
- nbits_in_frac : integer := 12;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 12;
- has_in_reg : boolean := false;
- has_pipe_reg : boolean := false;
- has_out_reg : boolean := false;
- fir_mode : fir_stage_mode_t := transposed;
- rounding : boolean := true;
- saturating : boolean := true
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- out_valid : out std_logic;
- x_out : out sfixed;
- y_out : out sfixed;
- y_out_clr : in std_logic
-);
-end fir_stage;
-
-architecture Behavioral of fir_stage is
-
-signal xin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-signal yin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-signal hin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-signal prod : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-signal valid, p_valid : std_logic;
-------------------------------------------------------------
-begin
-
-
-------------------------------------------------------------
- proc_in_reg_y: process(clk)
- begin
- if rising_edge(clk) then
- if srst = '1' or y_out_clr = '1' then
- yin <= to_sfixed(0, yin);
- else
- yin <= resize(y_in, yin);
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_in_reg_hx: process(srst, clk, in_valid, x_in, h_in)
- variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- begin
- if has_in_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- xin <= to_sfixed(0, xin);
- hin <= to_sfixed(0, hin);
- valid <= '0';
- else
- valid <= in_valid;
- if in_valid = '1' then
- xin <= resize(x_in, xin);
- hin <= resize(h_in, hin);
- end if;
- end if;
- end if;
- else
- xin <= resize(x_in, xin);
- hin <= resize(h_in, hin);
- valid <= in_valid;
- end if;
- x_out <= resize(x_in, p);
-
- end process;
-
-------------------------------------------------------------
- proc_pipe_reg: process(srst, clk, valid, xin, hin)
- variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- begin
- p := resize(xin * hin, p);
- if has_pipe_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- prod <= to_sfixed(0, prod);
- p_valid <= '0';
- else
- prod <= p;
- p_valid <= valid;
- end if;
- end if;
- else
- prod <= p;
- p_valid <= valid;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_out_reg: process(srst, clk, p_valid, prod, yin)
- variable yout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- begin
- yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
--- if rising_edge(clk) then
--- if srst = '1' or y_out_clr = '1' then
--- y_out <= to_sfixed(0, yout);
--- out_valid <= '0';
--- else
--- y_out <= yout;
--- out_valid <= p_valid;
--- end if;
--- end if;
- out_valid <= p_valid;
- y_out <= yout;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/filter/src/fir_stage_pkg.vhd b/lib/filter/src/fir_stage_pkg.vhd
deleted file mode 100644
index c6408b8..0000000
--- a/lib/filter/src/fir_stage_pkg.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-package fir_stage_pkg is
-
-type fir_stage_mode_t is (transposed, systolic);
-
-end; -- package fir_stage_pkg;
-
-package body fir_stage_pkg is
-
-end; -- package fir_stage_pkg;
diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd
deleted file mode 100644
index af0f74a..0000000
--- a/lib/filter/src/fir_stage_sys.vhd
+++ /dev/null
@@ -1,109 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_stage_sys is
-Generic
-(
- nbits_in : integer := 12;
- nbits_in_frac : integer := 12;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 12;
- pipe_latency : integer := 4
-);
-Port
-(
- clk : in std_logic;
- ce : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- x_out : out sfixed;
- y_out : out sfixed
-);
-end fir_stage_sys;
-
-architecture Behavioral of fir_stage_sys is
-
-constant min_pipe_lat : integer := 4;
-
-subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
-type input_pipe_t is array (pipe_latency-2 downto 0) of in_t;
-type coef_pipe_t is array (pipe_latency-2 downto 0) of in_t;
-
-signal yin : in_t;
-signal prod : out_t;
-
-------------------------------------------------------------
-begin
-
- assert pipe_latency >= min_pipe_lat report "Pipe latency must be greater than " & natural'image(min_pipe_lat-1) & "!" severity failure;
-
- yin <= resize(y_in, yin);
-
-------------------------------------------------------------
- proc_pipe_reg: process(clk)
- variable h_pipe : coef_pipe_t;
- variable x_pipe : input_pipe_t;
- begin
- if rising_edge(clk) then
- if ce = '1' then
- x_pipe := x_pipe(x_pipe'left-1 downto 0) & resize(x_in, x_pipe(0));
- h_pipe := h_pipe(h_pipe'left-1 downto 0) & resize(h_in, h_pipe(0));
- prod <= resize(x_pipe(x_pipe'left) * h_pipe(h_pipe'left), prod, fixed_wrap, fixed_truncate);
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_out_reg: process(clk)
- variable yout : out_t;
- variable xout : in_t;
- begin
- if rising_edge(clk) then
- if ce = '1' then
- yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
- y_out <= yout;
- xout := resize(x_in, xout, fixed_wrap, fixed_truncate);
- x_out <= xout;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/filter/src/tb_fir_iterative.vhd b/lib/filter/src/tb_fir_iterative.vhd
deleted file mode 100644
index 76b6024..0000000
--- a/lib/filter/src/tb_fir_iterative.vhd
+++ /dev/null
@@ -1,234 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_iterative IS
- Generic (
- ntaps : integer := 11;
- nbits_in : integer := 15;
- nbits_in_frac : integer := 15;
- nbits_stages : integer := 15;
- nbits_stages_frac : integer := 15;
- nbits_out : integer := 15;
- nbits_out_frac : integer := 15;
- fir_mode : fir_iterative_mode_t := symmetric;
- rounding : boolean := true;
- saturating : boolean := true
- );
-END tb_fir_iterative;
-
-ARCHITECTURE behavior OF tb_fir_iterative IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT fir_iterative
- GENERIC
- (
- ntaps : integer;
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_stages : integer;
- nbits_stages_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- fir_mode : fir_iterative_mode_t;
- rounding : boolean;
- saturating : boolean
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- h_din : in sfixed;
- h_addr_out : out natural;
- ready : out std_logic;
- x_valid : in std_logic;
- x_din : in sfixed;
- y_dout_valid : out std_logic;
- y_dout : out sfixed
- );
- END COMPONENT;
-
- -------------------------------------------------------------------------------
- --Constants
- constant nsamples : integer := 32;
-
- constant PERIOD : time := 10 ns;
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL x_valid : std_logic := '0';
- SIGNAL h_din : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- SIGNAL x_din : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
- --Outputs
- SIGNAL y_dout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL y_valid : std_logic;
- SIGNAL ready : std_logic;
-
- SIGNAL fileout_enable : std_logic := '1';
-
- -- Test coefficients
--- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Delta(ntaps, 10, 0.999)(0 to ntaps_addr(ntaps, fir_mode)-1);
- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Bandpass(ntaps, 0.25, 0.125, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1);
--- SIGNAL coeffs : real_array_t(0 to ntaps-1) := FilterTestCoef(ntaps);
- signal x_input : real_array_t(0 to nsamples-1) :=
- (
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.9999,
- -0.0000,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0
-
- );
- type ymem_t is array (0 to nsamples-1) of sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- signal ymem : ymem_t;
-
- signal y_cnt : integer ;
- SIGNAL xi, yo : real := 0.0;
- SIGNAL h_addr : natural;
-
- -- file I/O
- subtype sample_t is integer range -32768 to 32767;
- type file_t is file of sample_t;
-
- -------------------------------------------------------------------------------
-BEGIN
-
- xi <= to_real(x_din);
- yo <= to_real(y_dout);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut_fir_iterative: fir_iterative
- GENERIC MAP
- (
- ntaps => ntaps,
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- nbits_stages => nbits_stages,
- nbits_stages_frac => nbits_stages_frac,
- fir_mode => fir_mode,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- h_din => h_din,
- h_addr_out => h_addr,
- ready => ready,
- x_valid => x_valid,
- x_din => x_din,
- y_dout_valid => y_valid,
- y_dout => y_dout
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
-
- for i in 0 to nsamples-1 loop
- if i = nsamples/2 then
- wait for 43*PERIOD;
- end if;
- ------------------------------------------
- wait until rising_edge(clk) and ready = '1';
- x_din <= to_sfixed(x_input(i), x_din);
- x_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- x_valid <= '0';
- end loop;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- process(srst, clk, y_valid)
- begin
- if rising_edge(clk) then
- h_din <= to_sfixed(coeffs(h_addr), h_din);
- if srst = '1' then
- y_cnt <= 0;
-
- elsif y_valid = '1' then
- ymem(y_cnt) <= y_dout;
- y_cnt <= y_cnt + 1;
- end if;
- end if;
- end process;
-
-END;
diff --git a/lib/filter/src/tb_fir_parallel.vhd b/lib/filter/src/tb_fir_parallel.vhd
deleted file mode 100644
index e1ff939..0000000
--- a/lib/filter/src/tb_fir_parallel.vhd
+++ /dev/null
@@ -1,193 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_parallel IS
- Generic (
- ntaps : integer := 33;
- nbits_in : integer := 16;
- nbits_in_frac : integer := 16;
- nbits_stages : integer := 16;
- nbits_stages_frac : integer := 15;
- nbits_out : integer := 16;
- nbits_out_frac : integer := 16;
- has_in_reg : boolean := false;
- has_pipe_reg : boolean := true;
- has_out_reg : boolean := false;
- fir_mode : fir_parallel_mode_t := transposed;
- rounding : boolean := true;
- saturating : boolean := true
- );
-END tb_fir_parallel;
-
-ARCHITECTURE behavior OF tb_fir_parallel IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT fir_parallel
- GENERIC
- (
- ntaps : integer;
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_stages : integer;
- nbits_stages_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- has_in_reg : boolean;
- has_pipe_reg : boolean;
- has_out_reg : boolean;
- fir_mode : fir_parallel_mode_t;
- rounding : boolean;
- saturating : boolean
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- h_in : in sfixed_array_t;
- in_valid : in std_logic;
- d_in : in sfixed;
- out_valid : out std_logic;
- d_out : out sfixed
- );
- END COMPONENT;
-
- -------------------------------------------------------------------------------
- --Constants
- constant PERIOD : time := 10 ns;
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL in_valid : std_logic := '0';
- SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
- --Outputs
- SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL out_valid : std_logic := '0';
-
- SIGNAL fileout_enable : std_logic := '1';
-
- -- Test coefficients
- SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac);
-
- SIGNAL xi, yo : real := 0.0;
-
- -- file I/O
- subtype sample_t is integer range -32768 to 32767;
- type file_t is file of sample_t;
-
- -------------------------------------------------------------------------------
-BEGIN
-
- xi <= to_real(x_in);
- yo <= to_real(y_out);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut_fir_parallel: fir_parallel
- GENERIC MAP
- (
- ntaps => ntaps,
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- nbits_stages => nbits_stages,
- nbits_stages_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_mode,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- h_in => coeff_in,
- in_valid => in_valid,
- d_in => x_in,
- out_valid => out_valid,
- d_out => y_out
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- file fi : file_t open read_mode is "wav_in.dat";
- variable si : sample_t;
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
-
- while not endfile(fi) loop
- read(fi, si);
- x_in <= to_sfixed(to_signed(si, x_in'length));
- in_valid <= '1';
- wait for PERIOD;
- wait until rising_edge(clk);
- end loop;
- ------------------------------------------
- in_valid <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk, fileout_enable, out_valid)
- file fo : file_t open write_mode is "wav_out.dat";
- variable so : sample_t;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
- so := to_integer(y_out);
- write(fo, so);
- end if;
-
- END PROCESS;
-
-END;
diff --git a/lib/filter/src/tb_fir_semi_parallel.vhd b/lib/filter/src/tb_fir_semi_parallel.vhd
deleted file mode 100644
index 33da80f..0000000
--- a/lib/filter/src/tb_fir_semi_parallel.vhd
+++ /dev/null
@@ -1,289 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_semi_parallel IS
- Generic
- (
- ntaps_per_stage : integer := 32;
- nstages : integer := 2;
- nbits_in : integer := 32;
- nbits_in_frac : integer := 30;
- nbits_stages : integer := 32;
- nbits_stages_frac : integer := 30;
- nbits_out : integer := 32;
- nbits_out_frac : integer := 30
- );
-END tb_fir_semi_parallel;
-
-ARCHITECTURE behavior OF tb_fir_semi_parallel IS
-
- -------------------------------------------------------------------------------
- --Constants
- constant PERIOD : time := 10 ns;
- constant nsamples : integer := 32;
- constant M : integer := 1;
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL rst : std_logic := '1';
- SIGNAL din_vld : std_logic := '0';
- SIGNAL d_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- signal h_addr : natural := 0;
- SIGNAL h_we : std_logic := '0';
- SIGNAL h_in : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- SIGNAL start : std_logic := '0';
-
- --Outputs
- SIGNAL d_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL dout_vld : std_logic;
- SIGNAL rdy : std_logic;
-
- SIGNAL fileout_enable : std_logic := '1';
-
-
- SIGNAL xi, yo : real := 0.0;
-
- CONSTANT ntaps : natural := nstages*ntaps_per_stage;
- type h_mem_t is array (0 to ntaps-1) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
- variable res : h_mem_t;
- begin
- for i in 0 to ntaps-1 loop
- res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round);
- end loop;
-
- return res;
- end to_h_mem;
-
- CONSTANT coeffs : real_array_t(0 to ntaps-1) := FilterCoef_Lowpass(ntaps, 0.1, 4.0);
- CONSTANT h_mem : h_mem_t := to_h_mem(coeffs, ntaps, h_in);
-
- -- file I/O
- subtype sample_t is integer range -32768 to 32767;
- type file_t is file of sample_t;
-
- signal x_input : real_array_t(0 to nsamples-1) :=
- (
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 1.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0
-
- );
-
- -------------------------------------------------------------------------------
-BEGIN
-
- xi <= to_real(d_in);
- yo <= to_real(d_out);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut : entity work.fir_semi_parallel
- GENERIC MAP
- (
- ntaps_per_stage => ntaps_per_stage,
- nstages => nstages,
- pipe_latency => 5,
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_stages => nbits_stages,
- nbits_stages_frac => nbits_stages_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- h_addr => h_addr,
- h_we => h_we,
- h_in => h_in,
- din_vld => din_vld,
- din => d_in,
- dout_vld => dout_vld,
- rdy => rdy,
- start => start,
- dout => d_out
- );
-
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- file fi : file_t open read_mode is "wav_in.dat";
- variable si : sample_t;
- variable remain : integer;
- variable j : integer;
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- rst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
-
- -- write coeffs
- for i in 0 to ntaps-1 loop
- wait until rising_edge(clk);
- h_addr <= i;
- h_in <= h_mem(i);
- h_we <= '1';
- end loop;
- wait until rising_edge(clk);
--- h_addr <= 0;
--- h_in <= to_sfixed(0.25, h_in);
--- h_we <= '1';
--- wait until rising_edge(clk);
- h_we <= '0';
-
- -- Write zeros
- remain := ntaps_per_stage*nstages;
- j := 0;
- while remain /= 0 loop
- wait until rising_edge(clk) and rdy = '1';
- for i in 0 to M-1 loop
- d_in <= to_sfixed(0.0, d_in);
- din_vld <= '1';
- j := j + 1;
- remain := remain - 1;
- wait until rising_edge(clk);
- end loop;
- din_vld <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
- start <= '1';
- wait until rising_edge(clk);
- start <= '0';
- end loop;
-
- ------------------------------------------
- -- Write data
- remain := nsamples;
- j := 0;
- while remain /= 0 loop
- wait until rising_edge(clk) and rdy = '1';
- for i in 0 to M-1 loop
- d_in <= to_sfixed(x_input(j), d_in);
- din_vld <= '1';
- j := j + 1;
- remain := remain - 1;
- wait until rising_edge(clk);
- end loop;
- din_vld <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
- start <= '1';
- wait until rising_edge(clk);
- start <= '0';
- end loop;
-
- -- Write zeros
- remain := 100;
- j := 0;
- while remain /= 0 loop
- wait until rising_edge(clk) and rdy = '1';
- for i in 0 to M-1 loop
- d_in <= to_sfixed(0.0, d_in);
- din_vld <= '1';
- j := j + 1;
- remain := remain - 1;
- wait until rising_edge(clk);
- end loop;
- din_vld <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
- start <= '1';
- wait until rising_edge(clk);
- start <= '0';
- end loop;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk, fileout_enable)
- file fo : file_t open write_mode is "wav_out.dat";
- variable so : sample_t;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' then
- if dout_vld = '1' then
- so := to_integer(d_out);
- write(fo, so);
- end if;
- end if;
-
- END PROCESS;
-
-END;
diff --git a/lib/filter/src/tb_fir_stage.vhd b/lib/filter/src/tb_fir_stage.vhd
deleted file mode 100644
index 04bb03f..0000000
--- a/lib/filter/src/tb_fir_stage.vhd
+++ /dev/null
@@ -1,276 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-use work.filter_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_stage IS
- Generic (
- ntaps : integer := 33;
- nbits_in : integer := 24;
- nbits_in_frac : integer := 23;
- nbits_stages : integer := 25;
- nbits_stages_frac : integer := 23;
- nbits_out : integer := 24;
- nbits_out_frac : integer := 22;
- has_in_reg : boolean := true;
- has_pipe_reg : boolean := true;
- has_out_reg : boolean := false;
- fir_mode : fir_stage_mode_t := transposed;
- rounding : boolean := true;
- saturating : boolean := true
- );
-END tb_fir_stage;
-
-ARCHITECTURE behavior OF tb_fir_stage IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT fir_stage
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- has_in_reg : boolean;
- has_pipe_reg : boolean;
- has_out_reg : boolean;
- fir_mode : fir_stage_mode_t;
- rounding : boolean;
- saturating : boolean
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- out_valid : out std_logic;
- x_out : out sfixed;
- y_out : out sfixed;
- y_out_clr : in std_logic
- );
- END COMPONENT;
-
- type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- --Constants
- constant PERIOD : time := 10 ns;
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL in_valid : std_logic := '0';
- SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
- --Outputs
- SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL out_valid : std_logic := '0';
-
- SIGNAL x : stages_t(0 to ntaps-2);
- SIGNAL y : stages_t(0 to ntaps-2);
-
- SIGNAL fileout_enable : std_logic := '1';
-
- -- Test coefficients
- function to_sfixed(x_real : real_array_t) return stages_t is
- variable res : stages_t(x_real'range);
- begin
- for i in x_real'range loop
- res(i) := to_sfixed(x_real(i), res(i), fixed_wrap, fixed_round);
- end loop;
-
- return res;
- end to_sfixed;
-
- constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0));
-
- SIGNAL xi, yo : real := 0.0;
-
-BEGIN
-
- xi <= to_real(x_in);
- yo <= to_real(y_out);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut_first_stage: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_mode,
- rounding => false,
- saturating => false
- )
- PORT MAP
- (
- srst => srst,
- y_out_clr => '0',
- clk => clk,
- in_valid => in_valid,
- x_in => x_in,
- y_in => zero_in,
- h_in => h(ntaps-1),
- out_valid => out_valid,
- x_out => x(0),
- y_out => y(0)
- );
-
- ----------------------------------------
- gen_stages:
- for i in 1 to ntaps-2 generate
- uut_stages: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_mode,
- rounding => false,
- saturating => false
- )
- PORT MAP
- (
- srst => srst,
- y_out_clr => '0',
- clk => clk,
- in_valid => in_valid,
- x_in => x(i-1),
- y_in => y(i-1),
- h_in => h(ntaps-i-1),
- out_valid => open,
- x_out => x(i),
- y_out => y(i)
- );
- end generate;
-
- ----------------------------------------
- uut_last_stage: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_mode,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- y_out_clr => '0',
- clk => clk,
- in_valid => in_valid,
- x_in => x(ntaps-2),
- y_in => y(ntaps-2),
- h_in => h(0),
- out_valid => open,
- x_out => x_out,
- y_out => y_out
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
-
- x_in <= to_sfixed(0.0, x_in);
-
- wait until rising_edge(clk);
- in_valid <= '1';
-
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
-
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(1.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
-
- wait for 150*PERIOD;
-
- wait until rising_edge(clk);
- in_valid <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk, fileout_enable, out_valid)
- file RESULT_FIR: text open write_mode is "fir.txt";
- variable L: line;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
- fprint(RESULT_FIR, L,"%s\n", REAL'image(yo));
- end if;
-
- END PROCESS;
-
-END;
diff --git a/lib/filter/src/tb_fir_stage_sys.vhd b/lib/filter/src/tb_fir_stage_sys.vhd
deleted file mode 100644
index b0afe32..0000000
--- a/lib/filter/src/tb_fir_stage_sys.vhd
+++ /dev/null
@@ -1,230 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-use work.filter_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_stage_sys IS
- Generic
- (
- ntaps : integer := 33;
- nbits_in : integer := 24;
- nbits_in_frac : integer := 23;
- nbits_stages : integer := 25;
- nbits_stages_frac : integer := 23;
- nbits_out : integer := 24;
- nbits_out_frac : integer := 22
- );
-END tb_fir_stage_sys;
-
-ARCHITECTURE behavior OF tb_fir_stage_sys IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT fir_stage_sys
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- input_latency : integer;
- coef_latency : integer;
- pipe_latency : integer
- );
- PORT
- (
- clk : in std_logic;
- ce : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- x_out : out sfixed;
- y_out : out sfixed
- );
- END COMPONENT;
-
- type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- --Constants
- constant PERIOD : time := 10 ns;
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
- --Inputs
- SIGNAL ce : std_logic := '1';
- SIGNAL clk : std_logic := '0';
- SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
- --Outputs
- SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
- SIGNAL x : stages_t(0 to ntaps-2);
- SIGNAL y : stages_t(0 to ntaps-2);
-
- SIGNAL fileout_enable : std_logic := '1';
-
- -- Test coefficients
- function to_sfixed(x_real : real_array_t) return stages_t is
- variable res : stages_t(x_real'range);
- begin
- for i in x_real'range loop
- res(i) := to_sfixed(x_real(i), res(i), fixed_wrap, fixed_round);
- end loop;
-
- return res;
- end to_sfixed;
-
- constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0));
-
- SIGNAL xi, yo : real := 0.0;
-
-BEGIN
-
- xi <= to_real(x_in);
- yo <= to_real(y_out);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut_first_stage_sys: fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- input_latency => 1,
- coef_latency => 1,
- pipe_latency => 2
- )
- PORT MAP
- (
- clk => clk,
- ce => ce,
- x_in => x_in,
- y_in => zero_in,
- h_in => h(ntaps-1),
- x_out => x(0),
- y_out => y(0)
- );
-
- ----------------------------------------
- gen_stages:
- for i in 1 to ntaps-2 generate
- uut_stages: fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- input_latency => 2,
- coef_latency => 1,
- pipe_latency => 2
- )
- PORT MAP
- (
- clk => clk,
- ce => ce,
- x_in => x(i-1),
- y_in => y(i-1),
- h_in => h(ntaps-i-1),
- x_out => x(i),
- y_out => y(i)
- );
- end generate;
-
- ----------------------------------------
- uut_last_stage: fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- input_latency => 2,
- coef_latency => 1,
- pipe_latency => 2
- )
- PORT MAP
- (
- clk => clk,
- ce => ce,
- x_in => x(ntaps-2),
- y_in => y(ntaps-2),
- h_in => h(0),
- x_out => x_out,
- y_out => y_out
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- x_in <= to_sfixed(0.0, x_in);
-
- wait for 40*PERIOD;
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(1.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
-
- wait for 150*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk, fileout_enable)
- file RESULT_FIR: text open write_mode is "fir.txt";
- variable L: line;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' then
- fprint(RESULT_FIR, L,"%s\n", REAL'image(yo));
- end if;
-
- END PROCESS;
-
-END;
diff --git a/lib/fix_std/fix_std.vhd b/lib/fix_std/fix_std.vhd
deleted file mode 100644
index 6397ebc..0000000
--- a/lib/fix_std/fix_std.vhd
+++ /dev/null
@@ -1,1007 +0,0 @@
----------------------------------------------------------------------
---
--- Package fix_std
--- Fixed point arithmetic based on numeric_std
---
----------------------------------------------------------------------
---
--- This document describes a VHDL package of definitions and subprograms
--- intended to support the use of fixed-point arithmetic in test benches
--- and synthesisable designs. This document and the package it describes
--- are made freely available to the HDL design community without warranty
--- of any kind. You are welcome to make use of this information for your
--- own private study and in your own designs. If you make use of the
--- package, you accept sole responsibility for its fitness for purpose
--- and its suitability in your application. You are free to modify the
--- package in any way, and to record your contribution to it, but this
--- notice must appear in a prominent place in any modified or derived
--- version of the package or its supporting documentation.
---
--- The author wishes to thank his employer Doulos Ltd for making
--- available the facilities used to develop, test and distribute this
--- package. However, Doulos Ltd accepts no responsibility for the
--- package's contents and cannot support it in any way.
---
----------------------------------------------------------------------
--- Revision information:
---
--- Version 0.1 06-May-2003
--- Alpha version, for review
--- No division operators are provided, pending detailed
--- consultation on their functionality.
--- Some subprogram implementations are unnecessarily inefficient.
--- Version 0.2 11-Jun-2003
--- Fixes aiming to make the package portable across all synthesis tools:
--- * Removed deferred constants, made them package constants
--- * Removed all variable initialisations in procedures, made them
--- procedural initialisations in the code
----------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-package fix_std is
-
- --------------------------------------------------------------------
-
- -- Integer subtype specifying legal values for a bit index.
- -- At present it's restricted to 'natural' to conform with
- -- the behaviour of mainstream synthesis tools. For simulation,
- -- or in the future when synthesis tools are able to cope, it
- -- would be possible to change this subtype to be the full
- -- integer range, thus allowing negative subscripts for
- -- fraction bits.
- --
- subtype Fix_Subscr is natural;
-
- -- Fixed-point offset, the bit number (subscript) used for
- -- the bit in a UFix or SFix vector having binary weight 2^0
- -- (the units bit).
- --
- constant FixP: Fix_Subscr := 100;
-
- -- Type declarations for the basic unsigned and signed fixed point
- -- data types:
- --
- type UFix is array (Fix_Subscr range <>) of std_logic;
- type SFix is array (Fix_Subscr range <>) of std_logic;
-
- -- Type declarations for control of rounding and overflow modes:
- --
- type Fix_Rounding_Mode is (
- clip_LS, -- Throw away unwanted least significant bits
- towards_zero, -- Round towards zero - same as clip_LS for UFix
- to_nearest -- Round to nearest. Exact halves round up.
- );
- type Fix_Overflow_Mode is (
- clip_MS, -- Throw away unwanted most significant bits
- saturate -- Saturate overflow to nearest representable value
- );
-
- -- Defaults for these modes:
- --
- constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS;
- constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS;
-
- --------------------------------------------------------------------
-
- ---------------------------
- -- E. Extraction functions
- ---------------------------
-
- -- E.1. Return the integral part of a UFix value
- function Int(U: UFix) return UFix;
-
- -- E.2. Return the fractional part of a UFix value
- function Frac(U: UFix) return UFix;
-
- -- E.3. Return the integral part of a SFix value
- function Int(S: SFix) return SFix;
-
- -- E.4. Return the fractional part of a SFix value
- function Frac(S: SFix) return UFix;
-
- -- E.5. Widen a SFix value if necessary so that
- -- its range adjoins or spans the binary point
- function Span(S: SFix) return SFix;
-
- -- E.6. Widen a UFix value if necessary so that
- -- its range adjoins or spans the binary point
- function Span(U: UFix) return UFix;
-
- ---------------------------
- -- T. Conversion functions
- ---------------------------
-
- -- T.1 to T.8: Unsigned conversions
- --
- -- T.1. Resizing an existing UFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_UFix(
- N : UFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix;
-
- -- T.2. Resizing an existing SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_UFix(
- N : SFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix;
-
- -- T.3. Conversion from integer to UFix. Provide number of
- -- integer bits and number of fraction bits. Note that
- -- negative input is tolerated!
- --
- function to_UFix(
- N : integer;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix;
-
- -- T.4. Conversion from unsigned to UFix. Provide subscripts of
- -- MS and (optionally) LS bit of the resulting UFix.
- --
- function to_UFix(
- N : unsigned;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix;
-
- -- T.5. Conversion from unsigned to UFix. Automatically set the
- -- range of the resulting UFix to match the unsigned value,
- -- as an integral UFix value with no fraction bits.
- --
- function to_UFix( N : unsigned ) return UFix;
-
- -- T.6. Conversion from UFix to unsigned. All integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_unsigned(
- N : UFix;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return unsigned;
-
- -- T.7. Conversion from UFix to unsigned. Caller specifies
- -- required number of bits in unsigned result.
- --
- function to_unsigned(
- N : UFix;
- bits : positive;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return unsigned;
-
- -- T.8. Conversion from UFix to integer. Up to 31 integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_integer(
- N : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return integer;
-
-
- -- T.9 to T.16: Signed conversions
- --
- -- T.9. Resizing an existing UFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : UFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix;
-
- -- T.10. Resizing an existing SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : SFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix;
-
- -- T.11. Conversion from integer to SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : integer;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix;
-
- -- T.12. Conversion from signed to SFix. Provide subscripts of
- -- MS and (optionally) LS bit of the resulting SFix.
- --
- function to_SFix(
- N : signed;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix;
-
- -- T.13. Conversion from signed to SFix. Automatically set the
- -- range of the resulting SFix to match the signed value,
- -- as an integral SFix value with no fraction bits.
- --
- function to_SFix( N : signed ) return SFix;
-
- -- T.14. Conversion from SFix to signed. All integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_signed(
- N : SFix;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return signed;
-
- -- T.15. Conversion from SFix to signed. Caller specifies
- -- required number of bits in signed result.
- --
- function to_signed(
- N : SFix;
- bits : positive;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return signed;
-
- -- T.16. Conversion from SFix to integer. Up to 32 integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_integer(
- N : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return integer;
-
- -- T.17. Conversion from UFix to SFix. This simply adds
- -- an extra more significant bit, set to zero.
- --
- function to_SFix(U: UFix) return SFix;
-
- ----------------------------------
- -- V. Copy-to-variable procedures
- ----------------------------------
-
- -- Range-aware copying of an expression into a variable. The
- -- ranges of destination variable and source expression are
- -- used to determine correct rounding, overflow and scaling
- -- behaviour.
-
- -- V.1 to V.5: Copy an expression into a UFix variable
- --
-
- -- V.1. Copy UFix to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
- --
- -- V.2. Copy SFix to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.3. Copy UNSIGNED to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.4. Copy SIGNED to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.5. Copy integer to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.6 to V.10: Copy an expression into a SFix variable
- --
-
- -- V.6. Copy UFix to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.7. Copy SFix to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.8. Copy UNSIGNED to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.9. Copy SIGNED to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.10. Copy integer to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
-
- --------------------------------
- -- S. Copy-to-signal procedures
- --------------------------------
- --
- -- Range-aware copying of an expression into a signal. The
- -- ranges of destination signal and source expression are
- -- used to determine correct rounding, overflow and scaling
- -- behaviour.
-
- -- S.1 to S.5: Copy an expression into a UFix signal
- --
-
- -- S.1. Copy UFix to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.1. Copy SFix to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.3. Copy UNSIGNED to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.4. Copy SIGNED to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.5. Copy integer to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.6 to S.10: Copy an expression into a SFix signal
- --
-
- -- S.6. Copy UFix to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.7. Copy SFix to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.8. Copy UNSIGNED to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.9. Copy SIGNED to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.10. Copy integer to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
-
- ------------------------------------------------------------------
- -- A. Arithmetic operations involving UFix, SFix and other
- -- numeric types.
- -- The operators are overloaded for most of the sensible
- -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
- --
- -- IMPORTANT NOTE:
- -- Arithmetic operators return a result that is wide enough
- -- and precise enough so that no information is lost. THIS IS
- -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std.
- -- In the detailed description that follow, "scaling" means
- -- the numerical value (weight) of the least significant bit
- -- in a fixed-point value.
- --
- -- ADDITION returns a result whose least significant bit
- -- is the same as the least significant bit in either operand,
- -- and whose most significant bit is one position higher than
- -- the most significant bit in either operand. Addition of
- -- two operands having the same bounds therefore results in
- -- a growth of one bit at the most significant end.
- --
- -- SUBTRACTION where one or both operands are signed behaves
- -- in the same way as addition. Subtraction where both operands
- -- are unsigned returns a result whose most significant bit
- -- position is the same as the most significant bit in either
- -- operand, and whose least significant bit is the same as the
- -- least significant bit in either operand.
- --
- -- MULTIPLICATION returns a result whose width is the sum of
- -- the widths of its two operands, and whose scaling is the
- -- product of its two operands' scalings.
- --
- -- UNARY NEGATION always gives a result having one more
- -- significant bit than the operand.
- --
- -- ABSOLUTE VALUE always gives a result having exactly the
- -- same subtype as its operand.
- --
- -- In binary operations where one operand is a fixed-point type
- -- and the other is an integer numeric type, the integer operand
- -- is first converted to a fixed-point type of the same subtype
- -- as the other operand using Copy_V with default rounding and
- -- overflow modes. The operation is then performed between two
- -- fixed-point operands in the normal way.
- --
- ------------------------------------------------------------------
-
-
- ------------------------------------
- -- A.1. Unary "-" negation operator
- ------------------------------------
-
- -- A.1.1. SFix := - UFix
- function "-" (R: UFix) return SFix;
-
- -- A.1.2. SFix := - SFix
- function "-" (R: SFix) return SFix;
-
-
- --------------------------------------------
- -- A.2. Unary "abs" absolute-value operator
- --------------------------------------------
-
- -- A.2.1. SFix := abs SFix
- function "abs" (R: SFix) return SFix;
-
-
- -------------------------------------
- -- A.3. Binary "+" addition operator
- -------------------------------------
-
- -- A.3.1. UFix := UFix + UFix
- function "+" (L: UFix; R: UFix) return UFix;
-
- -- A.3.2. UFix := UFix + unsigned
- function "+" (L: UFix; R: unsigned) return UFix;
-
- -- A.3.3. UFix := unsigned + UFix
- function "+" (L: unsigned; R: UFix) return UFix;
-
- -- A.3.4. UFix := UFix + natural
- function "+" (L: UFix; R: natural) return UFix;
-
- -- A.3.5. UFix := natural + UFix
- function "+" (L: natural; R: UFix) return UFix;
-
- -- A.3.6. SFix := SFix + SFix
- function "+" (L: SFix; R: SFix) return SFix;
-
- -- A.3.7. SFix := SFix + UFix
- function "+" (L: SFix; R: UFix) return SFix;
-
- -- A.3.8. SFix := UFix + SFix
- function "+" (L: UFix; R: SFix) return SFix;
-
- -- A.3.9. SFix := SFix + signed
- function "+" (L: SFix; R: signed) return SFix;
-
- -- A.3.10. SFix := signed + SFix
- function "+" (L: signed; R: SFix) return SFix;
-
- -- A.3.11. SFix := SFix + integer
- function "+" (L: SFix; R: integer) return SFix;
-
- -- A.3.12. SFix := integer + SFix
- function "+" (L: integer; R: SFix) return SFix;
-
-
- ----------------------------------------
- -- A.4. Binary "-" subtraction operator
- ----------------------------------------
- --
- -- NOTE: There is a special problem with subtraction
- -- operators that return a UFix result if that result
- -- goes negative. Our arbitrary decision is that we
- -- truncate most-significant bits in this case. If you
- -- wish to avoid the risk of this arbitrarily-defined
- -- truncation behaviour, change one or more of your
- -- operands to SFix and get a SFix result using this
- -- idiom:
- -- SFix := UFix + (-UFix)
- -- or copy one of the UFix operands into a SFix that's
- -- one bit wider, before performing the operation.
- --
- -- Subtractions returning a UFix result take unsigned
- -- operands and do not exhibit bit growth.
- -- Subtractions returning a SFix result take signed or
- -- unsigned operands and exhibit one-bit growth like addition.
-
- -- A.4.1. UFix := UFix - UFix
- function "-" (L: UFix; R: UFix) return UFix;
-
- -- A.4.2. UFix := UFix - unsigned
- function "-" (L: UFix; R: unsigned) return UFix;
-
- -- A.4.3. UFix := unsigned - UFix
- function "-" (L: unsigned; R: UFix) return UFix;
-
- -- A.4.4. UFix := UFix - natural
- function "-" (L: UFix; R: natural) return UFix;
-
- -- A.4.5. UFix := natural - UFix
- function "-" (L: natural; R: UFix) return UFix;
-
- -- A.4.6. SFix := SFix - SFix
- function "-" (L: SFix; R: SFix) return SFix;
-
- -- A.4.7. SFix := SFix - UFix
- function "-" (L: SFix; R: UFix) return SFix;
-
- -- A.4.8. SFix := UFix - SFix
- function "-" (L: UFix; R: SFix) return SFix;
-
- -- A.4.9. SFix := SFix - signed
- function "-" (L: SFix; R: signed) return SFix;
-
- -- A.4.10. SFix := signed - SFix
- function "-" (L: signed; R: SFix) return SFix;
-
- -- A.4.11. SFix := SFix - integer
- function "-" (L: SFix; R: integer) return SFix;
-
- -- A.4.12. SFix := integer - SFix
- function "-" (L: integer; R: SFix) return SFix;
-
-
- -------------------------------------------
- -- A.5. Binary "*" multiplication operator
- -------------------------------------------
-
- -- A.5.1. UFix := UFix * UFix
- function "*" (L: UFix; R: UFix) return UFix;
-
- -- A.5.2. UFix := UFix * unsigned
- function "*" (L: UFix; R: unsigned) return UFix;
-
- -- A.5.3. UFix := unsigned * UFix
- function "*" (L: unsigned; R: UFix) return UFix;
-
- -- A.5.4. UFix := UFix * natural
- function "*" (L: UFix; R: natural) return UFix;
-
- -- A.5.5. UFix := natural * UFix
- function "*" (L: natural; R: UFix) return UFix;
-
- -- A.5.6. SFix := SFix * SFix
- function "*" (L: SFix; R: SFix) return SFix;
-
- -- A.5.7. SFix := SFix * UFix
- function "*" (L: SFix; R: UFix) return SFix;
-
- -- A.5.8. SFix := UFix * SFix
- function "*" (L: UFix; R: SFix) return SFix;
-
- -- A.5.9. SFix := SFix * signed
- function "*" (L: SFix; R: signed) return SFix;
-
- -- A.5.10. SFix := signed * SFix
- function "*" (L: signed; R: SFix) return SFix;
-
- -- A.5.11. SFix := SFix * integer
- function "*" (L: SFix; R: integer) return SFix;
-
- -- A.5.12. SFix := integer * SFix
- function "*" (L: integer; R: SFix) return SFix;
-
-
- ------------------------------------------------------------------
- -- R. Relational operators - arithmetic comparisons involving
- -- UFix, SFix and other numeric types.
- -- The operators are overloaded for most of the sensible
- -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
- -- Note that in all cases comparisons are exact; if one
- -- operand has more fraction bits than the other, the less
- -- precise operand will have its LSBs zero-extended, and
- -- these zero bits will take part in comparison with whatever
- -- LSBs exist in the more precise operand.
- ------------------------------------------------------------------
-
- -------------------------------------
- -- R.1. Binary "=" equality operator
- -------------------------------------
-
- -- R.1.1. UFix = UFix
- function "=" (L: UFix; R: UFix) return boolean;
-
- -- R.1.2. UFix = unsigned
- function "=" (L: UFix; R: unsigned) return boolean;
-
- -- R.1.3. unsigned = UFix
- function "=" (L: unsigned; R: UFix) return boolean;
-
- -- R.1.4. UFix = integer
- function "=" (L: UFix; R: integer) return boolean;
-
- -- R.1.5. integer = UFix
- function "=" (L: integer; R: UFix) return boolean;
-
- -- R.1.6. SFix = SFix
- function "=" (L: SFix; R: SFix) return boolean;
-
- -- R.1.7. SFix = UFix
- function "=" (L: SFix; R: UFix) return boolean;
-
- -- R.1.8. UFix = SFix
- function "=" (L: UFix; R: SFix) return boolean;
-
- -- R.1.9. SFix = signed
- function "=" (L: SFix; R: signed) return boolean;
-
- -- R.1.10. signed = SFix
- function "=" (L: signed; R: SFix) return boolean;
-
- -- R.1.11. SFix = integer
- function "=" (L: SFix; R: integer) return boolean;
-
- -- R.1.12. integer = SFix
- function "=" (L: integer; R: SFix) return boolean;
-
-
- --------------------------------------
- -- R.2. Binary "<" less-than operator
- --------------------------------------
-
- -- R.2.1. UFix < UFix
- function "<" (L: UFix; R: UFix) return boolean;
-
- -- R.2.2. UFix < unsigned
- function "<" (L: UFix; R: unsigned) return boolean;
-
- -- R.2.3. unsigned < UFix
- function "<" (L: unsigned; R: UFix) return boolean;
-
- -- R.2.4. UFix < integer
- function "<" (L: UFix; R: integer) return boolean;
-
- -- R.2.5. integer < UFix
- function "<" (L: integer; R: UFix) return boolean;
-
- -- R.2.6. SFix < SFix
- function "<" (L: SFix; R: SFix) return boolean;
-
- -- R.2.7. SFix < UFix
- function "<" (L: SFix; R: UFix) return boolean;
-
- -- R.2.8. UFix < SFix
- function "<" (L: UFix; R: SFix) return boolean;
-
- -- R.2.9. SFix < signed
- function "<" (L: SFix; R: signed) return boolean;
-
- -- R.2.10. signed < SFix
- function "<" (L: signed; R: SFix) return boolean;
-
- -- R.2.11. SFix < integer
- function "<" (L: SFix; R: integer) return boolean;
-
- -- R.2.12. integer < SFix
- function "<" (L: integer; R: SFix) return boolean;
-
-
- ----------------------------------------
- -- R.3. Binary "/=" inequality operator
- ----------------------------------------
-
- -- R.3.1. UFix /= UFix
- function "/=" (L: UFix; R: UFix) return boolean;
-
- -- R.3.2. UFix /= unsigned
- function "/=" (L: UFix; R: unsigned) return boolean;
-
- -- R.3.3. unsigned /= UFix
- function "/=" (L: unsigned; R: UFix) return boolean;
-
- -- R.3.4. UFix /= integer
- function "/=" (L: UFix; R: integer) return boolean;
-
- -- R.3.5. integer /= UFix
- function "/=" (L: integer; R: UFix) return boolean;
-
- -- R.3.6. SFix /= SFix
- function "/=" (L: SFix; R: SFix) return boolean;
-
- -- R.3.7. SFix /= UFix
- function "/=" (L: SFix; R: UFix) return boolean;
-
- -- R.3.8. UFix /= SFix
- function "/=" (L: UFix; R: SFix) return boolean;
-
- -- R.3.9. SFix /= signed
- function "/=" (L: SFix; R: signed) return boolean;
-
- -- R.3.10. signed /= SFix
- function "/=" (L: signed; R: SFix) return boolean;
-
- -- R.3.11. SFix /= integer
- function "/=" (L: SFix; R: integer) return boolean;
-
- -- R.3.12. integer /= SFix
- function "/=" (L: integer; R: SFix) return boolean;
-
-
- -----------------------------------------
- -- R.4. Binary ">" greater-than operator
- -----------------------------------------
-
- -- R.4.1. UFix > UFix
- function ">" (L: UFix; R: UFix) return boolean;
-
- -- R.4.2. UFix > unsigned
- function ">" (L: UFix; R: unsigned) return boolean;
-
- -- R.4.3. unsigned > UFix
- function ">" (L: unsigned; R: UFix) return boolean;
-
- -- R.4.4. UFix > integer
- function ">" (L: UFix; R: integer) return boolean;
-
- -- R.4.5. integer > UFix
- function ">" (L: integer; R: UFix) return boolean;
-
- -- R.4.6. SFix > SFix
- function ">" (L: SFix; R: SFix) return boolean;
-
- -- R.4.7. SFix > UFix
- function ">" (L: SFix; R: UFix) return boolean;
-
- -- R.4.8. UFix > SFix
- function ">" (L: UFix; R: SFix) return boolean;
-
- -- R.4.9. SFix > signed
- function ">" (L: SFix; R: signed) return boolean;
-
- -- R.4.10. signed > SFix
- function ">" (L: signed; R: SFix) return boolean;
-
- -- R.4.11. SFix > integer
- function ">" (L: SFix; R: integer) return boolean;
-
- -- R.4.12. integer > SFix
- function ">" (L: integer; R: SFix) return boolean;
-
-
- ----------------------------------------------
- -- R.5. Binary ">=" greater-or-equal operator
- ----------------------------------------------
-
- -- R.5.1. UFix >= UFix
- function ">=" (L: UFix; R: UFix) return boolean;
-
- -- R.5.2. UFix >= unsigned
- function ">=" (L: UFix; R: unsigned) return boolean;
-
- -- R.5.3. unsigned >= UFix
- function ">=" (L: unsigned; R: UFix) return boolean;
-
- -- R.5.4. UFix >= integer
- function ">=" (L: UFix; R: integer) return boolean;
-
- -- R.5.5. integer >= UFix
- function ">=" (L: integer; R: UFix) return boolean;
-
- -- R.5.6. SFix >= SFix
- function ">=" (L: SFix; R: SFix) return boolean;
-
- -- R.5.7. SFix >= UFix
- function ">=" (L: SFix; R: UFix) return boolean;
-
- -- R.5.8. UFix >= SFix
- function ">=" (L: UFix; R: SFix) return boolean;
-
- -- R.5.9. SFix >= signed
- function ">=" (L: SFix; R: signed) return boolean;
-
- -- R.5.10. signed >= SFix
- function ">=" (L: signed; R: SFix) return boolean;
-
- -- R.5.11. SFix >= integer
- function ">=" (L: SFix; R: integer) return boolean;
-
- -- R.5.12. integer >= SFix
- function ">=" (L: integer; R: SFix) return boolean;
-
-
- -------------------------------------------
- -- R.6. Binary "<=" less-or-equal operator
- -------------------------------------------
-
- -- R.6.1. UFix <= UFix
- function "<=" (L: UFix; R: UFix) return boolean;
-
- -- R.6.2. UFix <= unsigned
- function "<=" (L: UFix; R: unsigned) return boolean;
-
- -- R.6.3. unsigned <= UFix
- function "<=" (L: unsigned; R: UFix) return boolean;
-
- -- R.6.4. UFix <= integer
- function "<=" (L: UFix; R: integer) return boolean;
-
- -- R.6.5. integer <= UFix
- function "<=" (L: integer; R: UFix) return boolean;
-
- -- R.6.6. SFix <= SFix
- function "<=" (L: SFix; R: SFix) return boolean;
-
- -- R.6.7. SFix <= UFix
- function "<=" (L: SFix; R: UFix) return boolean;
-
- -- R.6.8. UFix <= SFix
- function "<=" (L: UFix; R: SFix) return boolean;
-
- -- R.6.9. SFix <= signed
- function "<=" (L: SFix; R: signed) return boolean;
-
- -- R.6.10. signed <= SFix
- function "<=" (L: signed; R: SFix) return boolean;
-
- -- R.6.11. SFix <= integer
- function "<=" (L: SFix; R: integer) return boolean;
-
- -- R.6.12. integer <= SFix
- function "<=" (L: integer; R: SFix) return boolean;
-
-
- ------------------------------------------------------------------
- -- C. Concatenation operators between fixed-point operands, and
- -- between fixed-point operands and other reasonable types.
- -- Unlike the implicitly defined "&" operator, they preserve
- -- place value and return an appropriately aligned subtype.
- -- Preservation of place value means that some concatenation
- -- operations are illegal. In particular, operations
- -- [SFix & SFix] and [UFix & SFix] are illegal, and
- -- the place values of operands in [SFix & UFix] and
- -- [UFix & UFix] must match up - the rightmost subscript of
- -- the left operand must be one higher than the leftmost
- -- subscript of the right operand.
- -- Single bits of type std_ulogic may be concatenated with
- -- fixed-point types where there is no risk of losing
- -- sign-extension information.
- -- Because of the way VHDL defines implicit concatenation,
- -- it is impossible to detect all these errors at compile time.
- -- Instead they are detected by assertion statements at run time.
- -- Tool vendors may choose to implement compile-time checks
- -- so that the run-time checking overhead can be avoided.
- ------------------------------------------------------------------
-
- -- C.1.1. UFix := UFix & UFix
- function "&" (L: UFix; R: UFix) return UFix;
-
- -- No need to define "&"[UFix, SFix] explicitly, because
- -- the types are incompatible and so there's no default
-
- -- C.1.2. UFix := UFix & std_ulogic
- function "&" (L: UFix; R: std_ulogic) return UFix;
-
- -- C.1.3. UFix := std_ulogic & UFix
- function "&" (L: std_ulogic; R: UFix) return UFix;
-
-
- -- C.2.1. SFix := SFix & UFix
- function "&" (L: SFix; R: UFix) return SFix;
-
- -- C.2.2. SFix := SFix & SFix -- ILLEGAL
- function "&" (L: SFix; R: SFix) return SFix;
-
- -- C.2.3. SFix := SFix & std_ulogic
- function "&" (L: SFix; R: std_ulogic) return SFix;
-
- -- C.2.4. SFix := std_ulogic & SFix
- function "&" (L: std_ulogic; R: SFix) return SFix;
-
-
-end; -- package fix_std;
diff --git a/lib/fix_std/fix_stdb.vhd b/lib/fix_std/fix_stdb.vhd
deleted file mode 100644
index 695cd11..0000000
--- a/lib/fix_std/fix_stdb.vhd
+++ /dev/null
@@ -1,1910 +0,0 @@
----------------------------------------------------------------------
---
--- Package body fix_std
--- Fixed point arithmetic based on numeric_std
--- Compile using VHDL-93 (required to support 'ASCENDING
--- array attribute).
---
----------------------------------------------------------------------
---
--- This document describes a VHDL package of definitions and subprograms
--- intended to support the use of fixed-point arithmetic in test benches
--- and synthesisable designs. This document and the package it describes
--- are made freely available to the HDL design community without warranty
--- of any kind. You are welcome to make use of this information for your
--- own private study and in your own designs. If you make use of the
--- package, you accept sole responsibility for its fitness for purpose
--- and its suitability in your application. You are free to modify the
--- package in any way, and to record your contribution to it, but this
--- notice must appear in a prominent place in any modified or derived
--- version of the package or its supporting documentation.
---
--- The author wishes to thank his employer Doulos Ltd for making
--- available the facilities used to develop, test and distribute this
--- package. However, Doulos Ltd accepts no responsibility for the
--- package's contents and cannot support it in any way.
---
----------------------------------------------------------------------
--- Revision information:
---
--- Version 0.1 06-May-2003
--- Alpha version, for review
--- No division operators are provided, pending detailed
--- consultation on their functionality.
--- Some subprogram implementations are unnecessarily inefficient.
--- Version 0.2 11-Jun-2003
--- Fixes aiming to make the package portable across all synthesis tools:
--- * Removed deferred constants, made them package constants
--- * Removed all variable initialisations in procedures, made them
--- procedural initialisations in the code
--- * Fixed definition of extract functions to return just one bit
--- if their results would otherwise be null
----------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-package body fix_std is
-
- --------------------------------------------------------------------
- -- DEFERRED CONSTANTS
- --------------------------------------------------------------------
- -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC
- -- IMPLEMENTATIONS OR APPLICATIONS.
- --------------------------------------------------------------------
-
- -- Fixed-point offset, the bit number (subscript) used for
- -- the bit in a UFix or SFix vector having binary weight 2^0
- -- (the units bit).
- --
- -- constant FixP : Fix_Subscr := 100;
-
- -- Default values for overflow and rounding modes:
- --
- -- constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS;
- -- constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS;
-
- --------------------------------------------------------------------
- -- END OF DEFERRED CONSTANTS
- --------------------------------------------------------------------
-
- --------------------------------------------------------------------
- -- IMPLEMENTATION CONSTANTS
- --------------------------------------------------------------------
- -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC
- -- IMPLEMENTATIONS OR APPLICATIONS.
- --------------------------------------------------------------------
-
- -- Severity levels for various errors
-
- -- Concatenation errors - bad sign extension, discontiguous range etc
- -- These are only warnings - they just give the wrong answer.
- --
- constant concat_severity : severity_level := WARNING;
-
- -- Subtype direction errors - the present implementation can't
- -- handle fixed-point objects with ascending ranges. These messages
- -- are intended to give early warning of problems that would
- -- definitely cause other fatal errors at elaboration or run time.
- --
- constant direction_severity : severity_level := FAILURE;
-
- -- Assertion error message constants
-
- constant bad_direction_msg : string :=
- " has ascending range";
-
- constant concat_range_msg : string :=
- "Concatenation bounds should have contiguous ranges";
-
- constant concat_sxt_msg : string :=
- "Concatenation corrupts sign of result";
-
- constant concat_signLS_msg : string :=
- "RHS of concatenation should be unsigned";
-
- constant compare_meta_msg : string :=
- "Metavalue detected in FIX_STD comparison, returning FALSE";
-
- --------------------------------------------------------------------
- -- END OF IMPLEMENTATION CONSTANTS
- --------------------------------------------------------------------
-
- --------------------------------------------------------------------
- -- DO NOT MODIFY ANY CODE BELOW THIS POINT.
- --------------------------------------------------------------------
-
- -- Assumed bit width of INTEGER type in VHDL
- --
- constant INT_WIDTH : positive := 32;
-
- -- Single-bit zero values
- subtype Izero_UFixT is UFix(FixP downto FixP);
- subtype Izero_SFixT is SFix(FixP downto FixP);
- subtype Fzero_UFixT is UFix(FixP-1 downto FixP-1);
- constant Izero_UFix: Izero_UFixT := "0";
- constant Izero_SFix: Izero_SFixT := "0";
- constant Fzero_UFix: Fzero_UFixT := "0";
-
- --------------------------------------------------------------------
- -- LOCAL PRIVATE SUBPROGRAMS
- --------------------------------------------------------------------
-
- -- Min, Max: Find minimum and maximum of two integers.
- -- Useful for determining appropriate range for operation results.
- --
- function Max(L, R: Fix_Subscr) return Fix_Subscr is
- begin
- if L>R then
- return L;
- else
- return R;
- end if;
- end;
- --
- function Min(L, R: Fix_Subscr) return Fix_Subscr is
- begin
- if L FixP then
- return Span(U);
- else
- return U(U'LEFT downto FixP);
- end if;
- end;
-
- -- E.2. Return the fractional part of a UFix value
- function Frac(U: UFix) return UFix is
- begin
- if U'LEFT < FixP-1 then
- return Span(U);
- elsif U'RIGHT >= FixP then
- return Fzero_UFix;
- else
- return U(FixP-1 downto U'RIGHT);
- end if;
- end;
-
- -- E.3. Return the integral part of a SFix value
- function Int(S: SFix) return SFix is
- begin
- if S'LENGTH = 0 then
- return Izero_SFix;
- elsif S'LEFT <= FixP then
- return SFix'(FixP => S(S'LEFT));
- elsif S'RIGHT > FixP then
- return Span(S);
- else
- return S(S'LEFT downto FixP);
- end if;
- end;
-
- -- E.4. Return the fractional part of a SFix value
- function Frac(S: SFix) return UFix is
- variable P: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP));
- begin
- if S'LEFT < FixP then
- for I in FixP-1 downto S'LEFT+1 loop
- P(I) := S(S'LEFT);
- end loop;
- P(S'RANGE) := S;
- return UFix(S(FixP-1 downto S'RIGHT));
- elsif S'RIGHT >= FixP then
- return Fzero_UFix;
- else
- return UFix(S(FixP-1 downto S'RIGHT));
- end if;
- end;
-
- -- E.5. Widen a SFix value if necessary so that
- -- its range adjoins or spans the binary point
- function Span(S: SFix) return SFix is
- variable F: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP));
- begin
- F(S'RANGE) := S;
- for I in F'LEFT downto S'LEFT+1 loop
- F(I) := S(S'LEFT);
- end loop;
- for I in S'RIGHT-1 downto F'RIGHT loop
- F(I) := '0';
- end loop;
- return F;
- end;
-
- -- E.6. Widen a UFix value if necessary so that
- -- its range adjoins or spans the binary point
- function Span(U: UFix) return UFix is
- variable F: UFix(Max(U'LEFT, FixP-1) downto Min(U'RIGHT, FixP));
- begin
- F(U'RANGE) := U;
- for I in F'LEFT downto U'LEFT+1 loop
- F(I) := '0';
- end loop;
- for I in U'RIGHT-1 downto F'RIGHT loop
- F(I) := '0';
- end loop;
- return F;
- end;
-
- ---------------------------
- -- T. Conversion functions
- ---------------------------
-
- -- T.1 to T.8: Unsigned conversions
-
- -- T.1. Resizing an existing UFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_UFix(
- N : UFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix is
- variable F: UFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.2. Resizing an existing SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_UFix(
- N : SFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix is
- variable F: UFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.3. Conversion from integer to UFix. Provide number of
- -- integer bits and number of fraction bits. Note that
- -- negative input is tolerated!
- --
- function to_UFix(
- N : integer;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix is
- variable F: UFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.4. Conversion from unsigned to UFix. Provide subscripts of
- -- MS and (optionally) LS bit of the resulting UFix.
- --
- function to_UFix(
- N : unsigned;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix is
- variable F: UFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.5. Conversion from unsigned to UFix. Automatically set the
- -- range of the resulting UFix to match the unsigned value,
- -- as an integral UFix value with no fraction bits.
- --
- function to_UFix( N : unsigned ) return UFix is
- variable F: UFix(FixP+N'LENGTH-1 downto FixP);
- begin
- F := UFix(N);
- return F;
- end;
-
- -- T.6. Conversion from UFix to unsigned. All integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_unsigned(
- N : UFix;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return unsigned is
- variable F_UFix: UFix(N'LEFT downto FixP);
- variable F: unsigned(F_UFix'LENGTH-1 downto 0);
- begin
- Copy_V(F_UFix, N, rounding=>rounding);
- F := unsigned(F_UFix);
- return F;
- end;
-
- -- T.7. Conversion from UFix to unsigned. Caller specifies
- -- required number of bits in unsigned result.
- --
- function to_unsigned(
- N : UFix;
- bits : positive;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return unsigned is
- variable F_UFix: UFix(FixP+bits-1 downto FixP);
- variable F: unsigned(F_UFix'LENGTH-1 downto 0);
- begin
- Copy_V(F_UFix, N, overflow, rounding);
- F := unsigned(F_UFix);
- return F;
- end;
-
- -- T.8. Conversion from UFix to integer. Up to 31 integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_integer(
- N : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return integer is
- variable F_UFix: UFix(Min(FixP+INT_WIDTH-2, N'LEFT) downto FixP);
- begin
- Copy_V(F_UFix, N, overflow, rounding);
- return to_integer(unsigned(F_UFix));
- end;
-
- -- T.9 to T.16: Signed conversions
-
- -- T.9. Resizing an existing UFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : UFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix is
- variable F: SFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.10. Resizing an existing SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : SFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix is
- variable F: SFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.11. Conversion from integer to SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : integer;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix is
- variable F: SFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.12. Conversion from signed to SFix. Provide subscripts of
- -- MS and (optionally) LS bit of the resulting SFix.
- --
- function to_SFix(
- N : signed;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix is
- variable F: SFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.13. Conversion from signed to SFix. Automatically set the
- -- range of the resulting SFix to match the signed value,
- -- as an integral SFix value with no fraction bits.
- --
- function to_SFix( N : signed ) return SFix is
- variable F: SFix(FixP+N'LENGTH-1 downto FixP);
- begin
- F := SFix(N);
- return F;
- end;
-
- -- T.14. Conversion from SFix to signed. All integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_signed(
- N : SFix;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return signed is
- variable F_SFix: SFix(N'LEFT downto FixP);
- variable F: signed(F_SFix'LENGTH-1 downto 0);
- begin
- Copy_V(F_SFix, N, rounding=>rounding);
- F := signed(F_SFix);
- return F;
- end;
-
- -- T.15. Conversion from SFix to signed. Caller specifies
- -- required number of bits in signed result.
- --
- function to_signed(
- N : SFix;
- bits : positive;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return signed is
- variable F_SFix: UFix(FixP+bits-1 downto FixP);
- variable F: signed(F_SFix'LENGTH-1 downto 0);
- begin
- Copy_V(F_SFix, N, overflow, rounding);
- F := signed(F_SFix);
- return F;
- end;
-
- -- T.16. Conversion from SFix to integer. Up to 32 integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_integer(
- N : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return integer is
- variable F_SFix: SFix(Min(FixP+INT_WIDTH-1, N'LEFT) downto FixP);
- begin
- Copy_V(F_SFix, N, overflow, rounding);
- return to_integer(signed(F_SFix));
- end;
-
- -- T.17. Conversion from UFix to SFix. This simply adds
- -- an extra more significant bit, set to zero.
- --
- function to_SFix(U: UFix) return SFix is
- variable F: SFix(U'LEFT+1 downto U'RIGHT);
- begin
- F := SFix('0' & U);
- return F;
- end;
-
-
- ----------------------------------
- -- V. Copy-to-variable procedures
- ----------------------------------
-
- -- Range-aware copying of an expression into a variable. The
- -- ranges of destination variable and source expression are
- -- used to determine correct rounding, overflow and scaling
- -- behaviour.
-
- -- V.1 to V.5: Copy an expression into a UFix variable
-
- -- V.1. Copy UFix to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- subtype target_T is UFix(target'RANGE);
- variable W: UFix(Max(target'LEFT, source'LEFT+1) downto
- Min(target'RIGHT, source'RIGHT));
- constant HighZero: UFix(W'LEFT downto target'LEFT+1) := (others => '0');
- begin
- assert not target'ASCENDING
- report "target" & bad_direction_msg
- severity direction_severity;
- assert not source'ASCENDING
- report "source" & bad_direction_msg
- severity direction_severity;
- W := (others => '0');
- W(source'RANGE) := source;
- if target'RIGHT > source'RIGHT then
- case rounding is
- when clip_LS | towards_zero =>
- null;
- when to_nearest =>
- W(W'LEFT downto target'RIGHT-1) := UFix(
- unsigned(W(W'LEFT downto target'RIGHT-1)) + 1
- );
- end case;
- end if;
- target := W(target'RANGE);
- if HighZero'LENGTH > 0 then
- if unsigned(W(HighZero'RANGE)) /= unsigned(HighZero) then
- case overflow is
- when clip_MS =>
- null;
- when saturate =>
- target := target_T'(others => '1');
- end case;
- end if;
- end if;
- end;
-
- -- V.2. Copy SFix to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable W: SFix(Max(Source'LEFT, target'LEFT) downto target'RIGHT);
- constant target_zero: UFix(target'RANGE) := (others => '0');
- begin
- assert not target'ASCENDING
- report "target" & bad_direction_msg
- severity direction_severity;
- assert not source'ASCENDING
- report "source" & bad_direction_msg
- severity direction_severity;
- W := (others => '0');
- -- Rounding & sign-extend
- Copy_V(W, source, clip_MS, rounding);
- -- Saturation?
- if W < 0 and overflow = saturate then
- target := target_zero;
- else
- Copy_V(target, UFix(W), overflow, clip_LS);
- end if;
- end;
-
- -- V.3. Copy UNSIGNED to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant U: UFix(FixP+source'LENGTH-1 downto FixP) := UFix(source);
- begin
- Copy_V(target, U, overflow, rounding);
- end;
-
- -- V.4. Copy SIGNED to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source);
- begin
- Copy_V(target, S, overflow, rounding);
- end;
-
- -- V.5. Copy integer to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant N: signed(FixP+INT_WIDTH-1 downto FixP)
- := to_signed(source, INT_WIDTH);
- begin
- -- Cop-out, this is very inefficient, but will do for now.
- Copy_V(target, N, overflow, rounding);
- end;
-
- -- V.6 to V.10: Copy an expression into a SFix variable
-
- -- V.6. Copy UFix to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant S: SFix(FixP+source'LENGTH downto FixP) := to_SFix(source);
- begin
- Copy_V(target, S, overflow, rounding);
- end;
-
- -- V.7. Copy SFix to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- subtype target_T is SFix(target'RANGE);
- variable W: SFix(Max(target'LEFT, source'LEFT+1) downto
- Min(target'RIGHT, source'RIGHT));
- variable HighSX: SFix(W'LEFT downto target'LEFT+1);
- begin
- for i in HighSX'RANGE loop
- HighSX(i) := source(source'LEFT);
- end loop;
- assert not target'ASCENDING
- report "target" & bad_direction_msg
- severity direction_severity;
- assert not source'ASCENDING
- report "source" & bad_direction_msg
- severity direction_severity;
- -- Make W a copy of source, duly extended at both ends
- W := (others => '0');
- W(source'RANGE) := source;
- W(HighSX'RANGE) := HighSX;
- -- Do any rounding required
- if target'RIGHT > source'RIGHT then
- case rounding is
- when clip_LS =>
- null;
- when towards_zero =>
- if
- (to_UX01(W(W'LEFT)) = '1') -- it's negative?
- and
- (unsigned(W(target'RIGHT-1 downto W'RIGHT)) /= 0) -- round up?
- then
- W(W'LEFT downto target'RIGHT) := SFix(
- signed(W(W'LEFT downto target'RIGHT)) + 1
- );
- end if;
- when to_nearest =>
- W(W'LEFT downto target'RIGHT-1) := SFix(
- signed(W(W'LEFT downto target'RIGHT-1)) + 1
- );
- end case;
- end if;
- -- Do any overflow required
- target := W(target'RANGE);
- if HighSX'LENGTH > 0 then
- if signed(W(HighSX'RANGE)) /= signed(HighSX) then
- case overflow is
- when clip_MS =>
- null;
- when saturate =>
- target := Target_T'(others => not W(W'LEFT));
- target(target'LEFT) := W(W'LEFT);
- end case;
- end if;
- end if;
- end;
-
- -- V.8. Copy UNSIGNED to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant S: SFix(FixP+source'LENGTH downto FixP) := SFix('0' & source);
- begin
- Copy_V(target, S, overflow, rounding);
- end;
-
- -- V.9. Copy SIGNED to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source);
- begin
- Copy_V(target, S, overflow, rounding);
- end;
-
- -- V.10. Copy integer to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant N: signed(FixP+INT_WIDTH-1 downto FixP)
- := to_signed(source, INT_WIDTH);
- begin
- -- Cop-out, this is very inefficient, but will do for now.
- Copy_V(target, N, overflow, rounding);
- end;
-
-
- --------------------------------
- -- S. Copy-to-signal procedures
- --------------------------------
- --
- -- Range-aware copying of an expression into a signal. The
- -- ranges of destination signal and source expression are
- -- used to determine correct rounding, overflow and scaling
- -- behaviour.
-
- -- S.1 to S.5: Copy an expression into a UFix signal
- --
-
- -- S.1. Copy UFix to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.1. Copy SFix to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.3. Copy UNSIGNED to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.4. Copy SIGNED to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.5. Copy integer to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.6 to S.10: Copy an expression into a SFix signal
- --
-
- -- S.6. Copy UFix to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.7. Copy SFix to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.8. Copy UNSIGNED to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.9. Copy SIGNED to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.10. Copy integer to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
-
- ------------------------------------------------------------------
- -- A. Arithmetic operations involving UFix, SFix and other
- -- numeric types.
- -- The operators are overloaded for most of the sensible
- -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
- --
- -- IMPORTANT NOTE:
- -- Arithmetic operators return a result that is wide enough
- -- and precise enough so that no information is lost. THIS IS
- -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std.
- -- In the detailed description that follow, "scaling" means
- -- the numerical value (weight) of the least significant bit
- -- in a fixed-point value.
- --
- -- ADDITION returns a result whose least significant bit
- -- is the same as the least significant bit in either operand,
- -- and whose most significant bit is one position higher than
- -- the most significant bit in either operand. Addition of
- -- two operands having the same bounds therefore results in
- -- a growth of one bit at the most significant end. Addition
- -- of an integer to a UFix or SFix is accomplished by first
- -- converting the integer to the same subtype as the other
- -- operand, thereby giving rise to one-bit growth; default
- -- truncation and rounding modes are used for the conversion.
- --
- -- SUBTRACTION where one or both operands are signed behaves
- -- in the same way as addition. Subtraction where both operands
- -- are unsigned returns a result whose most significant bit
- -- position is the same as the most significant bit in either
- -- operand, and whose least significant bit is the same as the
- -- least significant bit in either operand.
- --
- -- MULTIPLICATION returns a result whose width is the sum of
- -- the widths of its two operands, and whose scaling is the
- -- product of its two operands' scalings.
- --
- -- UNARY NEGATION always gives a result having one more
- -- significant bit than the operand.
- --
- -- ABSOLUTE VALUE always gives a result having exactly the
- -- same subtype as its operand.
- --
- -- In binary operations where one operand is a fixed-point type
- -- and the other is an integer numeric type, the integer operand
- -- is first converted to a fixed-point type of the same subtype
- -- as the other operand using Copy_V with default rounding and
- -- overflow modes. The operation is then performed between two
- -- fixed-point operands in the normal way.
- --
- ------------------------------------------------------------------
-
-
- ------------------------------------
- -- A.1. Unary "-" negation operator
- ------------------------------------
-
- -- A.1.1. SFix := - UFix
- function "-" (R: UFix) return SFix is
- variable F: SFix(R'LEFT+1 downto R'RIGHT);
- begin
- F := SFix(-(signed('0' & R)));
- return F;
- end;
-
- -- A.1.2. SFix := - SFix
- function "-" (R: SFix) return SFix is
- variable F: SFix(R'LEFT+1 downto R'RIGHT);
- begin
- F := SFix(-(signed(R(R'LEFT) & R)));
- return F;
- end;
-
-
- --------------------------------------------
- -- A.2. Unary "abs" absolute-value operator
- --------------------------------------------
-
- -- A.2.1. SFix := abs SFix
- function "abs" (R: SFix) return SFix is
- variable F: SFix(R'RANGE);
- begin
- F := R;
- if to_X01(R(R'LEFT)) = '1' then
- F := SFix(-(signed(R)));
- end if;
- return F;
- end;
-
-
- -------------------------------------
- -- A.3. Binary "+" addition operator
- -------------------------------------
-
- -- A.3.1. UFix := UFix + UFix
- function "+" (L: UFix; R: UFix) return UFix is
- variable F: UFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right));
- variable LU, RU: unsigned(F'RANGE);
- begin
- LU := (others => '0');
- RU := (others => '0');
- LU(L'RANGE) := unsigned(L);
- RU(R'RANGE) := unsigned(R);
- F := UFix(LU + RU);
- return F;
- end;
-
- -- A.3.2. UFix := UFix + unsigned
- function "+" (L: UFix; R: unsigned) return UFix is
- begin
- return L + to_UFix(R);
- end;
-
- -- A.3.3. UFix := unsigned + UFix
- function "+" (L: unsigned; R: UFix) return UFix is
- begin
- return R+L;
- end;
-
- -- A.3.4. UFix := UFix + natural
- function "+" (L: UFix; R: natural) return UFix is
- variable R_fp: UFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L + R_fp;
- end;
-
- -- A.3.5. UFix := natural + UFix
- function "+" (L: natural; R: UFix) return UFix is
- begin
- return R+L;
- end;
-
- -- A.3.6. SFix := SFix + SFix
- function "+" (L: SFix; R: SFix) return SFix is
- variable F: SFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right));
- variable LS, RS: signed(F'RANGE);
- begin
- LS := (others => '0');
- RS := (others => '0');
- LS(L'RANGE) := signed(L);
- RS(R'RANGE) := signed(R);
- for i in LS'LEFT downto L'LEFT+1 loop LS(i) := L(L'LEFT); end loop;
- for i in RS'LEFT downto R'LEFT+1 loop RS(i) := R(R'LEFT); end loop;
- F := SFix(LS + RS);
- return F;
- end;
-
- -- A.3.7. SFix := SFix + UFix
- function "+" (L: SFix; R: UFix) return SFix is
- begin
- return L + SFix('0' & R);
- end;
-
- -- A.3.8. SFix := UFix + SFix
- function "+" (L: UFix; R: SFix) return SFix is
- begin
- return SFix('0' & L) + R;
- end;
-
- -- A.3.9. SFix := SFix + signed
- function "+" (L: SFix; R: signed) return SFix is
- begin
- return L + to_SFix(R);
- end;
-
- -- A.3.10. SFix := signed + SFix
- function "+" (L: signed; R: SFix) return SFix is
- begin
- return to_SFix(L) + R;
- end;
-
- -- A.3.11. SFix := SFix + integer
- function "+" (L: SFix; R: integer) return SFix is
- variable R_fp: SFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L + R_fp;
- end;
-
- -- A.3.12. SFix := integer + SFix
- function "+" (L: integer; R: SFix) return SFix is
- begin
- return R + L;
- end;
-
-
- ----------------------------------------
- -- A.4. Binary "-" subtraction operator
- ----------------------------------------
- --
- -- NOTE: There is a special problem with subtraction
- -- operators that return a UFix result if that result
- -- goes negative. Our arbitrary decision is that we
- -- truncate most-significant bits in this case. If you
- -- wish to avoid the risk of this arbitrarily-defined
- -- truncation behaviour, change one or more of your
- -- operands to SFix and get a SFix result using this
- -- idiom:
- -- SFix := UFix + (-UFix)
- -- or copy one of the UFix operands into a SFix that's
- -- one bit wider, before performing the operation.
- --
- -- Subtractions returning a UFix result take unsigned
- -- operands and do not exhibit bit growth.
- -- Subtractions returning a SFix result take signed or
- -- unsigned operands and exhibit one-bit growth like addition.
-
- -- A.4.1. UFix := UFix - UFix
- function "-" (L: UFix; R: UFix) return UFix is
- variable F, LW, RW: UFix(Max(L'LEFT, R'LEFT) downto
- Min(L'RIGHT, R'RIGHT));
- begin
- LW := (others => '0');
- RW := (others => '0');
- LW(L'RANGE) := L;
- RW(R'RANGE) := R;
- F := UFix(unsigned(LW) - unsigned(RW));
- return F;
- end;
-
- -- A.4.2. UFix := UFix - unsigned
- function "-" (L: UFix; R: unsigned) return UFix is
- begin
- return L - to_UFix(R);
- end;
-
- -- A.4.3. UFix := unsigned - UFix
- function "-" (L: unsigned; R: UFix) return UFix is
- begin
- return to_UFix(L) - R;
- end;
-
- -- A.4.4. UFix := UFix - integer
- function "-" (L: UFix; R: natural) return UFix is
- variable R_fp: UFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L - R_fp;
- end;
-
- -- A.4.5. UFix := natural - UFix
- function "-" (L: natural; R: UFix) return UFix is
- variable L_fp: UFix(R'RANGE);
- begin
- Copy_V(L_fp, L);
- return L_fp - R;
- end;
-
- -- A.4.6. SFix := SFix - SFix
- function "-" (L: SFix; R: SFix) return SFix is
- begin
- return L + (-R);
- end;
-
- -- A.4.7. SFix := SFix - UFix
- function "-" (L: SFix; R: UFix) return SFix is
- begin
- return L + (-R);
- end;
-
- -- A.4.8. SFix := UFix - SFix
- function "-" (L: UFix; R: SFix) return SFix is
- begin
- return To_SFix(L) - R;
- end;
-
- -- A.4.9. SFix := SFix - signed
- function "-" (L: SFix; R: signed) return SFix is
- begin
- return L - to_SFix(R);
- end;
-
- -- A.4.10. SFix := signed - SFix
- function "-" (L: signed; R: SFix) return SFix is
- begin
- return to_SFix(L) - R;
- end;
-
- -- A.4.11. SFix := SFix - integer
- function "-" (L: SFix; R: integer) return SFix is
- variable R_fp: SFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L - R_fp;
- end;
-
- -- A.4.12. SFix := integer - SFix
- function "-" (L: integer; R: SFix) return SFix is
- variable L_fp: SFix(R'RANGE);
- begin
- Copy_V(L_fp, L);
- return L_fp - R;
- end;
-
-
- -------------------------------------------
- -- A.5. Binary "*" multiplication operator
- -------------------------------------------
-
- -- A.5.1. UFix := UFix * UFix
- function "*" (L: UFix; R: UFix) return UFix is
- variable F: UFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
- begin
- F := UFix(unsigned(L) * unsigned(R));
- return F;
- end;
-
- -- A.5.2. UFix := UFix * unsigned
- function "*" (L: UFix; R: unsigned) return UFix is
- begin
- return L * to_UFix(R);
- end;
-
- -- A.5.3. UFix := unsigned * UFix
- function "*" (L: unsigned; R: UFix) return UFix is
- begin
- return to_UFix(L) * R;
- end;
-
- -- A.5.4. UFix := UFix * natural
- function "*" (L: UFix; R: natural) return UFix is
- variable R_fp: UFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L * R_fp;
- end;
-
- -- A.5.5. UFix := natural * UFix
- function "*" (L: natural; R: UFix) return UFix is
- begin
- return R * L;
- end;
-
- -- A.5.6. SFix := SFix * SFix
- function "*" (L: SFix; R: SFix) return SFix is
- variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
- begin
- F := SFix(signed(L) * signed(R));
- return F;
- end;
-
- -- A.5.7. SFix := SFix * UFix
- function "*" (L: SFix; R: UFix) return SFix is
- constant RS: SFix := SFix('0' & R);
- variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
- variable FW: SFix(F'LEFT+1 downto F'RIGHT);
- begin
- FW := SFix(signed(L) * signed(RS));
- Copy_V(F, FW); -- never overflows
- return F;
- end;
-
- -- A.5.8. SFix := UFix * SFix
- function "*" (L: UFix; R: SFix) return SFix is
- begin
- return R * L;
- end;
-
- -- A.5.9. SFix := SFix * signed
- function "*" (L: SFix; R: signed) return SFix is
- begin
- return L * to_SFix(R);
- end;
-
- -- A.5.10. SFix := signed * SFix
- function "*" (L: signed; R: SFix) return SFix is
- begin
- return to_SFix(L) * R;
- end;
-
- -- A.5.11. SFix := SFix * integer
- function "*" (L: SFix; R: integer) return SFix is
- variable R_fp: SFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L * R_fp;
- end;
-
- -- A.5.12. SFix := integer * SFix
- function "*" (L: integer; R: SFix) return SFix is
- begin
- return R * L;
- end;
-
-
- ------------------------------------------------------------------
- -- R. Relational operators - arithmetic comparisons involving
- -- UFix, SFix and other numeric types.
- -- The operators are overloaded for most of the sensible
- -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
- -- Note that in all cases comparisons are exact; if one
- -- operand has more fraction bits than the other, the less
- -- precise operand will have its LSBs zero-extended, and
- -- these zero bits will take part in comparison with whatever
- -- LSBs exist in the more precise operand.
- --
- -- Our implementation is based on only two operators, "=" and "<".
- -- All other operators are derived from these two, either by
- -- logical inversion of the result or by swapping operands.
- ------------------------------------------------------------------
-
- -------------------------------------
- -- R.1. Binary "=" equality operator
- -------------------------------------
-
- -- R.1.1. UFix = UFix
- function "=" (L: UFix; R: UFix) return boolean is
- variable LW, RW: UFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT));
- begin
- LW := (others => '0');
- RW := (others => '0');
- LW(L'RANGE) := L;
- RW(R'RANGE) := R;
- return unsigned(LW) = unsigned(RW);
- end;
-
- -- R.1.2. UFix = unsigned
- function "=" (L: UFix; R: unsigned) return boolean is
- begin
- return L = to_UFix(R);
- end;
-
- -- R.1.3. unsigned = UFix
- function "=" (L: unsigned; R: UFix) return boolean is
- begin
- return to_UFix(L) = R;
- end;
-
- -- R.1.4. UFix = integer
- function "=" (L: UFix; R: integer) return boolean is
- variable RS: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(RS, R, clip_MS, clip_LS);
- return To_SFix(L) = RS;
- end;
-
- -- R.1.5. integer = UFix
- function "=" (L: integer; R: UFix) return boolean is
- begin
- return R = L;
- end;
-
- -- R.1.6. SFix = SFix
- function "=" (L: SFix; R: SFix) return boolean is
- variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT));
- begin
- -- clip modes are OK because we aren't losing any bits
- Copy_V(LW, L, clip_MS, clip_LS);
- Copy_V(RW, R, clip_MS, clip_LS);
- return signed(LW) = signed(RW);
- end;
-
- -- R.1.7. SFix = UFix
- function "=" (L: SFix; R: UFix) return boolean is
- begin
- return L = To_SFix(R);
- end;
-
- -- R.1.8. UFix = SFix
- function "=" (L: UFix; R: SFix) return boolean is
- begin
- return R = L;
- end;
-
- -- R.1.9. SFix = signed
- function "=" (L: SFix; R: signed) return boolean is
- begin
- return L = to_SFix(R);
- end;
-
- -- R.1.10. signed = SFix
- function "=" (L: signed; R: SFix) return boolean is
- begin
- return to_SFix(L) = R;
- end;
-
- -- R.1.11. SFix = integer
- function "=" (L: SFix; R: integer) return boolean is
- variable RS: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(RS, R, clip_MS, clip_LS);
- return L = RS;
- end;
-
- -- R.1.12. integer = SFix
- function "=" (L: integer; R: SFix) return boolean is
- begin
- return R = L;
- end;
-
-
- --------------------------------------
- -- R.2. Binary "<" less-than operator
- --------------------------------------
-
- -- R.2.1. UFix < UFix
- function "<" (L: UFix; R: UFix) return boolean is
- variable LW, RW: unsigned(Max(L'LEFT, R'LEFT) downto
- Min(L'RIGHT, R'RIGHT));
- begin
- LW := (others => '0');
- RW := (others => '0');
- LW(L'RANGE) := unsigned(L);
- RW(R'RANGE) := unsigned(R);
- return unsigned(LW) < unsigned(RW);
- end;
-
- -- R.2.2. UFix < unsigned
- function "<" (L: UFix; R: unsigned) return boolean is
- begin
- return L < To_UFix(R);
- end;
-
- -- R.2.3. unsigned < UFix
- function "<" (L: unsigned; R: UFix) return boolean is
- begin
- return To_UFix(L) < R;
- end;
-
- -- R.2.4. UFix < integer
- function "<" (L: UFix; R: integer) return boolean is
- variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(S, R, clip_MS, clip_LS);
- return L < S;
- end;
-
- -- R.2.5. integer < UFix
- function "<" (L: integer; R: UFix) return boolean is
- variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(S, L, clip_MS, clip_LS);
- return S < R;
- end;
-
- -- R.2.6. SFix < SFix
- function "<" (L: SFix; R: SFix) return boolean is
- variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto
- Min(L'RIGHT, R'RIGHT));
- begin
- Copy_V(LW, L, clip_MS, clip_LS);
- Copy_V(RW, R, clip_MS, clip_LS);
- return signed(LW) < signed(RW);
- end;
-
- -- R.2.7. SFix < UFix
- function "<" (L: SFix; R: UFix) return boolean is
- begin
- return L < To_SFix(R);
- end;
-
- -- R.2.8. UFix < SFix
- function "<" (L: UFix; R: SFix) return boolean is
- begin
- return To_SFix(L) < R;
- end;
-
- -- R.2.9. SFix < signed
- function "<" (L: SFix; R: signed) return boolean is
- begin
- return L < To_SFix(R);
- end;
-
- -- R.2.10. signed < SFix
- function "<" (L: signed; R: SFix) return boolean is
- begin
- return To_SFix(L) < R;
- end;
-
- -- R.2.11. SFix < integer
- function "<" (L: SFix; R: integer) return boolean is
- variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(S, R, clip_MS, clip_LS);
- return L < S;
- end;
-
- -- R.2.12. integer < SFix
- function "<" (L: integer; R: SFix) return boolean is
- variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(S, L, clip_MS, clip_LS);
- return S < R;
- end;
-
-
- ----------------------------------------
- -- R.3. Binary "/=" inequality operator
- ----------------------------------------
-
- -- R.3.1. UFix /= UFix
- function "/=" (L: UFix; R: UFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.2. UFix /= unsigned
- function "/=" (L: UFix; R: unsigned) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.3. unsigned /= UFix
- function "/=" (L: unsigned; R: UFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.4. UFix /= integer
- function "/=" (L: UFix; R: integer) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.5. integer /= UFix
- function "/=" (L: integer; R: UFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.6. SFix /= SFix
- function "/=" (L: SFix; R: SFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.7. SFix /= UFix
- function "/=" (L: SFix; R: UFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.8. UFix /= SFix
- function "/=" (L: UFix; R: SFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.9. SFix /= signed
- function "/=" (L: SFix; R: signed) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.10. signed /= SFix
- function "/=" (L: signed; R: SFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.11. SFix /= integer
- function "/=" (L: SFix; R: integer) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.12. integer /= SFix
- function "/=" (L: integer; R: SFix) return boolean is
- begin
- return not (L = R);
- end;
-
-
- -----------------------------------------
- -- R.4. Binary ">" greater-than operator
- -----------------------------------------
-
- -- R.4.1. UFix > UFix
- function ">" (L: UFix; R: UFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.2. UFix > unsigned
- function ">" (L: UFix; R: unsigned) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.3. unsigned > UFix
- function ">" (L: unsigned; R: UFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.4. UFix > integer
- function ">" (L: UFix; R: integer) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.5. integer > UFix
- function ">" (L: integer; R: UFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.6. SFix > SFix
- function ">" (L: SFix; R: SFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.7. SFix > UFix
- function ">" (L: SFix; R: UFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.8. UFix > SFix
- function ">" (L: UFix; R: SFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.9. SFix > signed
- function ">" (L: SFix; R: signed) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.10. signed > SFix
- function ">" (L: signed; R: SFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.11. SFix > integer
- function ">" (L: SFix; R: integer) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.12. integer > SFix
- function ">" (L: integer; R: SFix) return boolean is
- begin
- return R < L;
- end;
-
-
- ----------------------------------------------
- -- R.5. Binary ">=" greater-or-equal operator
- ----------------------------------------------
-
- -- R.5.1. UFix >= UFix
- function ">=" (L: UFix; R: UFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.2. UFix >= unsigned
- function ">=" (L: UFix; R: unsigned) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.3. unsigned >= UFix
- function ">=" (L: unsigned; R: UFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.4. UFix >= integer
- function ">=" (L: UFix; R: integer) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.5. integer >= UFix
- function ">=" (L: integer; R: UFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.6. SFix >= SFix
- function ">=" (L: SFix; R: SFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.7. SFix >= UFix
- function ">=" (L: SFix; R: UFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.8. UFix >= SFix
- function ">=" (L: UFix; R: SFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.9. SFix >= signed
- function ">=" (L: SFix; R: signed) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.10. signed >= SFix
- function ">=" (L: signed; R: SFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.11. SFix >= integer
- function ">=" (L: SFix; R: integer) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.12. integer >= SFix
- function ">=" (L: integer; R: SFix) return boolean is
- begin
- return not (L < R);
- end;
-
-
- -------------------------------------------
- -- R.6. Binary "<=" less-or-equal operator
- -------------------------------------------
-
- -- R.6.1. UFix <= UFix
- function "<=" (L: UFix; R: UFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.2. UFix <= unsigned
- function "<=" (L: UFix; R: unsigned) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.3. unsigned <= UFix
- function "<=" (L: unsigned; R: UFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.4. UFix <= integer
- function "<=" (L: UFix; R: integer) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.5. integer <= UFix
- function "<=" (L: integer; R: UFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.6. SFix <= SFix
- function "<=" (L: SFix; R: SFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.7. SFix <= UFix
- function "<=" (L: SFix; R: UFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.8. UFix <= SFix
- function "<=" (L: UFix; R: SFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.9. SFix <= signed
- function "<=" (L: SFix; R: signed) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.10. signed <= SFix
- function "<=" (L: signed; R: SFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.11. SFix <= integer
- function "<=" (L: SFix; R: integer) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.12. integer <= SFix
- function "<=" (L: integer; R: SFix) return boolean is
- begin
- return not (R < L);
- end;
-
- ------------------------------------------------------------------
- -- C. Concatenation operators between fixed-point operands, and
- -- between fixed-point operands and other reasonable types.
- -- Unlike the implicitly defined "&" operator, they preserve
- -- place value and return an appropriately aligned subtype.
- -- Preservation of place value means that some concatenation
- -- operations are illegal. In particular, operations
- -- [SFix & SFix] and [UFix & SFix] are illegal, and
- -- the place values of operands in [SFix & UFix] and
- -- [UFix & UFix] must match up - the rightmost subscript of
- -- the left operand must be one higher than the leftmost
- -- subscript of the right operand.
- -- Single bits of type std_ulogic may be concatenated with
- -- fixed-point types where there is no risk of losing
- -- sign-extension information.
- -- Because of the way VHDL defines implicit concatenation,
- -- it is impossible to detect all these errors at compile time.
- -- Instead they are detected by assertion statements at run time.
- -- Tool vendors may choose to implement compile-time checks
- -- so that the run-time checking overhead can be avoided.
- ------------------------------------------------------------------
-
- -- C.1.1. UFix := UFix & UFix
- function "&" (L: UFix; R: UFix) return UFix is
- begin
- return UFix(concat(std_logic_vector(L), std_logic_vector(R)));
- end;
-
- -- C.1.2. UFix := UFix & std_ulogic
- function "&" (L: UFix; R: std_ulogic) return UFix is
- begin
- return UFix(concat(std_logic_vector(L), R));
- end;
-
- -- C.1.3. UFix := std_ulogic & UFix
- function "&" (L: std_ulogic; R: UFix) return UFix is
- begin
- return UFix(concat(L, std_logic_vector(R)));
- end;
-
-
- -- C.2.1. SFix := SFix & UFix
- function "&" (L: SFix; R: UFix) return SFix is
- begin
- return SFix(concat(std_logic_vector(L), std_logic_vector(R)));
- end;
-
- -- C.2.2. SFix := SFix & SFix -- ILLEGAL
- function "&" (L: SFix; R: SFix) return SFix is
- begin
- report concat_signLS_msg
- severity concat_severity;
- return SFix(concat(std_logic_vector(L), std_logic_vector(R)));
- end;
-
- -- C.2.3. SFix := SFix & std_ulogic
- function "&" (L: SFix; R: std_ulogic) return SFix is
- begin
- return SFix(concat(std_logic_vector(L), R));
- end;
-
- -- C.2.4. SFix := std_ulogic & SFix
- function "&" (L: std_ulogic; R: SFix) return SFix is
- begin
- assert std_match(L, R(R'LEFT))
- report concat_sxt_msg
- severity concat_severity;
- return SFix(concat(L, std_logic_vector(R)));
- end;
-
-
-end; -- package body fix_std;
diff --git a/lib/fixed/fixed_util_pkg.vhd b/lib/fixed/fixed_util_pkg.vhd
deleted file mode 100644
index 584f186..0000000
--- a/lib/fixed/fixed_util_pkg.vhd
+++ /dev/null
@@ -1,159 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-package fixed_util_pkg is
-
- -------------------------------------------------------------
- -- Frequently used constants
- constant pi : real := 3.141592653589793e+000;
- constant sqrt2 : real := 1.414213562373095e+000;
- constant sqrt2_inv : real := 7.071067811865475e-001;
-
- -- Constructor helpers
- -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
- function uproto (nbits : integer; nbits_frac : integer) return ufixed;
-
- -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
- function sproto (nbits : integer; nbits_frac : integer) return sfixed;
-
- -- Safe variant of uproto
- function uhi (nbits : integer; nbits_frac : integer) return integer;
- function ulo (nbits : integer; nbits_frac : integer) return integer;
-
- -- Safe variant of sproto
- function shi (nbits : integer; nbits_frac : integer) return integer;
- function slo (nbits : integer; nbits_frac : integer) return integer;
-
- function to_unsigned (src : ufixed) return UNSIGNED;
- function to_signed (src : sfixed) return SIGNED;
-
- type real_array_t is array (natural range <>) of real;
- type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
- type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
-
- function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t;
- function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t;
-
- -- Slicing functions for unconstrained array types
- function to_ufixed(src : ufixed_array_t; index : integer) return ufixed;
- function to_sfixed(src : sfixed_array_t; index : integer) return sfixed;
-
--------------------------------------------------------------------------------
-end; -- package fixed_util_pkg;
-
-package body fixed_util_pkg is
-
- -------------------------------------------------------------
- -- Constuctor helpers
- function uproto (nbits : integer; nbits_frac : integer) return ufixed is
- constant result : ufixed (uhi(nbits,nbits_frac) downto ulo(nbits,nbits_frac)) := (others => '0');
- begin
- return result(uhi(nbits,nbits_frac) downto ulo(nbits,nbits_frac));
- end uproto;
-
- -------------------------------------------------------------
- function sproto (nbits : integer; nbits_frac : integer) return sfixed is
- constant result : sfixed (shi(nbits,nbits_frac) downto slo(nbits,nbits_frac)) := (others => '0');
- begin
- return result(shi(nbits,nbits_frac) downto slo(nbits,nbits_frac));
- end sproto;
-
- -------------------------------------------------------------
- function uhi (nbits : integer; nbits_frac : integer) return integer is
- begin
- return nbits-nbits_frac-1;
- end uhi;
-
- -------------------------------------------------------------
- function ulo (nbits : integer; nbits_frac : integer) return integer is
- begin
- return -nbits_frac;
- end ulo;
-
- -------------------------------------------------------------
- function shi (nbits : integer; nbits_frac : integer) return integer is
- begin
- return nbits-nbits_frac;
- end shi;
-
- -------------------------------------------------------------
- function slo (nbits : integer; nbits_frac : integer) return integer is
- begin
- return -nbits_frac+1;
- end slo;
-
- -------------------------------------------------------------
- function to_unsigned (src : ufixed) return UNSIGNED is
- subtype t is UNSIGNED(src'high - src'low downto 0);
- variable slv : t;
- begin
- slv := t(src);
- return UNSIGNED(to_X01(std_logic_vector(slv)));
-
- end function to_unsigned;
-
- -------------------------------------------------------------
- function to_signed (src : sfixed) return SIGNED is
- subtype t is SIGNED(src'high - src'low downto 0);
- variable slv : t;
- begin
- slv := t(src);
- return SIGNED(to_X01(std_logic_vector(slv)));
-
- end function to_signed;
-
- function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is
- variable res : sfixed_array_t(0 to x'length-1, proto'range);
- variable tt : sfixed(proto'range);
- begin
- for i in x'range loop
- tt := to_sfixed(x(i), proto);
- for j in proto'range loop
- res(i,j) := tt(j);
- end loop;
- end loop;
- return res;
- end to_sfixed_array;
-
- ---------------------------------------------------------------------------
- function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t is
- variable p : sfixed(shi(nbits, nbits_int) downto slo(nbits, nbits_int));
- begin
- return to_sfixed_array(x, p);
- end to_sfixed_array;
-
- -------------------------------------------------------------------------------
- -- ufixed <= ufixed_array(i)
- function to_ufixed(src : ufixed_array_t; index : integer) return ufixed is
- variable dst : ufixed(src'range(2));
- begin
- for j in src'range(2) loop
- dst(j) := src(index, j);
- end loop;
-
- return dst;
-
- end to_ufixed;
-
- -------------------------------------------------------------------------------
- -- sfixed <= sfixed_array(i)
- function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is
- variable dst : sfixed(src'range(2));
- begin
- for j in src'range(2) loop
- dst(j) := src(index, j);
- end loop;
-
- return dst;
-
- end to_sfixed;
-
--------------------------------------------------------------------------------
-end; -- package fixed_util_pkg;
diff --git a/lib/fixed_ja/fixed_ja.vhd b/lib/fixed_ja/fixed_ja.vhd
deleted file mode 100644
index bcd2700..0000000
--- a/lib/fixed_ja/fixed_ja.vhd
+++ /dev/null
@@ -1,322 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-package fixed_ja is
-
-
- type ufixed_t is array (integer range <>) of STD_LOGIC;
- type sfixed_t is array (integer range <>) of STD_LOGIC;
- type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
- type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
-
- type round_mode_t is (none, round_to_zero, round_pos_infinity, round_neg_infinity, round_half_up, round_half_down, round_nearest, round_convergent);
- type saturate_mode_t is (none, saturate);
-
- -- Declare functions and procedure
-
- constant ASSERT_NO_WARN : boolean := false;
- constant default_round_mode : round_mode_t := none;
- constant default_saturate_mode : saturate_mode_t := none;
-
- -- null array constants
- constant NAUF : ufixed_t (0 downto 1) := (others => '0');
- constant NASF : sfixed_t (0 downto 1) := (others => '0');
- constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
-
- -- Constructor helpers
- -- Use: variable v8u2 : ufixed_t(ufixed(8,2)'range);
- function uproto (nbits : integer; nbits_int : integer) return ufixed_t;
-
- -- Use: variable v8s2 : sfixed_t(sfixed(8,2)'range);
- function sproto (nbits : integer; nbits_int : integer) return sfixed_t;
-
- function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t;
- function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t;
-
- -- Conversion Functions
- function to_ufixed(src : ufixed_t) return ufixed_t;
- function to_sfixed(src : sfixed_t) return sfixed_t;
- function to_ufixed(src : sfixed_t) return ufixed_t;
- function to_sfixed(src : ufixed_t) return sfixed_t;
-
- function to_ufixed
- (
- src : ufixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t;
-
- function to_ufixed
- (
- src : ufixed_t;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t;
-
- function to_sfixed
- (
- src : sfixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t;
-
- function to_sfixed
- (
- src : sfixed_t;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t;
-
- -- fixed <= integer
- function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t;
- function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t;
-
- -- fixed <= integer
- function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t;
- function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t;
-
- -- ufixed <= unsigned
- function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t;
- function to_ufixed (src : unsigned; proto : ufixed_t) return ufixed_t;
-
- -- sfixed <= signed
- function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t;
- function to_sfixed (src : signed; proto : sfixed_t) return sfixed_t;
-
- -- fixed <= slv
- function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t;
- function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t;
- function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t;
- function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t;
-
- -- ufixed <= real
- function to_ufixed
- (
- src : real;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t;
-
- function to_ufixed
- (
- src : real;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t;
-
- -- sfixed <= real
- function to_sfixed
- (
- src : real;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t;
-
- function to_sfixed
- (
- src : real;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t;
-
- -- Slicing functions for unconstrained array types
- function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t;
- function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t;
-
- -- ufixed <= string
- function to_ufixed (src : string) return ufixed_t;
-
- -- sfixed <= string
- function to_sfixed (src : string) return sfixed_t;
-
- -- real <= ufixed
- function to_real(src : ufixed_t) return real;
-
- -- real <= sfixed
- function to_real(src : sfixed_t) return real;
-
- -- slv <= ufixed
- function to_slv(src : ufixed_t) return std_logic_vector;
-
- -- slv <= sfixed
- function to_slv(src : sfixed_t) return std_logic_vector;
-
- -- UNSIGNED <= ufixed
- function to_unsigned (src : ufixed_t) return UNSIGNED;
-
- -- SIGNED <= sfixed
- function to_signed (src : sfixed_t) return SIGNED;
-
- -- integer <= ufixed
- function to_integer (src : ufixed_t) return integer;
-
- -- integer <= sfixed
- function to_integer (src : sfixed_t) return integer;
-
- function to_string(src : ufixed_t) return string;
- function to_string(src : sfixed_t) return string;
- function to_string(src : std_logic_vector) return string;
-
- -------------------------------------------------------------
- -- Arithmetic shift left
- -------------------------------------------------------------
- function "sla" (src : ufixed_t; count : integer) return ufixed_t;
- function "sla" (src : sfixed_t; count : integer) return sfixed_t;
-
- -------------------------------------------------------------
- -- Arithmetic shift right
- -------------------------------------------------------------
- function "sra" (src : ufixed_t; count : integer) return ufixed_t;
- function "sra" (src : sfixed_t; count : integer) return sfixed_t;
-
- -------------------------------------------------------------
- -- Multiplication
- -------------------------------------------------------------
- function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t;
- function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t;
- function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t;
- function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t;
-
- -------------------------------------------------------------
- -- Sum
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : integer) return ufixed_t;
- function "+" (a : sfixed_t; b : integer) return sfixed_t;
- function "+" (a : ufixed_t; b : unsigned) return ufixed_t;
- function "+" (a : sfixed_t; b : signed) return sfixed_t;
- function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t;
- function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t;
- function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t;
- function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t;
- function "+" (a : ufixed_t; b : std_logic) return ufixed_t;
- function "+" (a : sfixed_t; b : std_logic) return sfixed_t;
-
-
- -------------------------------------------------------------
- -- Difference
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : integer) return ufixed_t;
- function "-" (a : sfixed_t; b : integer) return sfixed_t;
- function "-" (a : ufixed_t; b : unsigned) return ufixed_t;
- function "-" (a : sfixed_t; b : signed) return sfixed_t;
- function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t;
- function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t;
- function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t;
- function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t;
- function "-" (a : ufixed_t; b : std_logic) return ufixed_t;
- function "-" (a : sfixed_t; b : std_logic) return sfixed_t;
-
- -------------------------------------------------------------
- -- Equality
- -------------------------------------------------------------
- function "=" (a : ufixed_t; b : ufixed_t) return boolean;
- function "=" (a : sfixed_t; b : sfixed_t) return boolean;
- function "=" (a : ufixed_t; b : sfixed_t) return boolean;
- function "=" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Inequality
- -------------------------------------------------------------
- function "/=" (a : ufixed_t; b : ufixed_t) return boolean;
- function "/=" (a : sfixed_t; b : sfixed_t) return boolean;
- function "/=" (a : ufixed_t; b : sfixed_t) return boolean;
- function "/=" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Less than
- -------------------------------------------------------------
- function "<" (a : ufixed_t; b : ufixed_t) return boolean;
- function "<" (a : sfixed_t; b : sfixed_t) return boolean;
- function "<" (a : ufixed_t; b : sfixed_t) return boolean;
- function "<" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Greater than
- -------------------------------------------------------------
- function ">" (a : ufixed_t; b : ufixed_t) return boolean;
- function ">" (a : sfixed_t; b : sfixed_t) return boolean;
- function ">" (a : ufixed_t; b : sfixed_t) return boolean;
- function ">" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Less or equal than
- -------------------------------------------------------------
- function "<=" (a : ufixed_t; b : ufixed_t) return boolean;
- function "<=" (a : sfixed_t; b : sfixed_t) return boolean;
- function "<=" (a : ufixed_t; b : sfixed_t) return boolean;
- function "<=" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Greater or equal than
- -------------------------------------------------------------
- function ">=" (a : ufixed_t; b : ufixed_t) return boolean;
- function ">=" (a : sfixed_t; b : sfixed_t) return boolean;
- function ">=" (a : ufixed_t; b : sfixed_t) return boolean;
- function ">=" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Unary Arithmetic Operators
- -------------------------------------------------------------
- function "abs" (src : sfixed_t) return sfixed_t;
- function "-" (src : ufixed_t) return sfixed_t;
- function "-" (src : sfixed_t) return sfixed_t;
-
- -------------------------------------------------------------
- -- Misc. Operators
- -------------------------------------------------------------
- function ipart (src : ufixed_t) return ufixed_t;
- function fpart (src : ufixed_t) return ufixed_t;
- function ipart (src : sfixed_t) return sfixed_t;
- function fpart (src : sfixed_t) return sfixed_t;
-
- -------------------------------------------------------------
- -- Print function
- -------------------------------------------------------------
- procedure print_info(src : in ufixed_t; prefix : in string);
- procedure print_info(src : in sfixed_t; prefix : in string);
- procedure print_info(src : in string; prefix : in string);
-
- -------------------------------------------------------------
- -- Helpers
- -------------------------------------------------------------
- function cmsb(src : ufixed_t) return integer;
- function clsb(src : ufixed_t) return integer;
-
- function MIN (X, Y: INTEGER) return INTEGER;
- function MAX (X, Y: INTEGER) return INTEGER;
-
- function "MOD" (X, Y: in REAL ) return REAL;
- function ipart(src : real) return real;
- function fpart(src : real) return real;
-
- function and_red(arg : ufixed_t) return STD_ULOGIC;
- function nand_red(arg : ufixed_t) return STD_ULOGIC;
- function or_red(arg : ufixed_t) return STD_ULOGIC;
- function nor_red(arg : ufixed_t) return STD_ULOGIC;
- function xor_red(arg : ufixed_t) return STD_ULOGIC;
- function xnor_red(arg : ufixed_t) return STD_ULOGIC;
- function and_red(arg : sfixed_t) return STD_ULOGIC;
- function nand_red(arg : sfixed_t) return STD_ULOGIC;
- function or_red(arg : sfixed_t) return STD_ULOGIC;
- function nor_red(arg : sfixed_t) return STD_ULOGIC;
- function xor_red(arg : sfixed_t) return STD_ULOGIC;
- function xnor_red(arg : sfixed_t) return STD_ULOGIC;
-
- --------------------------------------------------------------
-
-end; -- package fixed_ja;
-
diff --git a/lib/fixed_ja/fixed_ja_body.vhd b/lib/fixed_ja/fixed_ja_body.vhd
deleted file mode 100644
index a85b626..0000000
--- a/lib/fixed_ja/fixed_ja_body.vhd
+++ /dev/null
@@ -1,1921 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use ieee.math_real.all;
-use std.textio.all;
-
-package body fixed_ja is
-
- -------------------------------------------------------------
- -- Local Procedures
- -------------------------------------------------------------
- -- adds 1 to the LSB of the number
- procedure round_up
- (
- src : in ufixed_t;
- result : out ufixed_t;
- overflowx : out BOOLEAN ) is
-
- variable srcuns, resuns : UNSIGNED (src'high-src'low+1 downto 0) := (others => '0');
- begin -- round_up
- srcuns (srcuns'high-1 downto 0) := to_unsigned (src);
- resuns := srcuns + 1;
-
- result := to_ufixed(resuns(src'high-src'low downto 0), src);
- overflowx := (resuns(resuns'high) = '1');
-
- end procedure round_up;
-
- -------------------------------------------------------------
- -- adds 1 to the LSB of the number
- procedure round_up
- (
- src : in sfixed_t;
- result : out sfixed_t;
- overflowx : out BOOLEAN ) is
-
- variable srcs, ress : SIGNED (src'high-src'low+1 downto 0);
- begin -- round_up
- srcs (srcs'high-1 downto 0) := to_signed (src);
- srcs(srcs'high) := src(src'high); -- sign extend
- ress := srcs + 1;
-
- result := to_sfixed(ress (ress'high-1 downto 0), src);
- overflowx := ((src(src'high) /= ress(ress'high-1)) and (or_red (sfixed_t(ress)) /= '0'));
-
- end procedure round_up;
-
- -------------------------------------------------------------
- -- Local functions
- -------------------------------------------------------------
- -- round_fixed()
--- function round_fixed
--- (
--- src : ufixed_t;
--- remainder : ufixed_t;
--- rnd_mode : round_mode_t := default_round_mode
--- ) return ufixed_t is
--- variable res : ufixed_t(src'range);
--- begin
--- return res;
---
--- end round_fixed;
-
- -------------------------------------------------------------
--- function round_fixed
--- (
--- src : sfixed_t;
--- remainder : sfixed_t;
--- rnd_mode : round_mode_t := default_round_mode
--- ) return sfixed_t is
--- variable res : signed(src'length-1 downto 0);
--- begin
--- return src;
---
--- end round_fixed;
-
- -------------------------------------------------------------
- function reshape
- (
- src : ufixed_t;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
-
- variable RemainLow : ufixed_t (proto'low-1 downto src'low) := (others => '0');
- variable RemainHigh : ufixed_t (src'high downto proto'high+1) := (others => '0');
- variable dst, tmp : ufixed_t (proto'high downto proto'low) := (others => '0');
- variable ovf, isTruncLo, isTruncHi : boolean := false;
- begin
-
- if proto'high < -1 then
- assert false report "U: reshape: Bad dual point (Upper bound < (-1))" severity error;
- end if;
-
- -- Check for high and low truncation
- isTruncLo := (src'low < dst'low);
- isTruncHi := (src'high > dst'high);
-
- -- Reshape
- dst := (others => '0');
- dst(min(src'high, dst'high) downto max(src'low, dst'low)) := src(min(src'high, dst'high) downto max(src'low, dst'low));
- tmp := dst;
-
- -- Get low remainder
- if isTruncLo then
- RemainLow := src(RemainLow'range);
- end if;
-
- -- Get high remainder
- if isTruncHi then
- RemainHigh := src(RemainHigh'range);
- end if;
-
- ovf := false;
-
- -- Rounding
- if isTruncLo then
-
- case rnd_mode is
-
- -- Round to positive infinity (round ceiling)
- when round_pos_infinity =>
- if or_red(RemainLow) = '1' then
- round_up(tmp, dst, ovf);
- end if;
-
- -- Round Half-up
- -- Round nearest
- when round_half_up | round_nearest =>
- if (RemainLow(RemainLow'high) = '1') then
- round_up(tmp, dst, ovf);
- end if;
-
- -- Round convergent
- when round_convergent =>
- if RemainLow(RemainLow'high) = '1' then
- if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then
- round_up(tmp, dst, ovf);
- elsif tmp(dst'low) = '1' then
- round_up(tmp, dst, ovf);
- end if;
- end if;
-
- -- Round to zero
- when round_to_zero | none => null;
-
- when others =>
- assert false report "Reshape(U): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error;
-
- end case;
- end if;
-
- -- Saturating
- if sat_mode = saturate then
-
- -- Check overflow
- if isTruncHi then
- ovf := ovf or or_red(RemainHigh) = '1';
- end if;
-
- -- Saturate
- if ovf then
- dst := (others => '1');
- end if;
-
- end if;
-
- return dst;
-
- end reshape;
-
- -------------------------------------------------------------
- function reshape
- (
- src : ufixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
-
- begin
- return reshape(src, uproto(nbits, nbits_int), rnd_mode, sat_mode);
-
- end reshape;
-
- -------------------------------------------------------------
- function reshape
- (
- src : sfixed_t;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
-
- variable RemainLow : sfixed_t (proto'low-1 downto src'low) := (others => '0');
- variable RemainHigh : sfixed_t (src'high-1 downto proto'high) := (others => '0');
- variable dst, tmp : sfixed_t (proto'high downto proto'low) := (others => '0');
- variable ovf, isTruncLo, isTruncHi : boolean := false;
- variable sign : std_logic;
- begin
-
- if proto'high < 0 then
- assert false report "Reshape(S): Bad dual point (Upper bound < (0))" severity error;
- end if;
-
- -- Check for high and low truncation
- isTruncLo := (src'low < dst'low);
- isTruncHi := (src'high > dst'high);
-
- -- Reshape
- sign := src(src'high);
- dst := (others => '0');
- dst(dst'high downto max(src'low, dst'low)) := (dst'high downto min(src'high, dst'high) => sign) & src(min(src'high, dst'high)-1 downto max(src'low, dst'low));
- tmp := dst;
-
- -- Get low remainder
- if isTruncLo then
- RemainLow := src(RemainLow'range);
- end if;
-
- -- Get high remainder
- if isTruncHi then
- RemainHigh := src(RemainHigh'range);
- end if;
-
- ovf := false;
-
- -- Rounding
- if isTruncLo then
-
- case rnd_mode is
-
- -- Round to positive infinity (round ceiling)
- when round_pos_infinity =>
- round_up(tmp, dst, ovf);
- if ovf then
- dst(dst'high) := '0';
- end if;
-
- -- Round Half-up
- when round_half_up =>
- if RemainLow(RemainLow'high) = '1' then
- round_up(tmp, dst, ovf);
- end if;
-
- -- Round nearest
- when round_nearest =>
- if RemainLow(RemainLow'high) = '1' then
- if RemainLow'length = 1 then
- if sign = '0' then
- round_up(tmp, dst, ovf);
- end if;
- elsif sign = '0' or (sign and or_red(RemainLow(RemainLow'high-1 downto RemainLow'low))) = '1' then
- round_up(tmp, dst, ovf);
- end if;
- end if;
-
- -- Round convergent
- when round_convergent =>
- if RemainLow(RemainLow'high) = '1' then
- if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then
- round_up(tmp, dst, ovf);
- elsif tmp(dst'low) = '1' then
- round_up(tmp, dst, ovf);
- end if;
- end if;
-
- -- Round to zero
- when round_to_zero =>
- if (or_red(RemainLow) = '1' and sign = '1') then
- round_up(tmp, dst, ovf);
- end if;
-
- -- No Round
- when none =>
- -- Same as RoundToZero but overflow detection is omitted
- dst := tmp + (or_red(RemainLow) and sign);
-
- when others =>
- assert false report "Reshape(S): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error;
-
- end case;
-
- -- Check negative zero
- if dst(dst'high) = '1' then
- if or_red(dst(dst'high-1 downto dst'low)) = '0' then
- dst(dst'high) := '0';
- -- assert false report "Reshape(S): -0 detected" severity note;
- end if;
- end if;
- end if;
-
- -- Saturating
- if sat_mode = saturate then
-
- -- Check overflow
- if isTruncHi then
- ovf := ovf or
- (sign = '1' and src(dst'high) = '0' and or_red(tmp(dst'high-1 downto dst'low)) = '1') or
- (sign = '1' and src(dst'high) = '1' and or_red(tmp(dst'high-1 downto dst'low)) = '0') or
- (sign = '0' and or_red(RemainHigh) = '1');
- end if;
-
- -- Saturate
- if ovf then
- if (sign = '1') then
- dst := '1' & (dst'high-1 downto dst'low+1 => '0') & '1';
- else
- dst := '0' & (dst'high-1 downto dst'low => '1');
- end if;
- end if;
-
- end if;
-
- return dst;
-
- end reshape;
-
- -------------------------------------------------------------
- function reshape
- (
- src : sfixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
-
- begin
- return reshape(src, sproto(nbits, nbits_int), rnd_mode, sat_mode);
-
- end reshape;
-
- -------------------------------------------------------------
- -- Constuctor helpers
- -------------------------------------------------------------
- function uproto (nbits : integer; nbits_int : integer) return ufixed_t is
- constant result : ufixed_t (nbits_int-1 downto nbits_int-nbits) := (others => '0');
- begin
- return result(nbits_int-1 downto nbits_int-nbits);
- end uproto;
-
- -------------------------------------------------------------
- function sproto (nbits : integer; nbits_int : integer) return sfixed_t is
- constant result : sfixed_t (nbits_int downto nbits_int-nbits+1) := (others => '0');
- begin
- return result(nbits_int downto nbits_int-nbits+1);
- end sproto;
-
- -------------------------------------------------------------
- function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t is
- constant result : ufixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0');
- variable hi, lo : integer := 0;
-
- begin
-
- case op is
- when '+' =>
- hi := max(a'high, b'high);
- if a'high = b'high then
- hi := hi + 1;
- end if;
- lo := min(a'low, b'low);
-
- when '-' =>
- hi := max(a'high, b'high);
- lo := min(a'low, b'low);
-
- when '*' =>
- hi := a'high + b'high + 1;
- if (a'high < 0 or b'high < 0) then
- if (hi > -1) then
- hi := hi-1;
- end if;
- end if;
- lo := hi - a'length - b'length + 1;
-
- when others => null;
-
- end case;
-
- return result(hi downto lo);
- end uproto;
-
- -------------------------------------------------------------
- function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t is
- constant result : sfixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0');
- variable hi, lo : integer := 0;
-
- begin
-
- case op is
- when '+' =>
- hi := max(a'high, b'high);
- if a'high = b'high then
- hi := hi + 1;
- end if;
- lo := min(a'low, b'low);
-
- when '-' =>
- hi := max(a'high, b'high);
- lo := min(a'low, b'low);
-
- when '*' =>
- hi := a'high + b'high;
- if (a'high = 0 or b'high = 0) then
- if (hi > 0) then
- hi := hi-1;
- end if;
- end if;
- lo := hi - a'length - b'length + 1;
-
- when others => null;
-
- end case;
-
- return result(hi downto lo);
- end sproto;
-
- -------------------------------------------------------------
- -- Type conversions
- -------------------------------------------------------------
- -- ufixed <= ufixed
- function to_ufixed(src : ufixed_t) return ufixed_t is
- begin
- return to_ufixed(src, src);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- ufixed <= sfixed
- function to_ufixed(src : sfixed_t) return ufixed_t is
- variable dst : ufixed_t(src'range) := (others => '0');
- begin
- dst := ufixed_t(abs(src));
- return dst(src'high-1 downto src'low);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= sfixed
- function to_sfixed(src : sfixed_t) return sfixed_t is
- begin
- return src;
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- sfixed <= ufixed
- function to_sfixed(src : ufixed_t) return sfixed_t is
- variable dst : sfixed_t(src'high+1 downto src'low) := (others => '0');
- begin
- dst(src'range) := sfixed_t(src);
- return dst;
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- ufixed <= ufixed
- function to_ufixed
- (
- src : ufixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
- begin
- return reshape(src, nbits, nbits_int, rnd_mode, sat_mode);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- ufixed <= ufixed
- function to_ufixed
- (
- src : ufixed_t;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
- begin
- return reshape(src, proto, rnd_mode, sat_mode);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= sfixed
- function to_sfixed
- (
- src : sfixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
- begin
- return reshape(src, nbits, nbits_int, rnd_mode, sat_mode);
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- sfixed <= sfixed
- function to_sfixed
- (
- src : sfixed_t;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
- begin
- return reshape(src, proto, rnd_mode, sat_mode);
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- ufixed <= integer
- function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t is
- begin
- return to_ufixed(src, uproto(nbits, nbits_int));
-
- end to_ufixed;
-
- function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t is
- begin
- return to_ufixed(to_unsigned(src, proto'length), proto);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- ufixed <= unsigned
- function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t is
- begin
- return to_ufixed(src, uproto(nbits, nbits_int));
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- ufixed <= unsigned
- function to_ufixed(src : unsigned; proto : ufixed_t) return ufixed_t is
- variable dst : ufixed_t(proto'high downto proto'low) := (others => '0');
- begin
-
- dst(dst'low + min(dst'length, src'length)-1 downto dst'low) := ufixed_t(src(min(dst'length, src'length)-1 downto 0));
-
- return dst;
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= integer
- function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t is
- begin
- return to_sfixed(src, sproto(nbits, nbits_int));
-
- end to_sfixed;
-
- function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t is
- begin
-
- return to_sfixed(to_signed(src, proto'length), proto);
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- sfixed <= signed
- function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t is
- begin
- return to_sfixed(src, sproto(nbits, nbits_int));
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- sfixed <= signed
- function to_sfixed(src : signed; proto : sfixed_t) return sfixed_t is
- variable dst : sfixed_t(proto'high downto proto'low) := (others => '0');
- begin
-
- dst(dst'low + min(dst'length, src'length)-2 downto dst'low) := sfixed_t(src(min(dst'length, src'length)-2 downto 0));
- dst(dst'high) := src(src'high);
-
- return dst;
-
- end to_sfixed;
-
- -------------------------------------------------------------
- function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t is
- variable result : ufixed_t (proto'left downto proto'right);
- begin
- if (result'length < 1) then
- return result;
- else
- result := to_ufixed (unsigned(src), proto);
- return result;
- end if;
-
- end function to_ufixed;
-
- -------------------------------------------------------------
- function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t is
- begin
- return to_ufixed(src, uproto(nbits, nbits_int));
-
- end function to_ufixed;
-
- -------------------------------------------------------------
- function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t is
- variable result : sfixed_t (proto'left downto proto'right);
- begin
- if (result'length < 1) then
- return result;
- else
- result := to_sfixed (signed(src), proto);
- return result;
- end if;
-
- end function to_sfixed;
-
- -------------------------------------------------------------
- function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t is
- begin
- return to_sfixed(src, sproto(nbits, nbits_int));
-
- end to_sfixed;
- -------------------------------------------------------------
-
- -- ufixed <= real
- function to_ufixed
- (
- src : real;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
-
- constant nbits_ext : integer := nbits + 1;
- constant fix_hi : integer := nbits_int - 1;
- constant fix_lo : integer := nbits_int - nbits_ext;
-
- variable dst : ufixed_t (fix_hi downto fix_lo) := (others => '0');
- variable i : integer := 0;
- variable remain : real := 0.0;
-
- begin
-
- if (nbits_int < 0) then
- assert false report "to_ufixed: Bad dual point (N integer bits < 0)" severity error;
- end if;
-
- if ((2.0**nbits_int - 1.0) < ipart(abs(src))) then
--- assert ASSERT_NO_WARN report "to_ufixed: Overflow (" & REAL'image(src) & ") " severity warning;
--- print_info(dst, "dst: ");
- end if;
-
- remain := abs(src);
- for i in dst'range loop
- if remain >= 2.0**i then
- dst(i) := '1';
- remain := remain - 2.0**i;
- else
- dst(i) := '0';
- end if;
- end loop;
-
- return to_ufixed(dst, nbits, nbits_int, rnd_mode, sat_mode);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= real
- function to_sfixed
- (
- src : real;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
-
- variable utmp : ufixed_t(proto'high-1 downto proto'low) := (others => '0');
- variable dst : sfixed_t(proto'high downto proto'low) := (others => '0');
-
- begin
- utmp := to_ufixed(src, utmp, rnd_mode, sat_mode);
- if (src < 0.0) then
- dst := -to_sfixed(utmp);
- else
- dst := to_sfixed(utmp);
- end if;
-
- return dst;
- end to_sfixed;
-
- -------------------------------------------------------------
- -- ufixed <= real
- function to_ufixed
- (
- src : real;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
- begin
- return to_ufixed(src, proto'length, proto'high+1, rnd_mode, sat_mode);
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= real
- function to_sfixed
- (
- src : real;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
- begin
- return to_sfixed(src, sproto(nbits, nbits_int), rnd_mode, sat_mode);
- end to_sfixed;
-
- -------------------------------------------------------------------------------
- -- ufixed <= ufixed_array(i)
- function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t is
- variable dst : ufixed_t(src'range(2));
- begin
- for j in src'range(2) loop
- dst(j) := src(index, j);
- end loop;
-
- return dst;
-
- end to_ufixed;
-
- -------------------------------------------------------------------------------
- -- sfixed <= sfixed_array(i)
- function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t is
- variable dst : sfixed_t(src'range(2));
- begin
- for j in src'range(2) loop
- dst(j) := src(index, j);
- end loop;
-
- return dst;
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- ufixed <= string
- function to_ufixed (src : string) return ufixed_t is
-
- variable i, j, nbits, nbits_int, nbits_frac : integer := 0;
- variable dst : unsigned(src'length downto 0) := (others => '0');
- variable dp_found : boolean := false;
- begin
-
- for i in src'reverse_range loop
- case src(i) is
- when '.' =>
- if dp_found then
- assert false report "More than one DP not found." severity error;
- else
- dp_found := true;
- nbits_frac := j;
- end if;
-
- when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1;
- when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1;
- when others =>
- assert false report "Illegal character in binary string." severity error;
-
- end case;
-
- end loop ;
- if not dp_found then
- assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning;
- end if;
-
- nbits_int := nbits - nbits_frac;
-
- return to_ufixed(dst(nbits-1 downto 0), nbits, nbits_int);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= string
- function to_sfixed (src : string) return sfixed_t is
-
- variable i, j, nbits, nbits_int, nbits_frac : integer := 0;
- variable dst : signed(src'length downto 0) := (others => '0');
- variable dp_found : boolean := false;
- variable is_neg : boolean := false;
- begin
-
- is_neg := src(src'left) = '-';
-
- for i in src'reverse_range loop
- case src(i) is
- when '-' => null;
- when '+' => null;
-
- when '.' =>
- if dp_found then
- assert false report "More than one DP not found." severity error;
- else
- dp_found := true;
- nbits_frac := j;
- end if;
-
- when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1;
- when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1;
- when others =>
- assert false report "Illegal character in binary string." severity error;
- end case;
- end loop ;
- nbits := nbits + 1;
-
- if not dp_found then
- assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning;
- end if;
-
- nbits_int := nbits - nbits_frac-1;
-
- if is_neg then
- dst(nbits-1 downto 0) := -dst(nbits-1 downto 0);
- end if;
-
- return to_sfixed(dst(nbits-1 downto 0), nbits, nbits_int);
-
- end to_sfixed;
-
- -------------------------------------------------------------
- function to_unsigned (src : ufixed_t) return UNSIGNED is
- subtype t is UNSIGNED(src'high - src'low downto 0);
- variable slv : t;
- begin
- slv := t(src);
- return UNSIGNED(to_X01(std_logic_vector(slv)));
-
- end function to_unsigned;
-
- -------------------------------------------------------------
- function to_signed (src : sfixed_t) return SIGNED is
- subtype t is SIGNED(src'high - src'low downto 0);
- variable slv : t;
- begin
- slv := t(src);
- return SIGNED(to_X01(std_logic_vector(slv)));
-
- end function to_signed;
-
- -------------------------------------------------------------
- -- integer <= ufixed
- function to_integer (src : ufixed_t) return integer is
- begin
- return to_integer(to_unsigned(src));
- end to_integer;
-
- -------------------------------------------------------------
- -- integer <= sfixed
- function to_integer (src : sfixed_t) return integer is
- begin
- return to_integer(to_signed(src));
- end to_integer;
-
- -------------------------------------------------------------
- -- to_real
- function to_real(src : ufixed_t) return real is
- variable dst : real := 0.0;
- begin
- for i in src'range loop
- if (src(i) = '1') then
- dst := dst + real(2.0**i);
- end if;
- end loop;
- return dst;
-
- end to_real;
-
- -------------------------------------------------------------
- function to_real(src : sfixed_t) return real is
- variable dst : real := 0.0;
- begin
- dst := to_real(to_ufixed(src));
-
- if (src(src'high) = '1') then
- dst := -dst;
- end if;
-
- return dst;
-
- end to_real;
-
- -------------------------------------------------------------
- -- to_slv
- function to_slv (src : ufixed_t) return STD_LOGIC_VECTOR is
- subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0);
- variable slv : t;
- begin
- if src'length < 1 then
- return NSLV;
- end if;
- slv := t (src);
- return slv;
-
- end function to_slv;
-
- -------------------------------------------------------------
- -- to_slv
- function to_slv (src : sfixed_t) return STD_LOGIC_VECTOR is
- subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0);
- variable slv : t;
- begin
- if src'length < 1 then
- return NSLV;
- end if;
- slv := t (src);
- return slv;
-
- end function to_slv;
-
- -------------------------------------------------------------
- function to_string(src : ufixed_t) return string is
- variable str : string(src'length+1 downto 1) := (others => '0');
- variable i, j : integer := 0;
-
- begin
- j := src'length+1;
- for i in src'high downto 0 loop
- if (src(i) = '1') then
- str(j) := '1';
- end if;
- j := j - 1;
- end loop;
-
- str(j) := '.';
- j := j - 1;
-
- for i in -1 downto src'low loop
- if (src(i) = '1') then
- str(j) := '1';
- end if;
- j := j - 1;
- end loop;
-
- return str;
-
- end to_string;
-
- -------------------------------------------------------------
- function to_string(src : sfixed_t) return string is
- variable str : string(src'length+1 downto 1) := (others => '0');
- variable i, j, start : integer := 0;
- variable strlen : integer := 0;
- variable src_abs : sfixed_t(src'range) := (others => '0');
-
- begin
- if (src'high < 0) then
- assert false report "Illegal signed fix point number" severity error;
- end if;
-
- start := src'high;
- strlen := src'length;
-
- j := src'length+1;
- if (src(start) = '1') then
- str(j) := '-';
- j := j - 1;
- start := start - 1;
- strlen := strlen + 1;
- end if;
-
- src_abs := abs(src);
-
- for i in start downto 0 loop
- if (src_abs(i) = '1') then
- str(j) := '1';
- end if;
- j := j - 1;
- end loop;
-
- str(j) := '.';
- j := j - 1;
-
- for i in -1 downto src'low loop
- if (src_abs(i) = '1') then
- str(j) := '1';
- end if;
- j := j - 1;
- end loop;
-
- return str(strlen downto 1);
-
- end to_string;
-
- -------------------------------------------------------------
- function to_string(src : std_logic_vector) return string is
- variable str : string(src'length downto 1) := (others => '0');
- variable i : integer := 0;
-
- begin
- for i in src'range loop
- if (src(i) = '1') then
- str(i+1) := '1';
- end if;
- end loop;
-
- return str;
-
- end to_string;
-
- -------------------------------------------------------------
- -- Binary Operators
- -------------------------------------------------------------
- function "sla" (src : ufixed_t; count : integer) return ufixed_t is
- variable result : ufixed_t (src'high downto src'low) := (others => '0');
-
- begin
- if (count = 0) then
- result := src;
- elsif (count < 0) then
- result := src sra -count;
- elsif (count < src'length) then
- result(src'high downto src'low) := src(src'high-count downto src'low) & (count-1 downto 0 => '0');
- end if;
- return result;
-
- end "sla";
-
- -------------------------------------------------------------
- function "sla" (src : sfixed_t; count : integer) return sfixed_t is
- variable result : sfixed_t (src'high downto src'low) := (others => '0');
- variable sign : std_logic := '0';
-
- begin
- sign := src(src'high);
- if (count = 0) then
- result := src;
- elsif (count < 0) then
- result := src sra -count;
- elsif (count < src'length-1) then
- result(src'high downto src'low) := sign & src(src'high-count-1 downto src'low) & (count-1 downto 0 => '0');
- end if;
- return result;
-
- end "sla";
-
- -------------------------------------------------------------
- function "sra" (src : ufixed_t; count : integer) return ufixed_t is
- variable result : ufixed_t (src'high downto src'low) := (others => '0');
-
- begin
- if (count = 0) then
- result := src;
- elsif (count < 0) then
- result := src sla -count;
- elsif (count < src'length) then
- result(src'high downto src'low) := (count-1 downto 0 => '0') & src(src'high downto src'low + count);
- end if;
- return result;
-
- end "sra";
-
- -------------------------------------------------------------
- function "sra" (src : sfixed_t; count : integer) return sfixed_t is
- variable result : sfixed_t (src'high downto src'low) := (others => '0');
- variable res_slv, src_slv : signed (src'length-1 downto 0) := (others => '0');
- variable sign, do_sub : std_logic := '0';
-
- begin
- src_slv := to_signed(src);
- sign := src(src'high);
- do_sub := src(src'high) and src(src'low);
- if (count = 0) then
- result := src;
- elsif (count < 0) then
- result := src sla -count;
- elsif (count < src'length-1) then
- res_slv := (count downto 0 => sign) & src_slv(src'length-2 downto count);
- if (do_sub = '1') then
- result(src'high downto src'low) := to_sfixed(res_slv+1, result);
- else
- result(src'high downto src'low) := to_sfixed(res_slv, result);
- end if;
- end if;
- return result;
-
- end "sra";
-
- -------------------------------------------------------------
- function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t is
- variable result : ufixed_t (uproto(a,'*',b)'high downto uproto(a,'*',b)'low);
-
- begin
- if (a'high < 0 and b'high >= 0) or (a'high >= 0 and b'high < 0) then
- result := to_ufixed(to_unsigned(a) * to_unsigned(b), result) sla 1;
- else
- result := to_ufixed(to_unsigned(a) * to_unsigned(b), result);
- end if;
- return result;
-
- end "*";
-
- -------------------------------------------------------------
- function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t is
- variable result : sfixed_t (sproto(a,'*',b)'high downto sproto(a,'*',b)'low);
-
- begin
- if (a'high = 0 and b'high > 0) or (a'high > 0 and b'high = 0) then
- result := to_sfixed(signed(a) * signed(b), result) sla 2;
- else
- result := to_sfixed(signed(a) * signed(b), result) sla 1;
- end if;
- return result;
-
- end "*";
-
- -------------------------------------------------------------
- function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t is
-
- begin
- return to_sfixed(a) * b;
-
- end "*";
-
- -------------------------------------------------------------
- function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t is
-
- begin
- return b * a;
-
- end "*";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t is
- variable result : ufixed_t (uproto(a,'+',b)'high downto uproto(a,'+',b)'low);
-
- begin
- result := ufixed_t(unsigned(reshape(a, result)) + unsigned(reshape(b, result)));
- return result;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t is
- variable result : sfixed_t (sproto(a,'+',b)'high downto sproto(a,'+',b)'low);
-
- begin
- result := to_sfixed(signed(reshape(a,result)) + signed(reshape(b,result)), result);
--- result := to_sfixed(signed(a) + signed(b), result);
- return result;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t is
-
- begin
- return to_sfixed(a) + b;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t is
-
- begin
- return b + a;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : unsigned) return ufixed_t is
-
- begin
-
- return ufixed_t(unsigned(a) + b);
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : signed) return sfixed_t is
-
- begin
-
- return sfixed_t(signed(a) + b);
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : integer) return ufixed_t is
-
- begin
-
- return ufixed_t(unsigned(a) + to_unsigned(b, a'length));
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : integer) return sfixed_t is
-
- begin
-
- return sfixed_t(signed(a) + to_signed(b, a'length));
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : std_logic) return ufixed_t is
- variable result : ufixed_t (a'high downto a'low);
- variable buns : unsigned(a'length-1 downto 0);
-
- begin
- buns := (a'length-1 downto 1 => '0') & b;
- result := ufixed_t(to_unsigned(a) + buns);
- return result;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : std_logic) return sfixed_t is
- variable result : sfixed_t (a'high downto a'low);
- variable bs : signed(a'length-1 downto 0);
-
- begin
- bs := (a'length-1 downto 1 => '0') & b;
- result := sfixed_t(to_signed(a) + bs);
- return result;
-
- end "+";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t is
- variable result : ufixed_t (uproto(a,'-',b)'high downto uproto(a,'-',b)'low);
- begin
- result := to_ufixed(to_sfixed(a) - to_sfixed(b));
- return result;
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t is
- variable result : sfixed_t (sproto(a,'-',b)'high downto sproto(a,'-',b)'low);
-
- begin
- result := to_sfixed(signed(reshape(a,result)) - signed(reshape(b,result)), result);
- return result;
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t is
- begin
- return to_sfixed(a) - b;
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t is
-
- begin
- return a - to_sfixed(b);
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : unsigned) return ufixed_t is
-
- begin
- return ufixed_t(unsigned(a) - b);
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : signed) return sfixed_t is
-
- begin
- return sfixed_t(signed(a) - b);
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : integer) return ufixed_t is
-
- begin
-
- return ufixed_t(unsigned(a) - to_unsigned(b, a'length));
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : integer) return sfixed_t is
-
- begin
-
- return sfixed_t(signed(a) - to_signed(b, a'length));
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : std_logic) return ufixed_t is
- variable result : ufixed_t (a'high downto a'low);
- variable buns : unsigned(a'length-1 downto 0);
-
- begin
- buns := (a'length-1 downto 1 => '0') & b;
- result := ufixed_t(unsigned(a) - buns);
- return result;
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : std_logic) return sfixed_t is
- variable result : sfixed_t (a'high downto a'low);
- variable bs : signed(a'length-1 downto 0);
-
- begin
- bs := (a'length-1 downto 1 => '0') & b;
- result := sfixed_t(signed(a) - bs);
- return result;
-
- end "-";
-
- -------------------------------------------------------------
- -- Unary Operators
- -------------------------------------------------------------
- function "abs" (src : sfixed_t) return sfixed_t is
- begin
- return to_sfixed(abs(signed(src)), src);
-
- end "abs";
-
- -------------------------------------------------------------
- function "-" (src : ufixed_t) return sfixed_t is
- begin
- return -to_sfixed(src);
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (src : sfixed_t) return sfixed_t is
- begin
- return to_sfixed(-signed(src), src);
-
- end "-";
-
- -------------------------------------------------------------
- -- Binary Equality
- -------------------------------------------------------------
- function "=" (a : ufixed_t; b : ufixed_t) return boolean is
- variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_ufixed(a, ta);
- tb := to_ufixed(b, tb);
- return to_unsigned(ta) = to_unsigned(tb);
-
- end "=";
-
- -------------------------------------------------------------
- function "=" (a : sfixed_t; b : sfixed_t) return boolean is
- variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_sfixed(a, ta);
- tb := to_sfixed(b, tb);
- return to_signed(ta) = to_signed(tb);
-
- end "=";
-
- -------------------------------------------------------------
- function "=" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return to_sfixed(a) = b;
- end "=";
-
- -------------------------------------------------------------
- function "=" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return b = a;
- end "=";
-
- -------------------------------------------------------------
- -- Binary Inequality
- -------------------------------------------------------------
- function "/=" (a : ufixed_t; b : ufixed_t) return boolean is
- begin
- return not (a = b);
-
- end "/=";
-
- -------------------------------------------------------------
- function "/=" (a : sfixed_t; b : sfixed_t) return boolean is
- begin
- return not (a = b);
-
- end "/=";
-
- -------------------------------------------------------------
- function "/=" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return not (a = b);
- end "/=";
-
- -------------------------------------------------------------
- function "/=" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return not (a = b);
- end "/=";
-
- -------------------------------------------------------------
- -- Binary less than
- -------------------------------------------------------------
- function "<" (a : ufixed_t; b : ufixed_t) return boolean is
- variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_ufixed(a, ta);
- tb := to_ufixed(b, tb);
- return to_unsigned(ta) < to_unsigned(tb);
-
- end "<";
-
- -------------------------------------------------------------
- function "<" (a : sfixed_t; b : sfixed_t) return boolean is
- variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_sfixed(a, ta);
- tb := to_sfixed(b, tb);
- return to_signed(ta) < to_signed(tb);
-
- end "<";
-
- -------------------------------------------------------------
- function "<" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return to_sfixed(a) < b;
-
- end "<";
-
- -------------------------------------------------------------
- function "<" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return a < to_sfixed(b);
-
- end "<";
-
- -------------------------------------------------------------
- -- Binary greater than
- -------------------------------------------------------------
- function ">" (a : ufixed_t; b : ufixed_t) return boolean is
- variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_ufixed(a, ta);
- tb := to_ufixed(b, tb);
- return to_unsigned(ta) > to_unsigned(tb);
-
- end ">";
-
- -------------------------------------------------------------
- function ">" (a : sfixed_t; b : sfixed_t) return boolean is
- variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_sfixed(a, ta);
- tb := to_sfixed(b, tb);
- return to_signed(ta) > to_signed(tb);
-
- end ">";
-
- -------------------------------------------------------------
- function ">" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return to_sfixed(a) > b;
- end ">";
-
- -------------------------------------------------------------
- function ">" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return a > to_sfixed(b);
- end ">";
-
- -------------------------------------------------------------
- -- Binary less equal than
- -------------------------------------------------------------
- function "<=" (a : ufixed_t; b : ufixed_t) return boolean is
- begin
- return not (a > b);
- end "<=";
-
- function "<=" (a : sfixed_t; b : sfixed_t) return boolean is
- begin
- return not (a > b);
- end "<=";
-
- function "<=" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return not (a > b);
- end "<=";
-
- function "<=" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return not (a > b);
- end "<=";
-
- -------------------------------------------------------------
- -- Binary greater or equal than
- -------------------------------------------------------------
- function ">=" (a : ufixed_t; b : ufixed_t) return boolean is
- begin
- return not (a < b);
- end ">=";
-
- function ">=" (a : sfixed_t; b : sfixed_t) return boolean is
- begin
- return not (a < b);
- end ">=";
-
- function ">=" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return not (a < b);
- end ">=";
-
- function ">=" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return not (a < b);
- end ">=";
-
- -------------------------------------------------------------
- -- Misc. Operators
- -------------------------------------------------------------
- function ipart (src : ufixed_t) return ufixed_t is
- begin
- return src(src'high downto 0);
- end ipart;
-
- function fpart (src : ufixed_t) return ufixed_t is
- begin
- return src(-1 downto src'low);
- end fpart;
-
- function ipart (src : sfixed_t) return sfixed_t is
- begin
- return src(src'high-1 downto 0);
- end ipart;
-
- function fpart (src : sfixed_t) return sfixed_t is
- begin
- return src(-1 downto src'low);
- end fpart;
-
- -------------------------------------------------------------
- -- Print functions
- -------------------------------------------------------------
- procedure print_info(src : in ufixed_t; prefix : in string) is
- variable L : line;
-
- begin
- write (L, prefix & "'length = ");write (L, src'length);
- writeline (output, L);
-
- write (L, prefix & "'high(left) = ");
- write (L, src'high);
- write (L, '(');
- write (L, src'left);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'low(right) = ");
- write (L, src'low);
- write (L, '(');
- write (L, src'right);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'value = B");write (L, to_string(src));
- writeline (output, L);
-
- write (L, prefix & "'value = ");write (L, to_real(src));
- writeline (output, L);
-
- -- write (L, prefix & "'cmsb = ");write (L, cmsb(src));
- -- writeline (output, L);
-
- -- write (L, prefix & "'clsb = ");write (L, clsb(src));
- -- writeline (output, L);
-
- writeline (output, L);
-
- end print_info;
-
- -------------------------------------------------------------
- procedure print_info(src : in sfixed_t; prefix : in string) is
- variable L : line;
-
- begin
- write (L, prefix & "'length = ");write (L, src'length);
- writeline (output, L);
-
- write (L, prefix & "'high(left) = ");
- write (L, src'high);
- write (L, '(');
- write (L, src'left);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'low(right) = ");
- write (L, src'low);
- write (L, '(');
- write (L, src'right);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'value = B");write (L, to_string(src));
- writeline (output, L);
-
- write (L, prefix & "'value = ");write (L, to_real(src));
- writeline (output, L);
-
- -- write (L, prefix & "'cmsb = ");write (L, cmsb(src));
- -- writeline (output, L);
-
- -- write (L, prefix & "'clsb = ");write (L, clsb(src));
- -- writeline (output, L);
-
- writeline (output, L);
-
- end print_info;
-
- -------------------------------------------------------------
- procedure print_info(src : in string; prefix : in string) is
- variable L : line;
-
- begin
- write (L, prefix & "'length = ");write (L, src'length);
- writeline (output, L);
-
- write (L, prefix & "'high(left) = ");
- write (L, src'high);
- write (L, '(');
- write (L, src'left);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'low(right) = ");
- write (L, src'low);
- write (L, '(');
- write (L, src'right);
- write (L, ')');
- writeline (output, L);
-
- writeline (output, L);
-
- end print_info;
-
- -------------------------------------------------------------
- -- Helpers
- -------------------------------------------------------------
- -- Count significant bits for integer part
- function cmsb(src : ufixed_t) return integer is
- variable j, i : integer := src'high;
- begin
- for i in src'range loop
- if src(i) = '1' then
- exit;
- end if;
- j := j - 1;
- end loop;
-
- -- LRM nachlesen: hier is i=src'high re-initialisert
-
- return j;
-
- end cmsb;
-
- -------------------------------------------------------------
- -- Count significant bits for fractional part
- function clsb(src : ufixed_t) return integer is
- variable j, i : integer := src'low;
- begin
- for i in src'reverse_range loop
- if src(i) = '1' then
- exit;
- end if;
- j := j + 1;
- end loop;
-
- -- LRM nachlesen: hier is i=src'low re-initialisert
-
- return j;
-
- end clsb;
-
- -------------------------------------------------------------
- function MIN (X, Y: INTEGER) return INTEGER is
- variable res : integer := X;
- begin
- if Y < X then
- res := Y;
- end if;
-
- return res;
-
- end MIN;
-
- -------------------------------------------------------------
- function MAX (X, Y: INTEGER) return INTEGER is
- variable res : integer := X;
- begin
- if Y > X then
- res := Y;
- end if;
-
- return res;
-
- end MAX;
-
- -------------------------------------------------------------
- function "MOD" (X, Y: in REAL ) return REAL is
- -- Description:
- -- See function declaration in IEEE Std 1076.2-1996
- -- Notes:
- -- a) Returns 0.0 on error
-
- variable XNEGATIVE : BOOLEAN := X < 0.0;
- variable YNEGATIVE : BOOLEAN := Y < 0.0;
- variable VALUE : REAL;
- begin
- -- Check validity of input arguments
- if (Y = 0.0) then
- assert FALSE
- report "MOD(X, 0.0) is undefined"
- severity ERROR;
- return 0.0;
- end if;
-
- -- Compute value
- if ( XNEGATIVE ) then
- if ( YNEGATIVE ) then
- VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
- else
- VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
- end if;
- else
- if ( YNEGATIVE ) then
- VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
- else
- VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
- end if;
- end if;
-
- return VALUE;
-
- end "MOD";
-
- -------------------------------------------------------------
- -- misc. conversion
- function ipart(src : real) return real is
- begin
- return floor(src);
-
- end ipart;
-
- -------------------------------------------------------------
- function fpart(src : real) return real is
- begin
- return src - floor(src);
-
- end fpart;
-
- -------------------------------------------------------------
- function or_red (arg : STD_LOGIC_VECTOR)
- return STD_LOGIC is
- variable Upper, Lower : STD_LOGIC;
- variable Half : INTEGER;
- variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
- variable Result : STD_LOGIC;
- begin
- if (arg'length < 1) then -- In the case of a NULL range
- Result := '0';
- else
- BUS_int := to_ux01 (arg);
- if (BUS_int'length = 1) then
- Result := BUS_int (BUS_int'left);
- elsif (BUS_int'length = 2) then
- Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
- else
- Half := (BUS_int'length + 1) / 2 + BUS_int'right;
- Upper := or_red (BUS_int (BUS_int'left downto Half));
- Lower := or_red (BUS_int (Half - 1 downto BUS_int'right));
- Result := Upper or Lower;
- end if;
- end if;
- return Result;
-
- end function or_red;
-
- -------------------------------------------------------------
- function and_red (arg : STD_LOGIC_VECTOR)
- return STD_LOGIC is
- variable Upper, Lower : STD_LOGIC;
- variable Half : INTEGER;
- variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
- variable Result : STD_LOGIC;
- begin
- if (arg'length < 1) then -- In the case of a NULL range
- Result := '1';
- else
- BUS_int := to_ux01 (arg);
- if (BUS_int'length = 1) then
- Result := BUS_int (BUS_int'left);
- elsif (BUS_int'length = 2) then
- Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
- else
- Half := (BUS_int'length + 1) / 2 + BUS_int'right;
- Upper := and_red (BUS_int (BUS_int'left downto Half));
- Lower := and_red (BUS_int (Half - 1 downto BUS_int'right));
- Result := Upper and Lower;
- end if;
- end if;
- return Result;
-
- end function and_red;
-
- -------------------------------------------------------------
- function xor_red (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
- variable Upper, Lower : STD_ULOGIC;
- variable Half : INTEGER;
- variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
- variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
- begin
- if (arg'length >= 1) then
- BUS_int := to_ux01 (arg);
- if (BUS_int'length = 1) then
- Result := BUS_int (BUS_int'left);
- elsif (BUS_int'length = 2) then
- Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
- else
- Half := (BUS_int'length + 1) / 2 + BUS_int'right;
- Upper := xor_red (BUS_int (BUS_int'left downto Half));
- Lower := xor_red (BUS_int (Half - 1 downto BUS_int'right));
- Result := Upper xor Lower;
- end if;
- end if;
- return Result;
-
- end function xor_red;
-
- -------------------------------------------------------------
- -- Reduction operators, same as numeric_std functions
- function and_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return and_red (to_slv(arg));
- end function and_red;
-
- function nand_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return not and_red (to_slv(arg));
- end function nand_red;
-
- function or_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return or_red (to_slv(arg));
- end function or_red;
-
- function nor_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return not or_red (to_slv(arg));
- end function nor_red;
-
- function xor_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return xor_red (to_slv(arg));
- end function xor_red;
-
- function xnor_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return not xor_red (to_slv(arg));
- end function xnor_red;
-
- function and_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return and_red (to_slv(arg));
- end function and_red;
-
- function nand_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return not and_red (to_slv(arg));
- end function nand_red;
-
- function or_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return or_red (to_slv(arg));
- end function or_red;
-
- function nor_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return not or_red (to_slv(arg));
- end function nor_red;
-
- function xor_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return xor_red (to_slv(arg));
- end function xor_red;
-
- function xnor_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return not xor_red (to_slv(arg));
- end function xnor_red;
-
- -------------------------------------------------------------
-
-end; -- package body fixed_ja;
diff --git a/lib/jasm/cg.inc.jsm b/lib/jasm/cg.inc.jsm
deleted file mode 100644
index 01c36c4..0000000
--- a/lib/jasm/cg.inc.jsm
+++ /dev/null
@@ -1,72 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xio-address equates for
-; reg_cg_char_addr: equ 0xXX ; RW
-; reg_cg_line_addr: equ 0xXX ; RW
-; reg_cg_data: equ 0xXX ; RW
-; reg_cg_ctrl: equ 0xXX ; WO
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-cg_clr_line: push R0
- mov R0, 2
- xout (reg_cg_ctrl), R0
- pop R0
- ret
-
-; -------------------------------------------------
-cg_clr_screen: push R0
- mov R0, 1
- xout (reg_cg_ctrl), R0
- pop R0
- ret
-
-; -------------------------------------------------
-; R0 : char address
-; R1 : line address
-cg_set_addr: call cg_wait_rdy
- xout (reg_cg_line_addr), R1
- xout (reg_cg_char_addr), R0
- ret
-
-; -------------------------------------------------
-; R0 : character
-cg_putchar: call cg_wait_rdy
- xout (reg_cg_data), R0
- ret
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts: push R0
-cg_p_lp: movx R0, (R1)
- inc R1
- tst R0
- jz ex_cgp
- call cg_putchar
- jmp cg_p_lp
-ex_cgp: pop R0
- ret
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_clr_puts: call cg_clr_line
- call cg_puts
- ret
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts_clr: call cg_puts
- call cg_clr_line
- ret
-
-; -------------------------------------------------
-cg_wait_rdy: push R0
-cg_wr_lp: xin R0, (reg_hwstat)
- and R0, 0x02
- jz cg_wr_lp
- pop R0
- ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/cregs.inc.jsm b/lib/jasm/cregs.inc.jsm
deleted file mode 100644
index 06d39d9..0000000
--- a/lib/jasm/cregs.inc.jsm
+++ /dev/null
@@ -1,7 +0,0 @@
-; JCPU On-Chip register
-cpu_revision: equ 0x00 ; RO
-cpu_control: equ 0x01 ; R/W
-cpu_status: equ 0x02 ; RO
-cpu_int_ctrl: equ 0x03 ; RW
-cpu_cmem_high: equ 0x04 ; RW
-cpu_stack_high: equ 0x05 ; RW
diff --git a/lib/jasm/delays.inc.jsm b/lib/jasm/delays.inc.jsm
deleted file mode 100644
index 6f002ee..0000000
--- a/lib/jasm/delays.inc.jsm
+++ /dev/null
@@ -1,64 +0,0 @@
-; -------------------------------------------------
-; Delays
-; -------------------------------------------------
-delay1s: push R15
- mov R15, 10
-loop1s: call delay100ms
- dec R15
- jnz loop1s
- pop R15
- ret
-
-delay100ms: push R15
- mov R15, 10
-loop100ms: call delay10ms
- dec R15
- jnz loop100ms
- pop R15
- ret
-
-delay10ms: push R15
- mov R15, 10
-loop10ms: call delay1ms
- dec R15
- jnz loop10ms
- pop R15
- ret
-
-delay1ms: push R15
- mov R15, 10
-loop1ms: call delay100us
- dec R15
- jnz loop1ms
- pop R15
- ret
-
-delay100us: push R15
- mov R15, 10
-loop100us: call delay10us
- dec R15
- jnz loop100us
- pop R15
- ret
-
-delay10us: push R15
- mov R15, 99
-loop10us: nop
- nop
- nop
- dec R15
- jnz loop10us
- pop R15
- ret
-
-delay1us: push R15
- mov R15, 9
-loop1us: nop
- nop
- nop
- dec R15
- jnz loop1us
- pop R15
- ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/lcd.inc.jsm b/lib/jasm/lcd.inc.jsm
deleted file mode 100644
index d2883fa..0000000
--- a/lib/jasm/lcd.inc.jsm
+++ /dev/null
@@ -1,208 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - lcd_port (LCD-Base)
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-lcd_cmd: equ 0x00
-lcd_rd: equ 0x20
-lcd_data: equ 0x40
-lcd_enable: equ 0x80
-
-LCD_CMD_Z1: equ 0x80
-LCD_CMD_Z2: equ 0xC0
-LCD_CMD_CLEAR: equ 0x01
-
-; -------------------------------------------------
-; Init LCD
-; -------------------------------------------------
-LCD_init: mov R2, 0x00
- mov R0, 0x03
- call _write_lcd
- call delay10ms
- mov R2, 0x00
- mov R0, 0x03
- call _write_lcd
- call delay10ms
-
- mov R2, 0x00
- mov R0, 0x02
- call _write_lcd
- call delay1ms
-
- ; 1. Function set: 4-Bit mode, two display lines
- mov R0, 0x28
- call LCD_writecmd
-
- ; 2. Display on, no cursor
- mov R0, 0x0C
- call LCD_writecmd
-
- ; 3. Cursor shift during write
- mov R0, 0x06
- call LCD_writecmd
-
- ; 4. Display clear
- mov R0, 0x01
- call LCD_writecmd
-
- ret
-
-; -------------------------------------------------
-; LCD_waitbsy
-; -------------------------------------------------
-LCD_waitbsy: push R0
-bsy_loop: call LCD_readstat
- and R0, 0x80
- jz ex_bsy
- call delay1us
- jmp bsy_loop
-ex_bsy: pop R0
- ret
-
-; -------------------------------------------------
-; LCD_writecmd
-; -------------------------------------------------
-; R0 = cmd
-LCD_writeaddr:
-LCD_writecmd: push R2
- mov R2, lcd_cmd
- call LCD_write
- pop R2
- ret
-
-; -------------------------------------------------
-; LCD_putsx
-; -------------------------------------------------
-; R1 = address of null-terminated string in XMEM
-LCD_putsx: push R0
-putsx_loop: movx R0, (R1)
- inc R1
- tst R0
- jz putsx_ex
- call LCD_writechar
- jmp putsx_loop
-putsx_ex: pop R0
- ret
-
-; -------------------------------------------------
-; LCD_putsc
-; -------------------------------------------------
-; R1 = address of null-terminated string in CMEM
-LCD_putsc: push R0
-putsc_loop: movc R0, (R1)
- inc R1
- tst R0
- jz putsc_ex
- call LCD_writechar
- jmp putsc_loop
-putsc_ex: pop R0
- ret
-
-; -------------------------------------------------
-; LCD_writechar
-; -------------------------------------------------
-; R0 = char
-LCD_writedata:
-LCD_writechar: push R2
- mov R2, lcd_data
- call LCD_write
- pop R2
- ret
-
-; -------------------------------------------------
-; LCD_write
-; -------------------------------------------------
-; R0 = input
-; R2 = register
-LCD_write: call LCD_waitbsy
- push R0
- swap R0
- call _write_lcd
- pop R0
- call _write_lcd
- ret
-
-; -------------------------------------------------
-; LCD_readstat
-; -------------------------------------------------
-; R0 = status
-LCD_readstat: push R2
- mov R2, lcd_cmd
- call LCD_read
- pop R2
- ret
-
-; -------------------------------------------------
-; LCD_read
-; -------------------------------------------------
-; R0 = output
-; R2 = register
-LCD_read: call _read_lcd
- swap R0
- push R0
- call _read_lcd
- pop R2
- or R0, R2
- ret
-
-; -------------------------------------------------
-; _write
-; -------------------------------------------------
-; R0 = input
-_write_lcd: push R1
-
- and R0, 0x0F
- mov R1, R0
- or R1, R2
- xout (lcd_port), R1
- call delay1us
-
- mov R1, R0
- or R1, R2
- or R1, lcd_enable
- xout (lcd_port), R1
- call delay1us
-
- mov R1, R0
- or R1, R2
- xout (lcd_port), R1
- call delay1us
-
- or R1, lcd_rd
- xout (lcd_port), R1
-
- pop R1
- ret
-
-; -------------------------------------------------
-; _read
-; -------------------------------------------------
-; R0 = output
-_read_lcd: push R1
-
- mov R1, lcd_rd
- or R1, R2
- xout (lcd_port), R1
- call delay1us
-
- mov R1, lcd_rd
- or R1, R2
- or R1, lcd_enable
- xout (lcd_port), R1
- call delay1us
- xin R0, (lcd_port)
- and R0, 0x0F
-
- mov R1, lcd_rd
- or R1, R2
- xout (lcd_port), R1
- call delay1us
-
- pop R1
- ret
-
-
\ No newline at end of file
diff --git a/lib/jasm/mul8x8.inc.jsm b/lib/jasm/mul8x8.inc.jsm
deleted file mode 100644
index 2f66e2a..0000000
--- a/lib/jasm/mul8x8.inc.jsm
+++ /dev/null
@@ -1,42 +0,0 @@
-; -------------------------------------------------
-; mul8x8.inc.jsm
-; -------------------------------------------------
-
-; -------------------------------------------------
-; Parameter:
-; R0 : operand 1
-; R1 : operand 2
-; Return:
-; R0 : product low
-; R1 : product high
-mul8x8: push R2
- push R3
- push R4
-
- mov R4, R1
- mov R1, 0
- mov R2, 0
- mov R3, 0
-
-loop1: cmp R4, 0x01
- jeq ende1
-
- shr R4
- jnc next1
-
- add R2, R0
- addc R3, R1
-
-next1: shl R0
- rolc R1
- jmp loop1
-
-ende1: add R0, R2
- addc R1, R3
-
- pop R4
- pop R3
- pop R2
- ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/uart.inc.jsm b/lib/jasm/uart.inc.jsm
deleted file mode 100644
index df557b1..0000000
--- a/lib/jasm/uart.inc.jsm
+++ /dev/null
@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; uart.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - uart_status (Status register)
-; - uart_data (Data register)
-
-; -------------------------------------------------
-; sout
-; -------------------------------------------------
-; R0 = input
-sout: push R1
-sout1: xin R1, (uart_status)
- and R1, 0x02
- jnz sout1
- xout (uart_data), R0
- pop R1
- ret
-
-; -------------------------------------------------
-; sin
-; -------------------------------------------------
-; R0 = output
-sin: push R1
-sin1: xin R1, (uart_status)
- and R1, 0x10
- jz sin1
- xin R0, (uart_data)
- pop R1
- ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/utils.inc.jsm b/lib/jasm/utils.inc.jsm
deleted file mode 100644
index f354d7c..0000000
--- a/lib/jasm/utils.inc.jsm
+++ /dev/null
@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; utils.inc.jsm
-; -------------------------------------------------
-
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value in lower nibble
-; Return
-; R0 : Hex character representing lower nibble
-nibble2hex: and R0, 0x0F
- cmp R0, 0x0A
- jlt isNum1
- add R0, 0x07
-isNum1: add R0, 0x30
- ret
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value
-; Return
-; R0 : Hex character high
-; R1 : Hex character low
-bin2hex: push R0
- call nibble2hex
- mov R1, R0
- pop R0
- swap R0
- call nibble2hex
- ret
-
-; -------------------------------------------------
diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd
index 854edd0..a2af1a2 100644
--- a/lib/misc/async_port_wb.vhd
+++ b/lib/misc/async_port_wb.vhd
@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.13 2009-11-04 19:26:53 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -10,10 +10,9 @@ use work.async_types.all;
entity async_port_wb is
Generic
(
- f_sysclk : real := 100.0;
- addr_width : natural := 32;
- data_width : natural := 32;
- byte_sel_width : natural := 4;
+ addr_width : natural := 32;
+ data_width : natural := 32;
+ byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
Port
@@ -57,8 +56,8 @@ architecture Behavioral of async_port_wb is
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
- signal cycle_cnt : natural range 0 to 31;
- signal cycle_reload : natural range 0 to 31;
+ signal cycle_cnt : natural range 0 to 15;
+ signal cycle_reload : natural range 0 to 15;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
@@ -73,9 +72,9 @@ architecture Behavioral of async_port_wb is
------------------------------------------------------------------
begin
- ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
- ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
- ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
+ ASSERT async_timespec.ncyc_pulse_rd > 0 report "Read pulse length must be greater than zero!" severity failure;
+ ASSERT async_timespec.ncyc_pulse_wr > 0 report "Write pulse length must be greater than zero!" severity failure;
+ ASSERT (not async_timespec.can_page_rd OR (async_timespec.ncyc_pulse_page_rd > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
@@ -111,7 +110,7 @@ architecture Behavioral of async_port_wb is
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
begin
- cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
+ cycle_reload <= async_timespec.ncyc_pulse_rst;
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
@@ -139,17 +138,17 @@ architecture Behavioral of async_port_wb is
if en = '1' then
as.cs <= '1';
cc_rst <= '1';
- if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
+ if async_timespec.ncyc_leadin = 0 then
sn <= pulse;
if WE_I = '1' then
cycle_reload <= 0;
sn <= leadin; -- always lead-in for writes
else
- cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
+ cycle_reload <= async_timespec.ncyc_pulse_rd-1;
as.rd <= '1';
end if;
else
- cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
+ cycle_reload <= async_timespec.ncyc_leadin-1;
sn <= leadin;
end if;
end if;
@@ -163,9 +162,9 @@ architecture Behavioral of async_port_wb is
cc_rst <= '1';
sn <= pulse;
if WE_I_r = '1' then
- cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
+ cycle_reload <= async_timespec.ncyc_pulse_wr-1;
else
- cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
+ cycle_reload <= async_timespec.ncyc_pulse_rd-1;
end if;
end if;
@@ -180,17 +179,17 @@ architecture Behavioral of async_port_wb is
ack <= not WE_I_r;
rdy <= do_page_read;
if en = '1' and do_page_read = '1' then
- cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
+ cycle_reload <= async_timespec.ncyc_pulse_page_rd-1;
sn <= pulse;
- elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
- if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
+ elsif async_timespec.ncyc_leadout = 0 then
+ if async_timespec.ncyc_release = 0 then
sn <= idle;
else
- cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
+ cycle_reload <= async_timespec.ncyc_release-1;
sn <= release;
end if;
else
- cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
+ cycle_reload <= async_timespec.ncyc_leadout-1;
sn <= leadout;
end if;
end if;
@@ -200,10 +199,10 @@ architecture Behavioral of async_port_wb is
as.drive_d <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
- if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
+ if async_timespec.ncyc_release = 0 then
sn <= idle;
else
- cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
+ cycle_reload <= async_timespec.ncyc_release-1;
sn <= release;
end if;
end if;
diff --git a/lib/misc/async_types.vhd b/lib/misc/async_types.vhd
index 1509dc1..295217f 100644
--- a/lib/misc/async_types.vhd
+++ b/lib/misc/async_types.vhd
@@ -24,20 +24,19 @@
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-USE IEEE.MATH_REAL.ALL;
package async_types is
type async_timespec_t is record
- T_leadin : real;
- T_pulse_rd : real;
- T_pulse_wr : real;
- T_leadout : real;
- T_release : real;
- T_pulse_rst : real;
- T_pulse_page_rd : real;
+ ncyc_leadin : natural;
+ ncyc_pulse_rd : natural;
+ ncyc_pulse_wr : natural;
+ ncyc_leadout : natural;
+ ncyc_release : natural;
+ ncyc_pulse_rst : natural;
can_page_rd : boolean;
nbits_page_rd : natural;
+ ncyc_pulse_page_rd : natural;
pol_cs : std_logic;
pol_oe : std_logic;
pol_we : std_logic;
@@ -45,16 +44,4 @@ package async_types is
pol_rst : std_logic;
end record;
- function to_cycles(T_ns : real; f_Mhz : real) return natural;
-
-end async_types;
-
-package body async_types is
-
- function to_cycles(T_ns : real; f_Mhz : real) return natural is
- begin
-
- return natural(ceil(1.0E-3*T_ns*f_Mhz));
-
- end to_cycles;
end async_types;
diff --git a/lib/misc/bbfifo.vhd b/lib/misc/bbfifo.vhd
deleted file mode 100644
index aa8799f..0000000
--- a/lib/misc/bbfifo.vhd
+++ /dev/null
@@ -1,123 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity bbfifo is
- Generic
- (
- depth : integer := 2;
- data_width : integer := 8
- );
- Port
- (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- re : in STD_LOGIC;
- we : in STD_LOGIC;
- ready : out STD_LOGIC;
- avail : out STD_LOGIC;
- din : in unsigned(data_width-1 downto 0);
- dout : out unsigned(data_width-1 downto 0)
- );
-end bbfifo;
-
-architecture Behavioral of bbfifo is
-
- type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
- signal req : unsigned(0 to depth);
- signal rdy : unsigned(1 to depth+1);
- signal bucket_array : bucket_array_t;
- signal ce_in : unsigned(1 to depth);
- signal ce_out : unsigned(1 to depth);
-
-begin
-
- req(0) <= we;
- rdy(depth+1) <= re;
- ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
- avail <= req(depth);
- bucket_array(0) <= din;
- dout <= bucket_array(depth);
-
-gen_ce:
- for i in 1 to depth generate
- begin
- process (rdy, req)
- begin
- ce_in(i) <= not req(i) and req(i-1);
- end process;
- end generate;
-
-gen_rdy:
- for i in 1 to depth generate
- begin
- process (clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- rdy(i) <= '1';
- elsif req(i-1) = '1' then
- rdy(i) <= rdy(i+1);
- end if;
- end if;
- end process;
- end generate;
-
-gen_req:
- for i in 1 to depth generate
- begin
- process (clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- req(i) <= '0';
- elsif rdy(i+1) = '1' then
- req(i) <= req(i-1);
- end if;
- end if;
- end process;
- end generate;
-
-gen_data:
- for i in 1 to depth generate
- begin
- process (clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- bucket_array(i) <= (others => '0');
- elsif req(i-1) = '1' then
- bucket_array(i) <= bucket_array(i-1);
- end if;
- end if;
- end process;
- end generate;
-
-end Behavioral;
-
diff --git a/lib/misc/clockgen_virtex4.vhd b/lib/misc/clockgen_virtex4.vhd
deleted file mode 100644
index 73a4c0e..0000000
--- a/lib/misc/clockgen_virtex4.vhd
+++ /dev/null
@@ -1,237 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Clock generator (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library ieee, work;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-USE WORK.utils_pkg.ALL;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity clockgen is
- generic
- (
- clk_in_freq : real := 100.0;
- clk0_out_phaseshift : integer := 0;
- clk1_out_phaseshift : integer := 0
- );
- port
- (
- -- Clocks and Reset
- rst : in std_logic; -- external async reset, low active
- clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
- clk_fb_in : in std_logic; -- feedback clock
- clk0_0_out : out std_logic; -- System clock #0, dcm#0 output 0°
- clk0_270_out : out std_logic; -- System clock #0, dcm#0 output 270°
- clk1_0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
- clk1_270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
- locked_out : out std_logic; -- DCM locked status
- error_out : out std_logic -- indicates DCM Errors
- );
-end;
-
-architecture tech of clockgen is
-
- signal locked : unsigned(1 downto 0);
- signal dcm_rst : unsigned(1 downto 0);
- signal clk1_0 : std_logic;
- signal clk1_270 : std_logic;
- signal clk1_0_bufg : std_logic;
- signal clk1_270_bufg : std_logic;
- signal clk0_0 : std_logic;
- signal clk0_270 : std_logic;
- signal clk0_0_bufg : std_logic;
- signal clk0_270_bufg : std_logic;
- signal dcm1_locked, dcm2_locked : unsigned(2 downto 0);
- signal cnt_q : unsigned(4 downto 0);
-
- type STATE_TYPE is (s0, s1, s2, s3, s4);
- signal state_q : STATE_TYPE;
-
-begin
-
- clk1_0_out <= clk1_0_bufg;
- clk1_270_out <= clk1_270_bufg;
- clk0_0_out <= clk0_0_bufg;
- clk0_270_out <= clk0_270_bufg;
-
-bufg11: bufg
- port map
- (
- o => clk0_0_bufg,
- i => clk0_0
- );
-
-bufg12: bufg
- port map (
- o => clk0_270_bufg,
- i => clk0_270
- );
-
-bufg13: bufg
- port map
- (
- o => clk1_0_bufg,
- i => clk1_0
- );
-
-bufg14: bufg
- port map (
- o => clk1_270_bufg,
- i => clk1_270
- );
-
- -------------------------------------------------------------------------------------------------------
- -- Clock generation
- -------------------------------------------------------------------------------------------------------
-
-inst_DCM_BASE_0 : DCM_BASE
- generic map (
- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
- -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
- CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
- CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
- CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
- CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
- DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
- DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
- -- an integer from 0 to 15
- DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
- DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
- FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
- PHASE_SHIFT => clk0_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
- STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
- port map (
- CLK0 => clk0_0, -- 0 degree DCM CLK ouptput
- CLK180 => open, -- 180 degree DCM CLK output
- CLK270 => clk0_270, -- 270 degree DCM CLK output
- CLK2X => open, -- 2X DCM CLK output
- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
- CLK90 => open, -- 90 degree DCM CLK output
- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
- CLKFX => open, -- DCM CLK synthesis out (M/D)
- CLKFX180 => open, -- 180 degree CLK synthesis out
- LOCKED => locked(0), -- DCM LOCK status output
- CLKFB => clk_fb_in, -- DCM clock feedback
- CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
- RST => dcm_rst(0) -- DCM asynchronous reset input
- );
-
- inst_DCM_BASE_1 : DCM_BASE
- generic map (
- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
- -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
- CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
- CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
- CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
- CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
- DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
- DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
- -- an integer from 0 to 15
- DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
- DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
- FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
- PHASE_SHIFT => clk1_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
- STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
- port map (
- CLK0 => clk1_0, -- 0 degree DCM CLK ouptput
- CLK180 => open, -- 180 degree DCM CLK output
- CLK270 => clk1_270, -- 270 degree DCM CLK output
- CLK2X => open, -- 2X DCM CLK output
- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
- CLK90 => open, -- 90 degree DCM CLK output
- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
- CLKFX => open, -- DCM CLK synthesis out (M/D)
- CLKFX180 => open, -- 180 degree CLK synthesis out
- LOCKED => locked(1), -- DCM LOCK status output
- CLKFB => clk1_0_bufg, -- DCM clock feedback
- CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
- RST => dcm_rst(1) -- DCM asynchronous reset input
- );
-
- dcm_rst(1) <= not locked(0);
-
-dcm_fsm:
- process(rst, clk_in)
- begin
- if rst = '1' then
- state_q <= s0;
- dcm_rst(0) <= '0';
- cnt_q <= "11111";
- error_out <= '0';
- locked_out <= '0';
- dcm1_locked <= (others => '0');
- dcm2_locked <= (others => '0');
- elsif rising_edge(clk_in) then
- case state_q is
- when s0 =>
- state_q <= s1;
-
- when s1 =>
- cnt_q <= cnt_q - 1;
- if cnt_q = 0 then
- dcm_rst(0) <= '1';
- state_q <= s2;
- end if;
-
- when s2 =>
- cnt_q <= cnt_q - 1;
- if cnt_q = 0 then
- dcm_rst(0) <= '0';
- state_q <= s3;
- end if;
-
- when s3 =>
- if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
- state_q <= s4;
- error_out <= '0';
- end if;
-
- when s4 =>
- if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
- locked_out <= '1';
- else
- error_out <= '1';
- end if;
- end case;
-
- -- synchronize 'dcm1_locked'
- dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
- dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
-
- end if;
- end process;
-
-end architecture tech;
-
-
diff --git a/lib/misc/debounce.vhd b/lib/misc/debounce.vhd
deleted file mode 100644
index 79317a5..0000000
--- a/lib/misc/debounce.vhd
+++ /dev/null
@@ -1,91 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 19:34:24 10/23/05
--- Design Name:
--- Module Name: debounce - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity debounce is
- Generic ( ncyc_latency : integer := 100);
- Port ( rst : in std_logic;
- clk : in std_logic;
- input : in std_logic;
- output : out std_logic);
-end debounce;
-
-architecture Behavioral of debounce is
-
-type debounce_state_t is (init_st, wait_st, rel_st);
-signal debounce_cs : debounce_state_t;
-signal debounce_ns : debounce_state_t;
-signal count : integer range 0 to ncyc_latency;
-signal input_last : std_logic;
-
-begin
-
- debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
- begin
- if (rst = '1') then
- count <= 0;
- output <= input;
- input_last <= input;
- else
- if rising_edge(clk) then
- debounce_cs <= debounce_ns;
- if (debounce_cs = wait_st) then
- if (count /= 0) then
- count <= count - 1;
- end if;
- else
- count <= ncyc_latency;
- if (debounce_cs = rel_st) then
- output <= input;
- input_last <= input;
- end if;
- end if;
- end if;
- end if;
- end process;
-
- debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
- begin
- debounce_ns <= debounce_cs;
- case debounce_cs is
- when init_st =>
- if (input /= input_last) then
- debounce_ns <= wait_st;
- end if;
- when wait_st =>
- if (count = 0) then
- debounce_ns <= rel_st;
- end if;
- when others =>
- debounce_ns <= init_st;
- end case;
- end process;
-
-end Behavioral;
diff --git a/lib/misc/debounce2.vhd b/lib/misc/debounce2.vhd
deleted file mode 100644
index 206a61c..0000000
--- a/lib/misc/debounce2.vhd
+++ /dev/null
@@ -1,142 +0,0 @@
--------------------------------------------------
--- Signal Debouncer
--- Jeff Bazinet
--- February 14, 2002
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-library lpm;
-use lpm.lpm_components.lpm_counter;
-
-
-entity debounce is
- generic(BUFFER_WIDTH: positive:= 30;
- CLOCK_DIV: positive:= 15
- );
- port( clock: in std_logic;
- reset: in std_logic;
- signal_in: in std_logic;
- signal_out: out std_logic
- );
-end entity debounce;
-
-
-architecture rtl of debounce is
-
- ---------------------------------------------------------------
- -- SIGNAL DECLARATION
- ---------------------------------------------------------------
-
- -- General
- signal reset_n: std_logic;
-
- -- SLOW CLOCK GENERATION
- signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0);
- signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1);
- signal clock_slow: std_logic;
- signal clock_slow_wire: std_logic;
-
- -- DATA BUFFER FILL
- signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
- signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
-
- -- CHECK FOR DEBOUNCE STABILITY
- signal stable: std_logic;
- signal stable_old: std_logic;
- signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
-
- -- PUSH BUTTON ENABLE
- signal button_pushed: std_logic;
-
- begin
-
- ---------------------------------------------------------------
- -- SLOW CLOCK GENERATION
- ---------------------------------------------------------------
-
- COUNTER_1: lpm_counter
- generic map (lpm_width => CLOCK_DIV)
- port map (
- clock => clock,
- sclr => reset_n,
- cout => clock_slow_wire
- );
-
- process (clock) is
- begin
-
- clock_slow <= clock_slow_wire;
-
- end process;
-
- ---------------------------------------------------------------
- -- DATA BUFFER FILL
- ---------------------------------------------------------------
-
- process (clock) is
- begin
-
- if (reset = '0') then
- -- Initialization
- data_buffer_reg <= (others => '1');
- elsif rising_edge(clock_slow) then
- data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
- end if;
-
- end process;
-
- ---------------------------------------------------------------
- -- CHECK FOR DEBOUNCE STABILITY
- ---------------------------------------------------------------
-
- process (clock) is
- begin
-
- if (reset = '0') then
- -- Initialization
- stable <= '0';
- stable_old <= '0';
- stable_state_reg <= (others => '0');
- elsif rising_edge(clock) then
- if (data_buffer_reg = stable_state_reg) then
- stable <= '1';
- stable_state_reg <= (others => '0');
- else
- stable <= '0';
- end if;
- stable_old <= stable;
- end if;
-
- end process;
-
- ---------------------------------------------------------------
- -- PUSH BUTTON ENABLE
- ---------------------------------------------------------------
-
- process (clock) is
- begin
-
- if (reset = '0') then
- -- Initialization
- button_pushed <= '0';
- elsif rising_edge(clock) then
- if (stable_old = '0' and stable = '1') then
- button_pushed <= '1';
- else
- button_pushed <= '0';
- end if;
- end if;
-
- end process;
-
- ---------------------------------------------------------------
- ---------------------------------------------------------------
-
- signal_out <= button_pushed;
- reset_n <= not reset;
-
-end rtl;
diff --git a/lib/misc/dpram_1w1r_dist.vhd b/lib/misc/dpram_1w1r_dist.vhd
deleted file mode 100644
index e07555c..0000000
--- a/lib/misc/dpram_1w1r_dist.vhd
+++ /dev/null
@@ -1,84 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r_dist is
- Generic
- (
- addr_width : integer := 3;
- data_width : integer := 8
- );
- Port
- (
- clka : in STD_LOGIC;
- clkb : in STD_LOGIC;
- en_a : in STD_LOGIC;
- en_b : in STD_LOGIC;
- we_a : in STD_LOGIC;
- addr_a : in unsigned (addr_width-1 downto 0);
- addr_b : in unsigned (addr_width-1 downto 0);
- din_a : in unsigned (data_width-1 downto 0);
- dout_b : out unsigned (data_width-1 downto 0)
- );
-end dpram_1w1r_dist;
-
-architecture Behavioral of dpram_1w1r_dist is
-
- constant depth : integer := 2**addr_width;
- type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
- signal RAM : RAMtype;
-
- attribute ram_style : string;
- attribute ram_style of RAM: signal is "distributed";
-
-begin
-
-process (clka)
- begin
- if clka'event and clka = '1' then
- if en_a = '1' then
- if we_a = '1' then
- RAM(to_integer(addr_a)) <= din_a;
- end if;
- end if;
- end if;
-end process;
-
-process (clkb)
- begin
- if clkb'event and clkb = '1' then
- if en_b = '1' then
- dout_b <= RAM(to_integer(addr_b));
- end if;
- end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/misc/flash_port_wb.vhd b/lib/misc/flash_port_wb.vhd
deleted file mode 100644
index 9dcc7fe..0000000
--- a/lib/misc/flash_port_wb.vhd
+++ /dev/null
@@ -1,293 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010-03-13 11:06:43 Jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.async_types.all;
-
- ------------------------------------------------------------------
-entity flash_port_wb is
- Generic
- (
- f_sysclk : real := 100.0;
- addr_width : natural := 32;
- data_width : natural := 32;
- async_timespec : async_timespec_t
- );
- Port
- (
- CLK_I : in STD_LOGIC;
- RST_I : in STD_LOGIC;
- CYC_I : in STD_LOGIC;
- STB_I : in STD_LOGIC;
- WE_I : in STD_LOGIC;
- ACK_O : out STD_LOGIC;
- SRDY_O : out STD_LOGIC;
- MRDY_I : in STD_LOGIC;
- ADDR_I : in unsigned(31 downto 0);
- DAT_I : in unsigned(31 downto 0);
- DAT_O : out unsigned(31 downto 0);
- port_bsyi : in std_logic;
- port_bsyo : out std_logic;
- port_a : out unsigned(addr_width-1 downto 0);
- port_di : in unsigned(data_width-1 downto 0);
- port_do : out unsigned(data_width-1 downto 0);
- port_d_drv : out STD_LOGIC;
- port_wr : out STD_LOGIC;
- port_rd : out STD_LOGIC;
- flash_cs : out std_logic;
- flash_rst : out std_logic
- );
-end flash_port_wb;
-
-architecture Behavioral of flash_port_wb is
-
- type async_t is record
- cs : std_logic;
- wr : std_logic;
- rd : std_logic;
- rst : std_logic;
- drive_d : std_logic;
- end record;
-
- type async_state_t is (start, reset, idle, go, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
-
- signal s, sn : async_state_t;
- signal as : async_t;
- signal ack : std_logic;
- signal cc_rst : std_logic;
- signal cycle_cnt : natural range 0 to 31;
- signal cycle_reload : natural range 0 to 31;
- signal rdy : std_logic;
- signal rdyo : std_logic;
- signal en : std_logic;
- signal we_reg : std_logic;
- signal data_reg : unsigned(data_width-1 downto 0);
- signal addr_reg : unsigned(addr_width-1 downto 0);
-
- ------------------------------------------------------------------
- begin
-
- SRDY_O <= CYC_I and rdyo;
- en <= CYC_I and STB_I;
- port_a <= addr_reg;
- port_do <= data_reg;
- port_d_drv <= as.drive_d;
- port_wr <= (not async_timespec.pol_we) xor as.wr;
- port_rd <= (not async_timespec.pol_oe) xor as.rd;
-
- proc_cycle_counter:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if cc_rst = '1' then
- cycle_cnt <= cycle_reload;
- elsif cycle_cnt /= 0 then
- cycle_cnt <= cycle_cnt - 1;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- proc_state_next:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- s <= start;
- else
- s <= sn;
- end if;
- end if;
- end process;
-
- proc_state:
- process(s, cycle_cnt, en, we_reg, port_bsyi)
- begin
-
- cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
- cc_rst <= '0';
- as.rst <= '0';
- as.cs <= '0';
- as.wr <= '0';
- as.rd <= '0';
- as.drive_d <= '0';
- ack <= '0';
- rdy <= '0';
- port_bsyo <= '1';
-
- sn <= s;
- case s is
-
- when start =>
- cc_rst <= '1';
- sn <= reset;
- when reset =>
- as.rst <= '1';
- if cycle_cnt = 0 then
- sn <= idle;
- end if;
- when idle =>
- port_bsyo <= '0';
- rdy <= '1';
- if en = '1' then
- sn <= go;
- end if;
- when go =>
- port_bsyo <= '0';
- if port_bsyi = '0' then
- as.cs <= '1';
- cc_rst <= '1';
- cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
- if we_reg = '0' then
- sn <= leadin_rd;
- else
- sn <= leadin_wr;
- end if;
- end if;
- when leadin_rd =>
- as.cs <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
- as.rd <= '1';
- sn <= read;
- end if;
-
- when leadin_wr =>
- as.cs <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
- as.wr <= '1';
- as.drive_d <= '1';
- sn <= write;
- end if;
-
- when read =>
- as.cs <= '1';
- as.rd <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
--- as.rd <= '0';
- sn <= leadout_rd;
- ack <= '1';
- end if;
-
- when write =>
- as.drive_d <= '1';
- as.cs <= '1';
- as.wr <= '1';
- if cycle_cnt = 0 then
- as.wr <= '0';
- cc_rst <= '1';
- cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
- sn <= leadout_wr;
--- ack <= '1';
- end if;
-
- when leadout_rd =>
- as.cs <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
- sn <= release;
- as.cs <= '0';
- end if;
-
- when leadout_wr =>
- as.cs <= '1';
- as.drive_d <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
- sn <= release;
- as.cs <= '0';
- end if;
-
- when release =>
- if cycle_cnt = 0 then
- sn <= idle;
- end if;
-
- when others =>
- sn <= idle;
-
- end case;
- end process;
-
- ------------------------------------------------------------------
- output_ctrl:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- flash_cs <= (not async_timespec.pol_cs) xor as.cs;
- flash_rst <= (not async_timespec.pol_rst) xor as.rst;
- end if;
- end process;
-
- ------------------------------------------------------------------
- din_register:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if as.rd = '1' then
- DAT_O(data_width-1 downto 0) <= port_di;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- data_register:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if en = '1' and rdy = '1' then
- we_reg <= WE_I;
- data_reg <= DAT_I(data_width-1 downto 0);
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- addr_register:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if en = '1' and rdy = '1' then
- addr_reg <= ADDR_I(addr_width-1 downto 0);
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- output_SRDY:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- rdyo <= '1';
- elsif en = '1' then
- rdyo <= rdy and not rdyo;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- output_ACK:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- ACK_O <= '0';
- else
- ACK_O <= ack;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
-
-end Behavioral;
diff --git a/lib/misc/gpio_wb.vhd b/lib/misc/gpio_wb.vhd
index 7434f85..6df62c0 100644
--- a/lib/misc/gpio_wb.vhd
+++ b/lib/misc/gpio_wb.vhd
@@ -3,10 +3,6 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY gpio_wb IS
- Generic
- (
- f_sysclk : real := 100.0
- );
Port
(
CLK_I : in STD_LOGIC;
@@ -23,45 +19,46 @@ ENTITY gpio_wb IS
DAT_O : out unsigned(31 downto 0);
INT_TIM_O : out STD_LOGIC;
- sys_gpi_0 : in unsigned(31 downto 0);
- sys_gpo_0 : out unsigned(31 downto 0)
+ sys_gpo0 : out unsigned(31 downto 0);
+ sys_gpo1 : out unsigned(31 downto 0);
+ sys_gpi0 : in unsigned(31 downto 0);
+ sys_gpi1 : in unsigned(31 downto 0)
);
END gpio_wb;
ARCHITECTURE behavior OF gpio_wb IS
- constant num_timers : natural := 2;
- constant ncycles_usec : natural := natural(f_sysclk);
+ constant num_timers : natural := 2;
- signal gpio_0_dout_reg : unsigned(31 downto 0);
- signal gpio_0_dir_reg : unsigned(31 downto 0);
- signal gpio_0_din_reg : unsigned(31 downto 0);
-
+ signal gpo0_reg : unsigned(31 downto 0);
+ signal gpo1_reg : unsigned(31 downto 0);
+ signal gpi0_reg : unsigned(31 downto 0);
+ signal gpi1_reg : unsigned(31 downto 0);
-- Signals to form an timer generating an interrupt every microsecond
- subtype tick_usec_t is natural range 0 to ncycles_usec-1;
- signal tick_usec : tick_usec_t := 0;
- signal cnt_usec : unsigned(31 downto 0);
- signal cnt_sec : unsigned(31 downto 0);
- signal cnt_usec_preset : unsigned(31 downto 0);
- signal cnt_sec_preset : unsigned(31 downto 0);
- signal cnt_usec_en : std_logic;
- signal cnt_usec_we : std_logic;
- signal cnt_sec_en : std_logic;
- signal cnt_sec_we : std_logic;
+ subtype tick_usec_t is natural range 0 to 99;
+ signal tick_usec : tick_usec_t;
+ signal cnt_usec : unsigned(31 downto 0);
+ signal cnt_sec : unsigned(31 downto 0);
+ signal cnt_usec_preset : unsigned(31 downto 0);
+ signal cnt_sec_preset : unsigned(31 downto 0);
+ signal cnt_usec_en : std_logic;
+ signal cnt_usec_we : std_logic;
+ signal cnt_sec_en : std_logic;
+ signal cnt_sec_we : std_logic;
type timer_array_t is array (0 to num_timers-1) of unsigned(31 downto 0);
- signal timer_cnt : timer_array_t;
- signal timer_cmp : timer_array_t;
- signal timer_en : unsigned(0 to num_timers-1);
- signal timer_inten : unsigned(0 to num_timers-1);
- signal timer_irq : unsigned(0 to num_timers-1);
- signal timer_ovl : unsigned(0 to num_timers-1);
- signal timer_irq_ack : unsigned(0 to num_timers-1);
- signal timer_cnt_we : unsigned(0 to num_timers-1);
- signal timer_cmp_we : unsigned(0 to num_timers-1);
+ signal timer_cnt : timer_array_t;
+ signal timer_cmp : timer_array_t;
+ signal timer_en : unsigned(0 to num_timers-1);
+ signal timer_inten : unsigned(0 to num_timers-1);
+ signal timer_irq : unsigned(0 to num_timers-1);
+ signal timer_ovl : unsigned(0 to num_timers-1);
+ signal timer_irq_ack : unsigned(0 to num_timers-1);
+ signal timer_cnt_we : unsigned(0 to num_timers-1);
+ signal timer_cmp_we : unsigned(0 to num_timers-1);
- signal reg_data_wr : unsigned(31 downto 0);
+ signal reg_data_wr : unsigned(31 downto 0);
begin
@@ -79,33 +76,25 @@ tim_irq:
end process;
------------------------------------------------------------------
-gpio_0_out:
- process(gpio_0_dir_reg, gpio_0_dout_reg)
- begin
- for i in 0 to 31 loop
- sys_gpo_0(i) <= 'Z';
- if gpio_0_dir_reg(i) = '1' then
- sys_gpo_0(i) <= gpio_0_dout_reg(i);
- end if;
- end loop;
- end process;
-
-------------------------------------------------------------------
-gpio_0_in:
+led_out:
process(CLK_I)
begin
if rising_edge(CLK_I) then
- for i in 0 to 31 loop
- if gpio_0_dir_reg(i) = '1' then
- gpio_0_din_reg(i) <= gpio_0_dout_reg(i);
- else
- gpio_0_din_reg(i) <= sys_gpi_0(i);
- end if;
- end loop;
+ sys_gpo0 <= gpo0_reg;
+ sys_gpo1 <= gpo1_reg;
+ end if;
+ end process;
+
+------------------------------------------------------------------
+btn_ps2_in:
+ process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ gpi0_reg <= sys_gpi0;
+ gpi1_reg <= sys_gpi1;
end if;
end process;
-
------------------------------------------------------------------
registers_write:
process(CLK_I)
@@ -117,19 +106,41 @@ registers_write:
timer_cmp_we <= (others => '0');
timer_irq_ack <= (others => '0');
if RST_I = '1' then
- gpio_0_dout_reg <= (others => '0');
- gpio_0_dir_reg <= (others => '0');
- timer_en <= (others => '0');
- timer_inten <= (others => '0');
+ gpo0_reg <= (others => '0');
+ gpo1_reg <= (others => '0');
+ timer_en <= (others => '0');
+ timer_inten <= (others => '0');
elsif (STB_I and CYC_I and WE_I) = '1' then
reg_data_wr <= DAT_I;
case ADDR_I(6 downto 2) is
when "00000" =>
- gpio_0_dout_reg <= DAT_I;
+ if SEL_I(0) = '1' then
+ gpo0_reg(7 downto 0) <= DAT_I(7 downto 0);
+ end if;
+ if SEL_I(1) = '1' then
+ gpo0_reg(15 downto 8) <= DAT_I(15 downto 8);
+ end if;
+ if SEL_I(2) = '1' then
+ gpo0_reg(23 downto 16) <= DAT_I(23 downto 16);
+ end if;
+ if SEL_I(3) = '1' then
+ gpo0_reg(31 downto 24) <= DAT_I(31 downto 24);
+ end if;
when "00001" =>
- gpio_0_dir_reg <= DAT_I;
+ if SEL_I(0) = '1' then
+ gpo1_reg(7 downto 0) <= DAT_I(7 downto 0);
+ end if;
+ if SEL_I(1) = '1' then
+ gpo1_reg(15 downto 8) <= DAT_I(15 downto 8);
+ end if;
+ if SEL_I(2) = '1' then
+ gpo1_reg(23 downto 16) <= DAT_I(23 downto 16);
+ end if;
+ if SEL_I(3) = '1' then
+ gpo1_reg(31 downto 24) <= DAT_I(31 downto 24);
+ end if;
when "00010" =>
cnt_usec_we <= '1';
@@ -176,10 +187,10 @@ registers_read:
case ADDR_I(6 downto 2) is
when "00000" =>
- DAT_O <= gpio_0_din_reg;
+ DAT_O <= gpi0_reg;
when "00001" =>
- DAT_O <= gpio_0_dir_reg;
+ DAT_O <= gpi1_reg;
when "00010" =>
DAT_O <= cnt_usec;
@@ -240,7 +251,7 @@ cnt_usec_clock:
if cnt_usec_we = '1' then
cnt_usec <= reg_data_wr;
elsif cnt_usec_en = '1' then
- if to_01(cnt_usec) >= to_unsigned(1E6 - 1, 32) then
+ if cnt_usec >= to_unsigned(1E6 - 1, 32) then
cnt_usec <= (others => '0');
cnt_sec_en <= '1';
else
@@ -277,7 +288,7 @@ proc_int_timer:
elsif timer_cnt_we(i) = '1' then
timer_cnt(i) <= reg_data_wr;
elsif timer_en(i) = '1' then
- if to_01(timer_cnt(i)) >= timer_cmp(i) then
+ if timer_cnt(i) >= timer_cmp(i) then
timer_cnt(i) <= (others => '0');
if timer_inten(i) = '1' then
if timer_irq(i) = '1' then
diff --git a/lib/misc/lcd_port.vhd b/lib/misc/lcd_port.vhd
deleted file mode 100644
index 11f97eb..0000000
--- a/lib/misc/lcd_port.vhd
+++ /dev/null
@@ -1,69 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
- ------------------------------------------------------------------
-entity lcd_port is
- Port (
- rst : in std_logic;
- clk : in std_logic;
- we : in std_logic;
- din : in unsigned(7 downto 0);
- dout : out unsigned(7 downto 0);
- lcd_d : inout unsigned(3 downto 0);
- lcd_e : out std_logic;
- lcd_rs : out std_logic;
- lcd_rw : out std_logic
- );
- end lcd_port;
-
-architecture Behavioral of lcd_port is
-
- constant clcd_e : integer := 7;
- constant clcd_rs : integer := 6;
- constant clcd_rw : integer := 5;
-
- type lcd_t is record
- d : unsigned(3 downto 0);
- e : std_logic;
- rs : std_logic;
- rw : std_logic;
- end record;
-
- ------------------------------------------------------------------
- begin
-
- proc_lcd_port:
- process(rst, clk)
- variable vlcd : lcd_t;
- begin
- if (rst = '1') then
- dout <= (others => '0');
- vlcd.d := (others => '0');
- vlcd.e := '0';
- vlcd.rw := '1';
- vlcd.rs := '0';
- elsif rising_edge(clk) then
- dout <= unsigned("0000" & lcd_d);
- if we = '1' then
- vlcd.d := din(3 downto 0);
- vlcd.e := din(clcd_e);
- vlcd.rs := din(clcd_rs);
- vlcd.rw := din(clcd_rw);
- end if;
- end if;
- if vlcd.rw = '0' then
- lcd_d <= unsigned(vlcd.d);
- else
- lcd_d <= (others => 'Z');
- end if;
- lcd_e <= vlcd.e;
- lcd_rs <= vlcd.rs;
- lcd_rw <= vlcd.rw;
- end process;
- ------------------------------------------------------------------
-
-end Behavioral;
diff --git a/lib/misc/mult_signed.vhd b/lib/misc/mult_signed.vhd
deleted file mode 100644
index 7740b37..0000000
--- a/lib/misc/mult_signed.vhd
+++ /dev/null
@@ -1,62 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-USE ieee.numeric_std.all;
-
-entity signed_mult is
-generic
-(
- latency : natural := 2;
- data_width : natural := 16
-);
-port
-(
- clk : in std_logic;
- ce : in std_logic;
- a : in signed (data_width-1 downto 0);
- b : in signed (data_width-1 downto 0);
- result : out signed (2*data_width-1 downto 0)
-);
-end signed_mult;
-
-architecture rtl of signed_mult is
-
- constant in_latency : natural := latency - 1;
- constant out_latency : natural := latency - in_latency;
-
- subtype in_t is signed (data_width-1 downto 0);
- subtype out_t is signed (2*data_width-1 downto 0);
- type in_pipe_t is array (in_latency downto 1) of in_t;
- type out_pipe_t is array (out_latency downto 1) of out_t;
-
- signal a_pipe : in_pipe_t;
- signal b_pipe : in_pipe_t;
- signal out_pipe : out_pipe_t;
-
-begin
-
- result <= out_pipe(out_latency);
-
-input_pipe_reg:
- process(clk)
- begin
- if rising_edge(clk) then
- if ce = '1' then
- a_pipe <= a_pipe(in_latency-1 downto 1) & a;
- b_pipe <= b_pipe(in_latency-1 downto 1) & b;
- end if;
- end if;
- end process;
-
-mult_pipe_reg:
- process (clk)
- variable res : out_t;
- begin
- if rising_edge(clk) then
- res := a_pipe(in_latency) * b_pipe(in_latency);
- if ce = '1' then
- out_pipe <= out_pipe(out_latency-1 downto 1) & res;
- end if;
- end if;
- end process;
-
-end rtl;
diff --git a/lib/misc/oneshot.vhd b/lib/misc/oneshot.vhd
deleted file mode 100644
index 2f5d8bd..0000000
--- a/lib/misc/oneshot.vhd
+++ /dev/null
@@ -1,223 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 21:52:19 10/22/05
--- Design Name:
--- Module Name: oneshot - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
--- Component Template
---
--- COMPONENT oneshot
--- GENERIC (mode : integer);
--- PORT(
--- rst : IN std_logic;
--- clk : IN std_logic;
--- input : IN std_logic;
--- output : OUT std_logic
--- );
--- END COMPONENT;
---
--- Instantation Template
---
--- oneshot_int: oneshot
--- GENERIC MAP (
--- mode => 1)
--- PORT MAP(
--- rst => ,
--- clk => ,
--- input => ,
--- output =>
--- );
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity oneshot is
- Generic ( mode : integer range 0 to 2 := 1);
- Port ( rst : in std_logic;
- clk : in std_logic;
- input : in std_logic;
- output : out std_logic);
-end oneshot;
-
-architecture Behavioral of oneshot is
-
-type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
-
-signal shot_cs : shot_state_t;
-signal shot_ns : shot_state_t;
-
-begin
-
-mode_0:
-if mode = 0 generate
-begin
- shot_clk: process(rst, clk, shot_ns, input)
- begin
- if (rst = '1') then
- if (input = '1') then
- shot_cs <= release_pos_st;
- else
- shot_cs <= release_neg_st;
- end if;
- else
- if rising_edge(clk) then
- shot_cs <= shot_ns;
- end if;
- end if;
- end process;
-
- shot_in: process(rst, clk, input, shot_cs)
- begin
- shot_ns <= shot_cs;
- case shot_cs is
- when release_pos_st =>
- if (input = '0') then
- shot_ns <= shot_neg_st;
- end if;
- when shot_neg_st =>
- shot_ns <= release_neg_st;
- when release_neg_st =>
- if (input = '1') then
- shot_ns <= release_pos_st;
- end if;
- when others => null;
- end case;
- end process;
-
- shot_out: process(shot_cs)
- begin
- output <= '0';
- case shot_cs is
- when shot_pos_st =>
- output <= '1';
- when shot_neg_st =>
- output <= '1';
- when others => null;
- end case;
- end process;
-end generate;
-
-mode_1:
-if mode = 1 generate
-begin
- shot_clk: process(rst, clk, shot_ns, input)
- begin
- if (rst = '1') then
- if (input = '1') then
- shot_cs <= release_pos_st;
- else
- shot_cs <= release_neg_st;
- end if;
- else
- if rising_edge(clk) then
- shot_cs <= shot_ns;
- end if;
- end if;
- end process;
-
- shot_in: process(rst, clk, input, shot_cs)
- begin
- shot_ns <= shot_cs;
- case shot_cs is
- when shot_pos_st =>
- shot_ns <= release_pos_st;
- when release_pos_st =>
- if (input = '0') then
- shot_ns <= release_neg_st;
- end if;
- when release_neg_st =>
- if (input = '1') then
- shot_ns <= shot_pos_st;
- end if;
- when others => null;
- end case;
- end process;
-
- shot_out: process(shot_cs)
- begin
- output <= '0';
- case shot_cs is
- when shot_pos_st =>
- output <= '1';
- when shot_neg_st =>
- output <= '1';
- when others => null;
- end case;
- end process;
-end generate;
-
-mode_2:
-if mode = 2 generate
-begin
- shot_clk: process(rst, clk, shot_ns, input)
- begin
- if (rst = '1') then
- if (input = '1') then
- shot_cs <= release_pos_st;
- else
- shot_cs <= release_neg_st;
- end if;
- else
- if rising_edge(clk) then
- shot_cs <= shot_ns;
- end if;
- end if;
- end process;
-
- shot_in: process(rst, clk, input, shot_cs)
- begin
- shot_ns <= shot_cs;
- case shot_cs is
- when shot_pos_st =>
- shot_ns <= release_pos_st;
- when release_pos_st =>
- if (input = '0') then
- shot_ns <= shot_neg_st;
- end if;
- when shot_neg_st =>
- shot_ns <= release_neg_st;
- when release_neg_st =>
- if (input = '1') then
- shot_ns <= shot_pos_st;
- end if;
- end case;
- end process;
-
- shot_out: process(shot_cs)
- begin
- output <= '0';
- case shot_cs is
- when shot_pos_st =>
- output <= '1';
- when shot_neg_st =>
- output <= '1';
- when others => null;
- end case;
- end process;
-end generate;
-
-
-
-end Behavioral;
diff --git a/lib/misc/pkg_template.vhd b/lib/misc/pkg_template.vhd
deleted file mode 100644
index fe866e8..0000000
--- a/lib/misc/pkg_template.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package template_pkg is
- -- Constants
- -- Types
- -- Functions
-
-end template_pkg;
-
-package body template_pkg is
-
-end template_pkg;
-
diff --git a/lib/misc/ram_sim.vhd b/lib/misc/ram_sim.vhd
deleted file mode 100644
index 6d26672..0000000
--- a/lib/misc/ram_sim.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-ENTITY ram IS
- Generic
- (
- word_addr_width : integer := 6
- );
- Port
- (
- clk : in STD_LOGIC;
- ce : in STD_LOGIC;
- we : in unsigned(3 downto 0);
- addr : in unsigned(31 downto 0);
- din : in unsigned(31 downto 0);
- dout : out unsigned(31 downto 0)
- );
-END ram;
-
-ARCHITECTURE behavior OF ram IS
-
- constant depth : natural := 2**word_addr_width;
-
- type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
-
- function sram_clear return sram_t is
-
- variable result : sram_t;
- begin
- for i in 0 to sram_t'length-1 loop
- result(i) := (others => '0');
- end loop;
- return result;
- end sram_clear;
-
- signal sram : sram_t := sram_clear;
-
-BEGIN
-
-
-SRAM_RW:
- process(clk)
- variable index : natural range 0 to depth-1;
- begin
- if rising_edge(clk) and ce = '1' then
- index := to_integer(addr(word_addr_width+1 downto 2));
- if we(0) = '1' then
- sram(index)(7 downto 0) <= din(7 downto 0);
- end if;
- if we(1) = '1' then
- sram(index)(15 downto 8) <= din(15 downto 8);
- end if;
- if we(2) = '1' then
- sram(index)(23 downto 16) <= din(23 downto 16);
- end if;
- if we(3) = '1' then
- sram(index)(31 downto 24) <= din(31 downto 24);
- end if;
- dout <= sram(index);
- end if;
- end process;
-
-end behavior;
diff --git a/lib/misc/ram_wb.vhd b/lib/misc/ram_wb.vhd
deleted file mode 100644
index 2ebf242..0000000
--- a/lib/misc/ram_wb.vhd
+++ /dev/null
@@ -1,80 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY ram_wb IS
- Port
- (
- CLK_I : in STD_LOGIC;
- RST_I : in STD_LOGIC;
- CYC_I : in STD_LOGIC;
- STB_I : in STD_LOGIC;
- SEL_I : in unsigned(3 downto 0);
- WE_I : in STD_LOGIC;
- ACK_O : out STD_LOGIC;
- SRDY_O : out STD_LOGIC;
- MRDY_I : in STD_LOGIC;
- ADDR_I : in unsigned(31 downto 0);
- DAT_I : in unsigned(31 downto 0);
- DAT_O : out unsigned(31 downto 0)
- );
-END ram_wb;
-
-ARCHITECTURE behavior OF ram_wb IS
-
- COMPONENT ram
- GENERIC
- (
- word_addr_width : integer
- );
- PORT
- (
- clk : in STD_LOGIC;
- ce : in STD_LOGIC;
- we : in unsigned(3 downto 0);
- addr : in unsigned(31 downto 0);
- din : in unsigned(31 downto 0);
- dout : out unsigned(31 downto 0)
- );
- END COMPONENT;
-
- signal data_en : std_logic;
- signal we : unsigned(3 downto 0);
-
-begin
-
- we <= SEL_I and (3 downto 0 => WE_I);
-
- data_en <= CYC_I and STB_I and MRDY_I;
- SRDY_O <= CYC_I;
-
-data_valid_register:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- ACK_O <= '0';
- else
- ACK_O <= data_en and not WE_I;
- end if;
- end if;
- end process;
-
-inst_ram : ram
- GENERIC MAP
- (
- word_addr_width => 6
- )
- PORT MAP
- (
- clk => CLK_I,
- ce => data_en,
- we => we,
- addr => ADDR_I,
- din => DAT_I,
- dout => DAT_O
- );
-
-
-
-end behavior;
diff --git a/lib/misc/rom_sim.vhd b/lib/misc/rom_sim.vhd
deleted file mode 100644
index 98c0484..0000000
--- a/lib/misc/rom_sim.vhd
+++ /dev/null
@@ -1,2082 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY rom IS
- Port
- (
- clk : in STD_LOGIC;
- ce : in STD_LOGIC;
- addr : in unsigned(31 downto 0);
- dout : out unsigned(31 downto 0)
- );
-END rom;
-
-ARCHITECTURE data OF rom IS
-
- subtype word_t is unsigned(31 downto 0);
- type word_array_t is array (0 to 2047) of word_t;
- constant word_array : word_array_t :=
- (
-
- X"3C1A1040", -- 00000000
- X"375A000C", -- 00000004
- X"409A6000", -- 00000008
- X"241A0000", -- 0000000C
- X"409A6800", -- 00000010
- X"401A7800", -- 00000014
- X"00000000", -- 00000018
- X"409AF800", -- 0000001C
- X"3C1ABFC0", -- 00000020
- X"275A01C4", -- 00000024
- X"03400008", -- 00000028
- X"00000000", -- 0000002C
- X"00000000", -- 00000030
- X"00000000", -- 00000034
- X"00000000", -- 00000038
- X"00000000", -- 0000003C
- X"00000000", -- 00000040
- X"00000000", -- 00000044
- X"00000000", -- 00000048
- X"00000000", -- 0000004C
- X"00000000", -- 00000050
- X"00000000", -- 00000054
- X"00000000", -- 00000058
- X"00000000", -- 0000005C
- X"00000000", -- 00000060
- X"00000000", -- 00000064
- X"00000000", -- 00000068
- X"00000000", -- 0000006C
- X"00000000", -- 00000070
- X"00000000", -- 00000074
- X"00000000", -- 00000078
- X"00000000", -- 0000007C
- X"00000000", -- 00000080
- X"00000000", -- 00000084
- X"00000000", -- 00000088
- X"00000000", -- 0000008C
- X"00000000", -- 00000090
- X"00000000", -- 00000094
- X"00000000", -- 00000098
- X"00000000", -- 0000009C
- X"00000000", -- 000000A0
- X"00000000", -- 000000A4
- X"00000000", -- 000000A8
- X"00000000", -- 000000AC
- X"00000000", -- 000000B0
- X"00000000", -- 000000B4
- X"00000000", -- 000000B8
- X"00000000", -- 000000BC
- X"00000000", -- 000000C0
- X"00000000", -- 000000C4
- X"00000000", -- 000000C8
- X"00000000", -- 000000CC
- X"00000000", -- 000000D0
- X"00000000", -- 000000D4
- X"00000000", -- 000000D8
- X"00000000", -- 000000DC
- X"00000000", -- 000000E0
- X"00000000", -- 000000E4
- X"00000000", -- 000000E8
- X"00000000", -- 000000EC
- X"00000000", -- 000000F0
- X"00000000", -- 000000F4
- X"00000000", -- 000000F8
- X"00000000", -- 000000FC
- X"00000000", -- 00000100
- X"00000000", -- 00000104
- X"00000000", -- 00000108
- X"00000000", -- 0000010C
- X"00000000", -- 00000110
- X"00000000", -- 00000114
- X"00000000", -- 00000118
- X"00000000", -- 0000011C
- X"00000000", -- 00000120
- X"00000000", -- 00000124
- X"00000000", -- 00000128
- X"00000000", -- 0000012C
- X"00000000", -- 00000130
- X"00000000", -- 00000134
- X"00000000", -- 00000138
- X"00000000", -- 0000013C
- X"00000000", -- 00000140
- X"00000000", -- 00000144
- X"00000000", -- 00000148
- X"00000000", -- 0000014C
- X"00000000", -- 00000150
- X"00000000", -- 00000154
- X"00000000", -- 00000158
- X"00000000", -- 0000015C
- X"00000000", -- 00000160
- X"00000000", -- 00000164
- X"00000000", -- 00000168
- X"00000000", -- 0000016C
- X"00000000", -- 00000170
- X"00000000", -- 00000174
- X"00000000", -- 00000178
- X"00000000", -- 0000017C
- X"401A6800", -- 00000180
- X"3C1BA000", -- 00000184
- X"277B0000", -- 00000188
- X"001AD082", -- 0000018C
- X"335A000F", -- 00000190
- X"035BD025", -- 00000194
- X"AF7A0000", -- 00000198
- X"401A6800", -- 0000019C
- X"00000000", -- 000001A0
- X"001AD202", -- 000001A4
- X"335A00FF", -- 000001A8
- X"1740FFFB", -- 000001AC
- X"00000000", -- 000001B0
- X"401A7000", -- 000001B4
- X"00000000", -- 000001B8
- X"03400008", -- 000001BC
- X"42000010", -- 000001C0
- X"3C1AA001", -- 000001C4
- X"275A0008", -- 000001C8
- X"241B000D", -- 000001CC
- X"A35B0000", -- 000001D0
- X"3C1DBFD0", -- 000001D4
- X"27BDFFF0", -- 000001D8
- X"241A0005", -- 000001DC
- X"1340009F", -- 000001E0
- X"241AFFFB", -- 000001E4
- X"1340009D", -- 000001E8
- X"241A0000", -- 000001EC
- X"13400003", -- 000001F0
- X"00000000", -- 000001F4
- X"0BF00118", -- 000001F8
- X"00000000", -- 000001FC
- X"241A0005", -- 00000200
- X"241B0006", -- 00000204
- X"135B0095", -- 00000208
- X"241AFFFB", -- 0000020C
- X"135B0093", -- 00000210
- X"241A0000", -- 00000214
- X"135B0091", -- 00000218
- X"241A0006", -- 0000021C
- X"135B0003", -- 00000220
- X"00000000", -- 00000224
- X"0BF00118", -- 00000228
- X"00000000", -- 0000022C
- X"241AFFFB", -- 00000230
- X"0741008A", -- 00000234
- X"241A0005", -- 00000238
- X"07410002", -- 0000023C
- X"00000000", -- 00000240
- X"0BF00118", -- 00000244
- X"241A0000", -- 00000248
- X"07410002", -- 0000024C
- X"00000000", -- 00000250
- X"0BF00118", -- 00000254
- X"241AFFFB", -- 00000258
- X"1F400080", -- 0000025C
- X"241A0000", -- 00000260
- X"1F40007E", -- 00000264
- X"241A0005", -- 00000268
- X"1F400002", -- 0000026C
- X"00000000", -- 00000270
- X"0BF00118", -- 00000274
- X"241A0005", -- 00000278
- X"1B400078", -- 0000027C
- X"241A0000", -- 00000280
- X"1B400002", -- 00000284
- X"00000000", -- 00000288
- X"0BF00118", -- 0000028C
- X"241AFFFB", -- 00000290
- X"1B400002", -- 00000294
- X"00000000", -- 00000298
- X"0BF00118", -- 0000029C
- X"241A0005", -- 000002A0
- X"0740006E", -- 000002A4
- X"241A0000", -- 000002A8
- X"0740006C", -- 000002AC
- X"241AFFFB", -- 000002B0
- X"07400002", -- 000002B4
- X"00000000", -- 000002B8
- X"0BF00118", -- 000002BC
- X"241A0005", -- 000002C0
- X"241B0006", -- 000002C4
- X"175B0002", -- 000002C8
- X"00000000", -- 000002CC
- X"0BF00118", -- 000002D0
- X"241AFFFB", -- 000002D4
- X"175B0002", -- 000002D8
- X"00000000", -- 000002DC
- X"0BF00118", -- 000002E0
- X"241AFFFA", -- 000002E4
- X"175B0002", -- 000002E8
- X"00000000", -- 000002EC
- X"0BF00118", -- 000002F0
- X"241A0000", -- 000002F4
- X"175B0002", -- 000002F8
- X"00000000", -- 000002FC
- X"0BF00118", -- 00000300
- X"241A0006", -- 00000304
- X"175B0055", -- 00000308
- X"241A0005", -- 0000030C
- X"17400002", -- 00000310
- X"00000000", -- 00000314
- X"0BF00118", -- 00000318
- X"241AFFFB", -- 0000031C
- X"17400002", -- 00000320
- X"00000000", -- 00000324
- X"0BF00118", -- 00000328
- X"241A0000", -- 0000032C
- X"1740004B", -- 00000330
- X"241B0005", -- 00000334
- X"2F7A0006", -- 00000338
- X"2F7AFFFA", -- 0000033C
- X"241BFFFB", -- 00000340
- X"2F7A0006", -- 00000344
- X"2F7AFFFA", -- 00000348
- X"241B0006", -- 0000034C
- X"2F7A0005", -- 00000350
- X"2F7AFFFB", -- 00000354
- X"241BFFFA", -- 00000358
- X"2F7A0005", -- 0000035C
- X"2F7AFFFB", -- 00000360
- X"241B0005", -- 00000364
- X"2B7A0006", -- 00000368
- X"2B7AFFFA", -- 0000036C
- X"241BFFFB", -- 00000370
- X"2B7A0006", -- 00000374
- X"2B7AFFFA", -- 00000378
- X"241B0006", -- 0000037C
- X"2B7A0005", -- 00000380
- X"2B7AFFFB", -- 00000384
- X"241BFFFA", -- 00000388
- X"2B7A0005", -- 0000038C
- X"2B7AFFFB", -- 00000390
- X"241A0005", -- 00000394
- X"241B0006", -- 00000398
- X"035BD02B", -- 0000039C
- X"241A0005", -- 000003A0
- X"241BFFFA", -- 000003A4
- X"035BD02B", -- 000003A8
- X"241AFFFB", -- 000003AC
- X"241B0006", -- 000003B0
- X"035BD02B", -- 000003B4
- X"241AFFFB", -- 000003B8
- X"241BFFFA", -- 000003BC
- X"035BD02B", -- 000003C0
- X"241A0006", -- 000003C4
- X"241B0005", -- 000003C8
- X"035BD02B", -- 000003CC
- X"241A0006", -- 000003D0
- X"241BFFFB", -- 000003D4
- X"035BD02B", -- 000003D8
- X"241AFFFA", -- 000003DC
- X"241B0005", -- 000003E0
- X"035BD02B", -- 000003E4
- X"241AFFFA", -- 000003E8
- X"241BFFFB", -- 000003EC
- X"035BD02B", -- 000003F0
- X"241A0005", -- 000003F4
- X"241B0006", -- 000003F8
- X"035BD02A", -- 000003FC
- X"241A0005", -- 00000400
- X"241BFFFA", -- 00000404
- X"035BD02A", -- 00000408
- X"241AFFFB", -- 0000040C
- X"241B0006", -- 00000410
- X"035BD02A", -- 00000414
- X"241AFFFB", -- 00000418
- X"241BFFFA", -- 0000041C
- X"035BD02A", -- 00000420
- X"241A0006", -- 00000424
- X"241B0005", -- 00000428
- X"035BD02A", -- 0000042C
- X"241A0006", -- 00000430
- X"241BFFFB", -- 00000434
- X"035BD02A", -- 00000438
- X"241AFFFA", -- 0000043C
- X"241B0005", -- 00000440
- X"035BD02A", -- 00000444
- X"241AFFFA", -- 00000448
- X"241BFFFB", -- 0000044C
- X"035BD02A", -- 00000450
- X"3C1ABFC0", -- 00000454
- X"275A0F2C", -- 00000458
- X"0340F809", -- 0000045C
- X"00000000", -- 00000460
- X"0BF00118", -- 00000464
- X"00000000", -- 00000468
- X"27BDFFF0", -- 0000046C
- X"AFBE000C", -- 00000470
- X"03A0F021", -- 00000474
- X"40026000", -- 00000478
- X"03C0E821", -- 0000047C
- X"8FBE000C", -- 00000480
- X"03E00008", -- 00000484
- X"27BD0010", -- 00000488
- X"27BDFFF0", -- 0000048C
- X"AFBE000C", -- 00000490
- X"03A0F021", -- 00000494
- X"40027800", -- 00000498
- X"03C0E821", -- 0000049C
- X"8FBE000C", -- 000004A0
- X"03E00008", -- 000004A4
- X"27BD0010", -- 000004A8
- X"27BDFFF0", -- 000004AC
- X"AFBE000C", -- 000004B0
- X"03A0F021", -- 000004B4
- X"3C02A001", -- 000004B8
- X"34420004", -- 000004BC
- X"AFC20004", -- 000004C0
- X"3C02A001", -- 000004C4
- X"AFC20000", -- 000004C8
- X"8FC20004", -- 000004CC
- X"00000000", -- 000004D0
- X"8C420000", -- 000004D4
- X"00000000", -- 000004D8
- X"30420010", -- 000004DC
- X"1040FFFA", -- 000004E0
- X"00000000", -- 000004E4
- X"8FC20000", -- 000004E8
- X"00000000", -- 000004EC
- X"8C420000", -- 000004F0
- X"00000000", -- 000004F4
- X"00021600", -- 000004F8
- X"00021603", -- 000004FC
- X"03C0E821", -- 00000500
- X"8FBE000C", -- 00000504
- X"27BD0010", -- 00000508
- X"03E00008", -- 0000050C
- X"00000000", -- 00000510
- X"27BDFFE8", -- 00000514
- X"AFBE0014", -- 00000518
- X"03A0F021", -- 0000051C
- X"00801021", -- 00000520
- X"A3C20008", -- 00000524
- X"3C02A001", -- 00000528
- X"34420004", -- 0000052C
- X"AFC20004", -- 00000530
- X"3C02A001", -- 00000534
- X"AFC20000", -- 00000538
- X"8FC20004", -- 0000053C
- X"00000000", -- 00000540
- X"8C420000", -- 00000544
- X"00000000", -- 00000548
- X"30420002", -- 0000054C
- X"1440FFFA", -- 00000550
- X"00000000", -- 00000554
- X"83C30008", -- 00000558
- X"8FC20000", -- 0000055C
- X"00000000", -- 00000560
- X"AC430000", -- 00000564
- X"03C0E821", -- 00000568
- X"8FBE0014", -- 0000056C
- X"27BD0018", -- 00000570
- X"03E00008", -- 00000574
- X"00000000", -- 00000578
- X"27BDFFF0", -- 0000057C
- X"AFBF000C", -- 00000580
- X"AFBE0008", -- 00000584
- X"03A0F021", -- 00000588
- X"00801021", -- 0000058C
- X"A3C20000", -- 00000590
- X"83C30000", -- 00000594
- X"2402000A", -- 00000598
- X"1462000B", -- 0000059C
- X"00000000", -- 000005A0
- X"2404000D", -- 000005A4
- X"0FF00145", -- 000005A8
- X"00000000", -- 000005AC
- X"83C20000", -- 000005B0
- X"00000000", -- 000005B4
- X"00402021", -- 000005B8
- X"0FF00145", -- 000005BC
- X"00000000", -- 000005C0
- X"0BF00178", -- 000005C4
- X"00000000", -- 000005C8
- X"83C20000", -- 000005CC
- X"00000000", -- 000005D0
- X"00402021", -- 000005D4
- X"0FF00145", -- 000005D8
- X"00000000", -- 000005DC
- X"03C0E821", -- 000005E0
- X"8FBF000C", -- 000005E4
- X"8FBE0008", -- 000005E8
- X"27BD0010", -- 000005EC
- X"03E00008", -- 000005F0
- X"00000000", -- 000005F4
- X"27BDFFE8", -- 000005F8
- X"AFBF0014", -- 000005FC
- X"AFBE0010", -- 00000600
- X"03A0F021", -- 00000604
- X"AFC40008", -- 00000608
- X"8FC20008", -- 0000060C
- X"00000000", -- 00000610
- X"AFC20000", -- 00000614
- X"0BF00194", -- 00000618
- X"00000000", -- 0000061C
- X"8FC20008", -- 00000620
- X"00000000", -- 00000624
- X"80420000", -- 00000628
- X"00000000", -- 0000062C
- X"00401821", -- 00000630
- X"8FC20008", -- 00000634
- X"00000000", -- 00000638
- X"24420001", -- 0000063C
- X"AFC20008", -- 00000640
- X"00602021", -- 00000644
- X"0FF0015F", -- 00000648
- X"00000000", -- 0000064C
- X"8FC20008", -- 00000650
- X"00000000", -- 00000654
- X"80420000", -- 00000658
- X"00000000", -- 0000065C
- X"1440FFEF", -- 00000660
- X"00000000", -- 00000664
- X"8FC30008", -- 00000668
- X"8FC20000", -- 0000066C
- X"00000000", -- 00000670
- X"00621023", -- 00000674
- X"03C0E821", -- 00000678
- X"8FBF0014", -- 0000067C
- X"8FBE0010", -- 00000680
- X"27BD0018", -- 00000684
- X"03E00008", -- 00000688
- X"00000000", -- 0000068C
- X"27BDFFE8", -- 00000690
- X"AFBF0014", -- 00000694
- X"AFBE0010", -- 00000698
- X"03A0F021", -- 0000069C
- X"00801021", -- 000006A0
- X"A3C20008", -- 000006A4
- X"AFC00004", -- 000006A8
- X"0BF001CD", -- 000006AC
- X"00000000", -- 000006B0
- X"93C20008", -- 000006B4
- X"00000000", -- 000006B8
- X"00021102", -- 000006BC
- X"A3C20000", -- 000006C0
- X"83C20008", -- 000006C4
- X"00000000", -- 000006C8
- X"00021100", -- 000006CC
- X"A3C20008", -- 000006D0
- X"93C20000", -- 000006D4
- X"00000000", -- 000006D8
- X"2C42000A", -- 000006DC
- X"10400007", -- 000006E0
- X"00000000", -- 000006E4
- X"93C20000", -- 000006E8
- X"00000000", -- 000006EC
- X"24420030", -- 000006F0
- X"A3C20001", -- 000006F4
- X"0BF001C4", -- 000006F8
- X"00000000", -- 000006FC
- X"93C20000", -- 00000700
- X"00000000", -- 00000704
- X"24420037", -- 00000708
- X"A3C20001", -- 0000070C
- X"83C20001", -- 00000710
- X"00000000", -- 00000714
- X"00402021", -- 00000718
- X"0FF00145", -- 0000071C
- X"00000000", -- 00000720
- X"8FC20004", -- 00000724
- X"00000000", -- 00000728
- X"24420001", -- 0000072C
- X"AFC20004", -- 00000730
- X"8FC20004", -- 00000734
- X"00000000", -- 00000738
- X"28420002", -- 0000073C
- X"1440FFDC", -- 00000740
- X"00000000", -- 00000744
- X"03C0E821", -- 00000748
- X"8FBF0014", -- 0000074C
- X"8FBE0010", -- 00000750
- X"27BD0018", -- 00000754
- X"03E00008", -- 00000758
- X"00000000", -- 0000075C
- X"27BDFFE8", -- 00000760
- X"AFBF0014", -- 00000764
- X"AFBE0010", -- 00000768
- X"03A0F021", -- 0000076C
- X"AFC40008", -- 00000770
- X"AFC00004", -- 00000774
- X"0BF001F1", -- 00000778
- X"00000000", -- 0000077C
- X"8FC20008", -- 00000780
- X"00000000", -- 00000784
- X"00021603", -- 00000788
- X"A3C20001", -- 0000078C
- X"83C20001", -- 00000790
- X"00000000", -- 00000794
- X"00402021", -- 00000798
- X"0FF001A4", -- 0000079C
- X"00000000", -- 000007A0
- X"8FC20008", -- 000007A4
- X"00000000", -- 000007A8
- X"00021200", -- 000007AC
- X"AFC20008", -- 000007B0
- X"8FC20004", -- 000007B4
- X"00000000", -- 000007B8
- X"24420001", -- 000007BC
- X"AFC20004", -- 000007C0
- X"8FC20004", -- 000007C4
- X"00000000", -- 000007C8
- X"28420004", -- 000007CC
- X"1440FFEB", -- 000007D0
- X"00000000", -- 000007D4
- X"03C0E821", -- 000007D8
- X"8FBF0014", -- 000007DC
- X"8FBE0010", -- 000007E0
- X"27BD0018", -- 000007E4
- X"03E00008", -- 000007E8
- X"00000000", -- 000007EC
- X"27BDFFE8", -- 000007F0
- X"AFBE0014", -- 000007F4
- X"03A0F021", -- 000007F8
- X"AFC40008", -- 000007FC
- X"A3C00000", -- 00000800
- X"AFC00004", -- 00000804
- X"0BF00229", -- 00000808
- X"00000000", -- 0000080C
- X"8FC30004", -- 00000810
- X"8FC20008", -- 00000814
- X"00000000", -- 00000818
- X"00431021", -- 0000081C
- X"90420000", -- 00000820
- X"00000000", -- 00000824
- X"A3C20001", -- 00000828
- X"93C20001", -- 0000082C
- X"00000000", -- 00000830
- X"2C420041", -- 00000834
- X"14400007", -- 00000838
- X"00000000", -- 0000083C
- X"93C20001", -- 00000840
- X"00000000", -- 00000844
- X"2442FFC9", -- 00000848
- X"A3C20001", -- 0000084C
- X"0BF0021A", -- 00000850
- X"00000000", -- 00000854
- X"93C20001", -- 00000858
- X"00000000", -- 0000085C
- X"2442FFD0", -- 00000860
- X"A3C20001", -- 00000864
- X"93C20000", -- 00000868
- X"00000000", -- 0000086C
- X"00021100", -- 00000870
- X"00021E00", -- 00000874
- X"00031E03", -- 00000878
- X"83C20001", -- 0000087C
- X"00000000", -- 00000880
- X"00621025", -- 00000884
- X"00021600", -- 00000888
- X"00021603", -- 0000088C
- X"A3C20000", -- 00000890
- X"8FC20004", -- 00000894
- X"00000000", -- 00000898
- X"24420001", -- 0000089C
- X"AFC20004", -- 000008A0
- X"8FC20004", -- 000008A4
- X"00000000", -- 000008A8
- X"28420002", -- 000008AC
- X"1440FFD7", -- 000008B0
- X"00000000", -- 000008B4
- X"93C20000", -- 000008B8
- X"03C0E821", -- 000008BC
- X"8FBE0014", -- 000008C0
- X"27BD0018", -- 000008C4
- X"03E00008", -- 000008C8
- X"00000000", -- 000008CC
- X"27BDFFD8", -- 000008D0
- X"AFBF0024", -- 000008D4
- X"AFBE0020", -- 000008D8
- X"03A0F021", -- 000008DC
- X"AFC40010", -- 000008E0
- X"AFC50014", -- 000008E4
- X"AFC60018", -- 000008E8
- X"8FC20018", -- 000008EC
- X"00000000", -- 000008F0
- X"14400004", -- 000008F4
- X"00000000", -- 000008F8
- X"AFC0001C", -- 000008FC
- X"0BF00321", -- 00000900
- X"00000000", -- 00000904
- X"8FC30010", -- 00000908
- X"24020003", -- 0000090C
- X"AC620008", -- 00000910
- X"AFC00004", -- 00000914
- X"8FC20014", -- 00000918
- X"00000000", -- 0000091C
- X"24420001", -- 00000920
- X"90420000", -- 00000924
- X"00000000", -- 00000928
- X"2C420031", -- 0000092C
- X"14400015", -- 00000930
- X"00000000", -- 00000934
- X"8FC20014", -- 00000938
- X"00000000", -- 0000093C
- X"24420001", -- 00000940
- X"90420000", -- 00000944
- X"00000000", -- 00000948
- X"2C420034", -- 0000094C
- X"1040000D", -- 00000950
- X"00000000", -- 00000954
- X"8FC20014", -- 00000958
- X"00000000", -- 0000095C
- X"24420001", -- 00000960
- X"90420000", -- 00000964
- X"00000000", -- 00000968
- X"2442FFD1", -- 0000096C
- X"AFC20004", -- 00000970
- X"8FC30010", -- 00000974
- X"24020002", -- 00000978
- X"AC620008", -- 0000097C
- X"0BF0028C", -- 00000980
- X"00000000", -- 00000984
- X"8FC20014", -- 00000988
- X"00000000", -- 0000098C
- X"24420001", -- 00000990
- X"90420000", -- 00000994
- X"00000000", -- 00000998
- X"2C420037", -- 0000099C
- X"14400017", -- 000009A0
- X"00000000", -- 000009A4
- X"8FC20014", -- 000009A8
- X"00000000", -- 000009AC
- X"24420001", -- 000009B0
- X"90420000", -- 000009B4
- X"00000000", -- 000009B8
- X"2C42003A", -- 000009BC
- X"1040000F", -- 000009C0
- X"00000000", -- 000009C4
- X"8FC20014", -- 000009C8
- X"00000000", -- 000009CC
- X"24420001", -- 000009D0
- X"90420000", -- 000009D4
- X"00000000", -- 000009D8
- X"00401821", -- 000009DC
- X"2402003B", -- 000009E0
- X"00431023", -- 000009E4
- X"AFC20004", -- 000009E8
- X"8FC30010", -- 000009EC
- X"24020004", -- 000009F0
- X"AC620008", -- 000009F4
- X"0BF0028C", -- 000009F8
- X"00000000", -- 000009FC
- X"8FC20014", -- 00000A00
- X"00000000", -- 00000A04
- X"24420001", -- 00000A08
- X"90430000", -- 00000A0C
- X"24020030", -- 00000A10
- X"14620006", -- 00000A14
- X"00000000", -- 00000A18
- X"24020002", -- 00000A1C
- X"AFC20004", -- 00000A20
- X"8FC30010", -- 00000A24
- X"24020001", -- 00000A28
- X"AC620008", -- 00000A2C
- X"8FC20014", -- 00000A30
- X"00000000", -- 00000A34
- X"24420002", -- 00000A38
- X"00402021", -- 00000A3C
- X"0FF001FC", -- 00000A40
- X"00000000", -- 00000A44
- X"A3C20008", -- 00000A48
- X"93C30008", -- 00000A4C
- X"8FC20010", -- 00000A50
- X"00000000", -- 00000A54
- X"AC430004", -- 00000A58
- X"93C20008", -- 00000A5C
- X"00000000", -- 00000A60
- X"A3C20009", -- 00000A64
- X"8FC20010", -- 00000A68
- X"00000000", -- 00000A6C
- X"AC400000", -- 00000A70
- X"AFC00000", -- 00000A74
- X"0BF002C0", -- 00000A78
- X"00000000", -- 00000A7C
- X"8FC20000", -- 00000A80
- X"00000000", -- 00000A84
- X"24420002", -- 00000A88
- X"00021040", -- 00000A8C
- X"00401821", -- 00000A90
- X"8FC20014", -- 00000A94
- X"00000000", -- 00000A98
- X"00431021", -- 00000A9C
- X"00402021", -- 00000AA0
- X"0FF001FC", -- 00000AA4
- X"00000000", -- 00000AA8
- X"A3C20008", -- 00000AAC
- X"8FC20010", -- 00000AB0
- X"00000000", -- 00000AB4
- X"8C420000", -- 00000AB8
- X"00000000", -- 00000ABC
- X"00021A00", -- 00000AC0
- X"93C20008", -- 00000AC4
- X"00000000", -- 00000AC8
- X"00621825", -- 00000ACC
- X"8FC20010", -- 00000AD0
- X"00000000", -- 00000AD4
- X"AC430000", -- 00000AD8
- X"93C30009", -- 00000ADC
- X"93C20008", -- 00000AE0
- X"00000000", -- 00000AE4
- X"00621021", -- 00000AE8
- X"A3C20009", -- 00000AEC
- X"8FC20000", -- 00000AF0
- X"00000000", -- 00000AF4
- X"24420001", -- 00000AF8
- X"AFC20000", -- 00000AFC
- X"8FC20000", -- 00000B00
- X"8FC30004", -- 00000B04
- X"00000000", -- 00000B08
- X"0043102A", -- 00000B0C
- X"1440FFDB", -- 00000B10
- X"00000000", -- 00000B14
- X"8FC20010", -- 00000B18
- X"00000000", -- 00000B1C
- X"8C430004", -- 00000B20
- X"8FC20004", -- 00000B24
- X"00000000", -- 00000B28
- X"00021027", -- 00000B2C
- X"00621821", -- 00000B30
- X"8FC20010", -- 00000B34
- X"00000000", -- 00000B38
- X"AC430004", -- 00000B3C
- X"8FC20004", -- 00000B40
- X"00000000", -- 00000B44
- X"24420002", -- 00000B48
- X"00021040", -- 00000B4C
- X"00401821", -- 00000B50
- X"8FC20014", -- 00000B54
- X"00000000", -- 00000B58
- X"00431821", -- 00000B5C
- X"8FC20010", -- 00000B60
- X"00000000", -- 00000B64
- X"AC43000C", -- 00000B68
- X"AFC00000", -- 00000B6C
- X"0BF002FB", -- 00000B70
- X"00000000", -- 00000B74
- X"8FC20010", -- 00000B78
- X"00000000", -- 00000B7C
- X"8C43000C", -- 00000B80
- X"8FC20000", -- 00000B84
- X"00000000", -- 00000B88
- X"00021040", -- 00000B8C
- X"00621021", -- 00000B90
- X"00402021", -- 00000B94
- X"0FF001FC", -- 00000B98
- X"00000000", -- 00000B9C
- X"A3C20008", -- 00000BA0
- X"8FC20010", -- 00000BA4
- X"00000000", -- 00000BA8
- X"8C43000C", -- 00000BAC
- X"8FC20000", -- 00000BB0
- X"00000000", -- 00000BB4
- X"00621821", -- 00000BB8
- X"93C20008", -- 00000BBC
- X"00000000", -- 00000BC0
- X"A0620000", -- 00000BC4
- X"93C30009", -- 00000BC8
- X"93C20008", -- 00000BCC
- X"00000000", -- 00000BD0
- X"00621021", -- 00000BD4
- X"A3C20009", -- 00000BD8
- X"8FC20000", -- 00000BDC
- X"00000000", -- 00000BE0
- X"24420001", -- 00000BE4
- X"AFC20000", -- 00000BE8
- X"8FC20010", -- 00000BEC
- X"00000000", -- 00000BF0
- X"8C420004", -- 00000BF4
- X"00000000", -- 00000BF8
- X"00401821", -- 00000BFC
- X"8FC20000", -- 00000C00
- X"00000000", -- 00000C04
- X"0043102A", -- 00000C08
- X"1440FFDA", -- 00000C0C
- X"00000000", -- 00000C10
- X"93C20009", -- 00000C14
- X"00000000", -- 00000C18
- X"00021027", -- 00000C1C
- X"A3C20009", -- 00000C20
- X"8FC20010", -- 00000C24
- X"00000000", -- 00000C28
- X"8C43000C", -- 00000C2C
- X"8FC20000", -- 00000C30
- X"00000000", -- 00000C34
- X"00021040", -- 00000C38
- X"00621021", -- 00000C3C
- X"00402021", -- 00000C40
- X"0FF001FC", -- 00000C44
- X"00000000", -- 00000C48
- X"A3C20008", -- 00000C4C
- X"93C30009", -- 00000C50
- X"93C20008", -- 00000C54
- X"00000000", -- 00000C58
- X"10620004", -- 00000C5C
- X"00000000", -- 00000C60
- X"AFC0001C", -- 00000C64
- X"0BF00321", -- 00000C68
- X"00000000", -- 00000C6C
- X"8FC20010", -- 00000C70
- X"00000000", -- 00000C74
- X"8C420008", -- 00000C78
- X"00000000", -- 00000C7C
- X"AFC2001C", -- 00000C80
- X"8FC2001C", -- 00000C84
- X"03C0E821", -- 00000C88
- X"8FBF0024", -- 00000C8C
- X"8FBE0020", -- 00000C90
- X"27BD0028", -- 00000C94
- X"03E00008", -- 00000C98
- X"00000000", -- 00000C9C
- X"27BDFFE8", -- 00000CA0
- X"AFBF0014", -- 00000CA4
- X"AFBE0010", -- 00000CA8
- X"03A0F021", -- 00000CAC
- X"AFC40008", -- 00000CB0
- X"AFC00000", -- 00000CB4
- X"0FF0012B", -- 00000CB8
- X"00000000", -- 00000CBC
- X"A3C20004", -- 00000CC0
- X"83C30004", -- 00000CC4
- X"24020073", -- 00000CC8
- X"10620015", -- 00000CCC
- X"00000000", -- 00000CD0
- X"83C30004", -- 00000CD4
- X"24020053", -- 00000CD8
- X"1462FFF6", -- 00000CDC
- X"00000000", -- 00000CE0
- X"0BF00349", -- 00000CE4
- X"00000000", -- 00000CE8
- X"8FC30000", -- 00000CEC
- X"8FC20008", -- 00000CF0
- X"00000000", -- 00000CF4
- X"00431821", -- 00000CF8
- X"93C20004", -- 00000CFC
- X"00000000", -- 00000D00
- X"A0620000", -- 00000D04
- X"8FC20000", -- 00000D08
- X"00000000", -- 00000D0C
- X"24420001", -- 00000D10
- X"AFC20000", -- 00000D14
- X"0FF0012B", -- 00000D18
- X"00000000", -- 00000D1C
- X"A3C20004", -- 00000D20
- X"83C30004", -- 00000D24
- X"2402000D", -- 00000D28
- X"10620005", -- 00000D2C
- X"00000000", -- 00000D30
- X"83C30004", -- 00000D34
- X"2402000A", -- 00000D38
- X"1462FFEB", -- 00000D3C
- X"00000000", -- 00000D40
- X"8FC20000", -- 00000D44
- X"03C0E821", -- 00000D48
- X"8FBF0014", -- 00000D4C
- X"8FBE0010", -- 00000D50
- X"27BD0018", -- 00000D54
- X"03E00008", -- 00000D58
- X"00000000", -- 00000D5C
- X"27BDFFF0", -- 00000D60
- X"AFBE000C", -- 00000D64
- X"03A0F021", -- 00000D68
- X"AFC40000", -- 00000D6C
- X"401A6000", -- 00000D70
- X"3C1BFFBF", -- 00000D74
- X"377BFFFF", -- 00000D78
- X"035BD024", -- 00000D7C
- X"409A6000", -- 00000D80
- X"00800008", -- 00000D84
- X"42000010", -- 00000D88
- X"03C0E821", -- 00000D8C
- X"8FBE000C", -- 00000D90
- X"03E00008", -- 00000D94
- X"27BD0010", -- 00000D98
- X"27BDFFD0", -- 00000D9C
- X"AFBF002C", -- 00000DA0
- X"AFBE0028", -- 00000DA4
- X"03A0F021", -- 00000DA8
- X"3C02BFC0", -- 00000DAC
- X"244215D0", -- 00000DB0
- X"AFC20008", -- 00000DB4
- X"3C02BFC0", -- 00000DB8
- X"244215D8", -- 00000DBC
- X"AFC2000C", -- 00000DC0
- X"3C02BFC0", -- 00000DC4
- X"244215E0", -- 00000DC8
- X"AFC20010", -- 00000DCC
- X"3C02BFC0", -- 00000DD0
- X"244215E8", -- 00000DD4
- X"AFC20014", -- 00000DD8
- X"3C02BFC0", -- 00000DDC
- X"244215F0", -- 00000DE0
- X"AFC20018", -- 00000DE4
- X"3C02BFC0", -- 00000DE8
- X"244215F8", -- 00000DEC
- X"AFC2001C", -- 00000DF0
- X"3C02BFC0", -- 00000DF4
- X"24421604", -- 00000DF8
- X"AFC20020", -- 00000DFC
- X"0FF0011B", -- 00000E00
- X"00000000", -- 00000E04
- X"AFC20004", -- 00000E08
- X"3C02BFC0", -- 00000E0C
- X"2444160C", -- 00000E10
- X"0FF0017E", -- 00000E14
- X"00000000", -- 00000E18
- X"8FC40004", -- 00000E1C
- X"0FF001D8", -- 00000E20
- X"00000000", -- 00000E24
- X"3C02BFC0", -- 00000E28
- X"24441618", -- 00000E2C
- X"0FF0017E", -- 00000E30
- X"00000000", -- 00000E34
- X"0FF00123", -- 00000E38
- X"00000000", -- 00000E3C
- X"AFC20004", -- 00000E40
- X"8FC20004", -- 00000E44
- X"00000000", -- 00000E48
- X"00021203", -- 00000E4C
- X"304200FF", -- 00000E50
- X"AFC20000", -- 00000E54
- X"3C02BFC0", -- 00000E58
- X"2444161C", -- 00000E5C
- X"0FF0017E", -- 00000E60
- X"00000000", -- 00000E64
- X"8FC20000", -- 00000E68
- X"00000000", -- 00000E6C
- X"18400020", -- 00000E70
- X"00000000", -- 00000E74
- X"8FC20000", -- 00000E78
- X"00000000", -- 00000E7C
- X"28420007", -- 00000E80
- X"1040001B", -- 00000E84
- X"00000000", -- 00000E88
- X"8FC20000", -- 00000E8C
- X"00000000", -- 00000E90
- X"00021080", -- 00000E94
- X"03C21021", -- 00000E98
- X"8C420008", -- 00000E9C
- X"00000000", -- 00000EA0
- X"00402021", -- 00000EA4
- X"0FF0017E", -- 00000EA8
- X"00000000", -- 00000EAC
- X"3C02BFC0", -- 00000EB0
- X"24441628", -- 00000EB4
- X"0FF0017E", -- 00000EB8
- X"00000000", -- 00000EBC
- X"8FC20004", -- 00000EC0
- X"00000000", -- 00000EC4
- X"304200FF", -- 00000EC8
- X"AFC20000", -- 00000ECC
- X"8FC20000", -- 00000ED0
- X"00000000", -- 00000ED4
- X"00021600", -- 00000ED8
- X"00021603", -- 00000EDC
- X"00402021", -- 00000EE0
- X"0FF001A4", -- 00000EE4
- X"00000000", -- 00000EE8
- X"0BF003C1", -- 00000EEC
- X"00000000", -- 00000EF0
- X"3C02BFC0", -- 00000EF4
- X"24441630", -- 00000EF8
- X"0FF0017E", -- 00000EFC
- X"00000000", -- 00000F00
- X"3C02BFC0", -- 00000F04
- X"24441618", -- 00000F08
- X"0FF0017E", -- 00000F0C
- X"00000000", -- 00000F10
- X"03C0E821", -- 00000F14
- X"8FBF002C", -- 00000F18
- X"8FBE0028", -- 00000F1C
- X"27BD0030", -- 00000F20
- X"03E00008", -- 00000F24
- X"00000000", -- 00000F28
- X"27BDFEA8", -- 00000F2C
- X"AFBF0154", -- 00000F30
- X"AFBE0150", -- 00000F34
- X"03A0F021", -- 00000F38
- X"AFC40140", -- 00000F3C
- X"AFC50144", -- 00000F40
- X"3C02A000", -- 00000F44
- X"AFC20020", -- 00000F48
- X"3C02A400", -- 00000F4C
- X"AFC20010", -- 00000F50
- X"3C02A002", -- 00000F54
- X"AFC2000C", -- 00000F58
- X"3C024000", -- 00000F5C
- X"AFC20008", -- 00000F60
- X"3C024000", -- 00000F64
- X"AFC20004", -- 00000F68
- X"3C024000", -- 00000F6C
- X"AFC20000", -- 00000F70
- X"8FC20020", -- 00000F74
- X"00000000", -- 00000F78
- X"AC400000", -- 00000F7C
- X"AFC00024", -- 00000F80
- X"3C02BFC0", -- 00000F84
- X"24441638", -- 00000F88
- X"0FF0017E", -- 00000F8C
- X"00000000", -- 00000F90
- X"3C024000", -- 00000F94
- X"AFC20014", -- 00000F98
- X"AFC00018", -- 00000F9C
- X"AFC00028", -- 00000FA0
- X"0BF003FD", -- 00000FA4
- X"00000000", -- 00000FA8
- X"8FC20018", -- 00000FAC
- X"00000000", -- 00000FB0
- X"8C430000", -- 00000FB4
- X"8FC20014", -- 00000FB8
- X"00000000", -- 00000FBC
- X"AC430000", -- 00000FC0
- X"8FC20014", -- 00000FC4
- X"00000000", -- 00000FC8
- X"24420004", -- 00000FCC
- X"AFC20014", -- 00000FD0
- X"8FC20018", -- 00000FD4
- X"00000000", -- 00000FD8
- X"24420004", -- 00000FDC
- X"AFC20018", -- 00000FE0
- X"8FC20028", -- 00000FE4
- X"00000000", -- 00000FE8
- X"24420004", -- 00000FEC
- X"AFC20028", -- 00000FF0
- X"8FC20028", -- 00000FF4
- X"00000000", -- 00000FF8
- X"28423500", -- 00000FFC
- X"1440FFEA", -- 00001000
- X"00000000", -- 00001004
- X"3C044000", -- 00001008
- X"0FF00358", -- 0000100C
- X"00000000", -- 00001010
- X"3C02BFC0", -- 00001014
- X"24441640", -- 00001018
- X"0FF0017E", -- 0000101C
- X"00000000", -- 00001020
- X"3C02BFC0", -- 00001024
- X"24441654", -- 00001028
- X"0FF0017E", -- 0000102C
- X"00000000", -- 00001030
- X"AFC00028", -- 00001034
- X"0BF0041C", -- 00001038
- X"00000000", -- 0000103C
- X"8FC30028", -- 00001040
- X"8FC20008", -- 00001044
- X"00000000", -- 00001048
- X"00431821", -- 0000104C
- X"8FC20028", -- 00001050
- X"00000000", -- 00001054
- X"304200FF", -- 00001058
- X"A0620000", -- 0000105C
- X"8FC20028", -- 00001060
- X"00000000", -- 00001064
- X"24420001", -- 00001068
- X"AFC20028", -- 0000106C
- X"8FC20028", -- 00001070
- X"3C030010", -- 00001074
- X"0043102A", -- 00001078
- X"1440FFF0", -- 0000107C
- X"00000000", -- 00001080
- X"3C02BFC0", -- 00001084
- X"2444166C", -- 00001088
- X"0FF0017E", -- 0000108C
- X"00000000", -- 00001090
- X"3C02BFC0", -- 00001094
- X"24441674", -- 00001098
- X"0FF0017E", -- 0000109C
- X"00000000", -- 000010A0
- X"3C02000F", -- 000010A4
- X"3442FFFF", -- 000010A8
- X"AFC20028", -- 000010AC
- X"0BF0043E", -- 000010B0
- X"00000000", -- 000010B4
- X"8FC30028", -- 000010B8
- X"8FC20008", -- 000010BC
- X"00000000", -- 000010C0
- X"00431021", -- 000010C4
- X"90420000", -- 000010C8
- X"00000000", -- 000010CC
- X"304300FF", -- 000010D0
- X"8FC20028", -- 000010D4
- X"00000000", -- 000010D8
- X"304200FF", -- 000010DC
- X"14620009", -- 000010E0
- X"00000000", -- 000010E4
- X"8FC20028", -- 000010E8
- X"00000000", -- 000010EC
- X"2442FFFF", -- 000010F0
- X"AFC20028", -- 000010F4
- X"8FC20028", -- 000010F8
- X"00000000", -- 000010FC
- X"0441FFED", -- 00001100
- X"00000000", -- 00001104
- X"8FC20028", -- 00001108
- X"00000000", -- 0000110C
- X"24420001", -- 00001110
- X"AFC20028", -- 00001114
- X"8FC20028", -- 00001118
- X"00000000", -- 0000111C
- X"10400007", -- 00001120
- X"00000000", -- 00001124
- X"3C02BFC0", -- 00001128
- X"24441690", -- 0000112C
- X"0FF0017E", -- 00001130
- X"00000000", -- 00001134
- X"0BF00454", -- 00001138
- X"00000000", -- 0000113C
- X"3C02BFC0", -- 00001140
- X"2444169C", -- 00001144
- X"0FF0017E", -- 00001148
- X"00000000", -- 0000114C
- X"3C02BFC0", -- 00001150
- X"244416A8", -- 00001154
- X"0FF0017E", -- 00001158
- X"00000000", -- 0000115C
- X"AFC00028", -- 00001160
- X"0BF00469", -- 00001164
- X"00000000", -- 00001168
- X"8FC20028", -- 0000116C
- X"00000000", -- 00001170
- X"00021840", -- 00001174
- X"8FC20004", -- 00001178
- X"00000000", -- 0000117C
- X"00431821", -- 00001180
- X"8FC20028", -- 00001184
- X"00000000", -- 00001188
- X"3042FFFF", -- 0000118C
- X"A4620000", -- 00001190
- X"8FC20028", -- 00001194
- X"00000000", -- 00001198
- X"24420001", -- 0000119C
- X"AFC20028", -- 000011A0
- X"8FC20028", -- 000011A4
- X"3C030008", -- 000011A8
- X"0043102A", -- 000011AC
- X"1440FFEE", -- 000011B0
- X"00000000", -- 000011B4
- X"3C02BFC0", -- 000011B8
- X"2444166C", -- 000011BC
- X"0FF0017E", -- 000011C0
- X"00000000", -- 000011C4
- X"3C02BFC0", -- 000011C8
- X"244416C4", -- 000011CC
- X"0FF0017E", -- 000011D0
- X"00000000", -- 000011D4
- X"3C020007", -- 000011D8
- X"3442FFFF", -- 000011DC
- X"AFC20028", -- 000011E0
- X"0BF0048D", -- 000011E4
- X"00000000", -- 000011E8
- X"8FC20028", -- 000011EC
- X"00000000", -- 000011F0
- X"00021840", -- 000011F4
- X"8FC20004", -- 000011F8
- X"00000000", -- 000011FC
- X"00431021", -- 00001200
- X"94420000", -- 00001204
- X"00000000", -- 00001208
- X"3043FFFF", -- 0000120C
- X"8FC20028", -- 00001210
- X"00000000", -- 00001214
- X"3042FFFF", -- 00001218
- X"14620009", -- 0000121C
- X"00000000", -- 00001220
- X"8FC20028", -- 00001224
- X"00000000", -- 00001228
- X"2442FFFF", -- 0000122C
- X"AFC20028", -- 00001230
- X"8FC20028", -- 00001234
- X"00000000", -- 00001238
- X"0441FFEB", -- 0000123C
- X"00000000", -- 00001240
- X"8FC20028", -- 00001244
- X"00000000", -- 00001248
- X"24420001", -- 0000124C
- X"AFC20028", -- 00001250
- X"8FC20028", -- 00001254
- X"00000000", -- 00001258
- X"10400007", -- 0000125C
- X"00000000", -- 00001260
- X"3C02BFC0", -- 00001264
- X"24441690", -- 00001268
- X"0FF0017E", -- 0000126C
- X"00000000", -- 00001270
- X"0BF004A3", -- 00001274
- X"00000000", -- 00001278
- X"3C02BFC0", -- 0000127C
- X"2444169C", -- 00001280
- X"0FF0017E", -- 00001284
- X"00000000", -- 00001288
- X"3C02BFC0", -- 0000128C
- X"244416E0", -- 00001290
- X"0FF0017E", -- 00001294
- X"00000000", -- 00001298
- X"AFC00028", -- 0000129C
- X"0BF004B7", -- 000012A0
- X"00000000", -- 000012A4
- X"8FC20028", -- 000012A8
- X"00000000", -- 000012AC
- X"00021880", -- 000012B0
- X"8FC20000", -- 000012B4
- X"00000000", -- 000012B8
- X"00431821", -- 000012BC
- X"8FC20028", -- 000012C0
- X"00000000", -- 000012C4
- X"AC620000", -- 000012C8
- X"8FC20028", -- 000012CC
- X"00000000", -- 000012D0
- X"24420001", -- 000012D4
- X"AFC20028", -- 000012D8
- X"8FC20028", -- 000012DC
- X"3C030004", -- 000012E0
- X"0043102A", -- 000012E4
- X"1440FFEF", -- 000012E8
- X"00000000", -- 000012EC
- X"3C02BFC0", -- 000012F0
- X"2444166C", -- 000012F4
- X"0FF0017E", -- 000012F8
- X"00000000", -- 000012FC
- X"3C02BFC0", -- 00001300
- X"244416FC", -- 00001304
- X"0FF0017E", -- 00001308
- X"00000000", -- 0000130C
- X"3C020003", -- 00001310
- X"3442FFFF", -- 00001314
- X"AFC20028", -- 00001318
- X"0BF004D8", -- 0000131C
- X"00000000", -- 00001320
- X"8FC20028", -- 00001324
- X"00000000", -- 00001328
- X"00021880", -- 0000132C
- X"8FC20000", -- 00001330
- X"00000000", -- 00001334
- X"00431021", -- 00001338
- X"8C430000", -- 0000133C
- X"8FC20028", -- 00001340
- X"00000000", -- 00001344
- X"14620009", -- 00001348
- X"00000000", -- 0000134C
- X"8FC20028", -- 00001350
- X"00000000", -- 00001354
- X"2442FFFF", -- 00001358
- X"AFC20028", -- 0000135C
- X"8FC20028", -- 00001360
- X"00000000", -- 00001364
- X"0441FFEE", -- 00001368
- X"00000000", -- 0000136C
- X"8FC20028", -- 00001370
- X"00000000", -- 00001374
- X"24420001", -- 00001378
- X"AFC20028", -- 0000137C
- X"8FC20028", -- 00001380
- X"00000000", -- 00001384
- X"10400007", -- 00001388
- X"00000000", -- 0000138C
- X"3C02BFC0", -- 00001390
- X"24441690", -- 00001394
- X"0FF0017E", -- 00001398
- X"00000000", -- 0000139C
- X"0BF004EE", -- 000013A0
- X"00000000", -- 000013A4
- X"3C02BFC0", -- 000013A8
- X"2444169C", -- 000013AC
- X"0FF0017E", -- 000013B0
- X"00000000", -- 000013B4
- X"AFC00028", -- 000013B8
- X"0BF004FC", -- 000013BC
- X"00000000", -- 000013C0
- X"8FC20028", -- 000013C4
- X"00000000", -- 000013C8
- X"00021880", -- 000013CC
- X"8FC20000", -- 000013D0
- X"00000000", -- 000013D4
- X"00431021", -- 000013D8
- X"AC400000", -- 000013DC
- X"8FC20028", -- 000013E0
- X"00000000", -- 000013E4
- X"24420001", -- 000013E8
- X"AFC20028", -- 000013EC
- X"8FC20028", -- 000013F0
- X"3C030004", -- 000013F4
- X"0043102A", -- 000013F8
- X"1440FFF1", -- 000013FC
- X"00000000", -- 00001400
- X"3C02BFC0", -- 00001404
- X"24441638", -- 00001408
- X"0FF0017E", -- 0000140C
- X"00000000", -- 00001410
- X"27C20030", -- 00001414
- X"00402021", -- 00001418
- X"0FF00328", -- 0000141C
- X"00000000", -- 00001420
- X"AFC2002C", -- 00001424
- X"27C20130", -- 00001428
- X"27C30030", -- 0000142C
- X"00402021", -- 00001430
- X"00602821", -- 00001434
- X"8FC6002C", -- 00001438
- X"0FF00234", -- 0000143C
- X"00000000", -- 00001440
- X"AFC2002C", -- 00001444
- X"8FC20020", -- 00001448
- X"00000000", -- 0000144C
- X"AC400000", -- 00001450
- X"8FC2002C", -- 00001454
- X"00000000", -- 00001458
- X"AFC20148", -- 0000145C
- X"24020002", -- 00001460
- X"8FC30148", -- 00001464
- X"00000000", -- 00001468
- X"10620008", -- 0000146C
- X"00000000", -- 00001470
- X"24020004", -- 00001474
- X"8FC30148", -- 00001478
- X"00000000", -- 0000147C
- X"1062002F", -- 00001480
- X"00000000", -- 00001484
- X"0BF0056B", -- 00001488
- X"00000000", -- 0000148C
- X"8FC30130", -- 00001490
- X"8FC20134", -- 00001494
- X"00000000", -- 00001498
- X"00621821", -- 0000149C
- X"8FC20024", -- 000014A0
- X"00000000", -- 000014A4
- X"0043102B", -- 000014A8
- X"10400006", -- 000014AC
- X"00000000", -- 000014B0
- X"8FC20130", -- 000014B4
- X"8FC30134", -- 000014B8
- X"00000000", -- 000014BC
- X"00431021", -- 000014C0
- X"AFC20024", -- 000014C4
- X"8FC20130", -- 000014C8
- X"00000000", -- 000014CC
- X"AFC2001C", -- 000014D0
- X"AFC00028", -- 000014D4
- X"0BF00548", -- 000014D8
- X"00000000", -- 000014DC
- X"8FC3013C", -- 000014E0
- X"8FC20028", -- 000014E4
- X"00000000", -- 000014E8
- X"00621021", -- 000014EC
- X"90430000", -- 000014F0
- X"8FC2001C", -- 000014F4
- X"00000000", -- 000014F8
- X"A0430000", -- 000014FC
- X"8FC2001C", -- 00001500
- X"00000000", -- 00001504
- X"24420001", -- 00001508
- X"AFC2001C", -- 0000150C
- X"8FC20028", -- 00001510
- X"00000000", -- 00001514
- X"24420001", -- 00001518
- X"AFC20028", -- 0000151C
- X"8FC20028", -- 00001520
- X"8FC30134", -- 00001524
- X"00000000", -- 00001528
- X"0043102B", -- 0000152C
- X"1440FFEB", -- 00001530
- X"00000000", -- 00001534
- X"0BF0056B", -- 00001538
- X"00000000", -- 0000153C
- X"8FC30020", -- 00001540
- X"24020001", -- 00001544
- X"AC620000", -- 00001548
- X"8FC20130", -- 0000154C
- X"00000000", -- 00001550
- X"00402021", -- 00001554
- X"0FF001D8", -- 00001558
- X"00000000", -- 0000155C
- X"3C02BFC0", -- 00001560
- X"24441718", -- 00001564
- X"0FF0017E", -- 00001568
- X"00000000", -- 0000156C
- X"8FC20024", -- 00001570
- X"00000000", -- 00001574
- X"2442FFFC", -- 00001578
- X"00402021", -- 0000157C
- X"0FF001D8", -- 00001580
- X"00000000", -- 00001584
- X"3C02BFC0", -- 00001588
- X"24441720", -- 0000158C
- X"0FF0017E", -- 00001590
- X"00000000", -- 00001594
- X"8FC20130", -- 00001598
- X"00000000", -- 0000159C
- X"00402021", -- 000015A0
- X"0FF00358", -- 000015A4
- X"00000000", -- 000015A8
- X"8FC2002C", -- 000015AC
- X"00000000", -- 000015B0
- X"1440FF97", -- 000015B4
- X"00000000", -- 000015B8
- X"8FC30020", -- 000015BC
- X"3C024000", -- 000015C0
- X"AC620000", -- 000015C4
- X"0BF00501", -- 000015C8
- X"00000000", -- 000015CC
- X"61766E69", -- 000015D0
- X"0064696C", -- 000015D4
- X"30303252", -- 000015D8
- X"00000030", -- 000015DC
- X"30303352", -- 000015E0
- X"00000030", -- 000015E4
- X"30303652", -- 000015E8
- X"00000030", -- 000015EC
- X"30303452", -- 000015F0
- X"00000030", -- 000015F4
- X"65736572", -- 000015F8
- X"64657672", -- 000015FC
- X"00000000", -- 00001600
- X"30303652", -- 00001604
- X"00004130", -- 00001608
- X"74617453", -- 0000160C
- X"20207375", -- 00001610
- X"0000203A", -- 00001614
- X"0000000A", -- 00001618
- X"20555043", -- 0000161C
- X"65707974", -- 00001620
- X"0000203A", -- 00001624
- X"76655220", -- 00001628
- X"0000002E", -- 0000162C
- X"6E6B6E55", -- 00001630
- X"006E776F", -- 00001634
- X"544F4F42", -- 00001638
- X"00000020", -- 0000163C
- X"41524453", -- 00001640
- X"654D204D", -- 00001644
- X"79726F6D", -- 00001648
- X"73655420", -- 0000164C
- X"000A0D74", -- 00001650
- X"74697257", -- 00001654
- X"38282065", -- 00001658
- X"7469422D", -- 0000165C
- X"63636120", -- 00001660
- X"29737365", -- 00001664
- X"002E2E2E", -- 00001668
- X"656E6F64", -- 0000166C
- X"00000A0D", -- 00001670
- X"69726556", -- 00001674
- X"28207966", -- 00001678
- X"69422D38", -- 0000167C
- X"63612074", -- 00001680
- X"73736563", -- 00001684
- X"2E2E2E29", -- 00001688
- X"00000000", -- 0000168C
- X"6C696166", -- 00001690
- X"0A0D6465", -- 00001694
- X"00000000", -- 00001698
- X"73736170", -- 0000169C
- X"0A0D6465", -- 000016A0
- X"00000000", -- 000016A4
- X"74697257", -- 000016A8
- X"31282065", -- 000016AC
- X"69422D36", -- 000016B0
- X"63612074", -- 000016B4
- X"73736563", -- 000016B8
- X"2E2E2E29", -- 000016BC
- X"00000000", -- 000016C0
- X"69726556", -- 000016C4
- X"28207966", -- 000016C8
- X"422D3631", -- 000016CC
- X"61207469", -- 000016D0
- X"73656363", -- 000016D4
- X"2E2E2973", -- 000016D8
- X"0000002E", -- 000016DC
- X"74697257", -- 000016E0
- X"33282065", -- 000016E4
- X"69422D32", -- 000016E8
- X"63612074", -- 000016EC
- X"73736563", -- 000016F0
- X"2E2E2E29", -- 000016F4
- X"00000000", -- 000016F8
- X"69726556", -- 000016FC
- X"28207966", -- 00001700
- X"422D3233", -- 00001704
- X"61207469", -- 00001708
- X"73656363", -- 0000170C
- X"2E2E2973", -- 00001710
- X"0000002E", -- 00001714
- X"206F7420", -- 00001718
- X"00000000", -- 0000171C
- X"00000A0D", -- 00001720
- X"00000000", -- 00001724
- X"00000000", -- 00001728
- X"00000000", -- 0000172C
- X"00000000", -- 00001730
- X"00000000", -- 00001734
- X"00000000", -- 00001738
- X"00000000", -- 0000173C
- X"00000000", -- 00001740
- X"00000000", -- 00001744
- X"00000000", -- 00001748
- X"00000000", -- 0000174C
- X"00000000", -- 00001750
- X"00000000", -- 00001754
- X"00000000", -- 00001758
- X"00000000", -- 0000175C
- X"00000000", -- 00001760
- X"00000000", -- 00001764
- X"00000000", -- 00001768
- X"00000000", -- 0000176C
- X"00000000", -- 00001770
- X"00000000", -- 00001774
- X"00000000", -- 00001778
- X"00000000", -- 0000177C
- X"00000000", -- 00001780
- X"00000000", -- 00001784
- X"00000000", -- 00001788
- X"00000000", -- 0000178C
- X"00000000", -- 00001790
- X"00000000", -- 00001794
- X"00000000", -- 00001798
- X"00000000", -- 0000179C
- X"00000000", -- 000017A0
- X"00000000", -- 000017A4
- X"00000000", -- 000017A8
- X"00000000", -- 000017AC
- X"00000000", -- 000017B0
- X"00000000", -- 000017B4
- X"00000000", -- 000017B8
- X"00000000", -- 000017BC
- X"00000000", -- 000017C0
- X"00000000", -- 000017C4
- X"00000000", -- 000017C8
- X"00000000", -- 000017CC
- X"00000000", -- 000017D0
- X"00000000", -- 000017D4
- X"00000000", -- 000017D8
- X"00000000", -- 000017DC
- X"00000000", -- 000017E0
- X"00000000", -- 000017E4
- X"00000000", -- 000017E8
- X"00000000", -- 000017EC
- X"00000000", -- 000017F0
- X"00000000", -- 000017F4
- X"00000000", -- 000017F8
- X"00000000", -- 000017FC
- X"00000000", -- 00001800
- X"00000000", -- 00001804
- X"00000000", -- 00001808
- X"00000000", -- 0000180C
- X"00000000", -- 00001810
- X"00000000", -- 00001814
- X"00000000", -- 00001818
- X"00000000", -- 0000181C
- X"00000000", -- 00001820
- X"00000000", -- 00001824
- X"00000000", -- 00001828
- X"00000000", -- 0000182C
- X"00000000", -- 00001830
- X"00000000", -- 00001834
- X"00000000", -- 00001838
- X"00000000", -- 0000183C
- X"00000000", -- 00001840
- X"00000000", -- 00001844
- X"00000000", -- 00001848
- X"00000000", -- 0000184C
- X"00000000", -- 00001850
- X"00000000", -- 00001854
- X"00000000", -- 00001858
- X"00000000", -- 0000185C
- X"00000000", -- 00001860
- X"00000000", -- 00001864
- X"00000000", -- 00001868
- X"00000000", -- 0000186C
- X"00000000", -- 00001870
- X"00000000", -- 00001874
- X"00000000", -- 00001878
- X"00000000", -- 0000187C
- X"00000000", -- 00001880
- X"00000000", -- 00001884
- X"00000000", -- 00001888
- X"00000000", -- 0000188C
- X"00000000", -- 00001890
- X"00000000", -- 00001894
- X"00000000", -- 00001898
- X"00000000", -- 0000189C
- X"00000000", -- 000018A0
- X"00000000", -- 000018A4
- X"00000000", -- 000018A8
- X"00000000", -- 000018AC
- X"00000000", -- 000018B0
- X"00000000", -- 000018B4
- X"00000000", -- 000018B8
- X"00000000", -- 000018BC
- X"00000000", -- 000018C0
- X"00000000", -- 000018C4
- X"00000000", -- 000018C8
- X"00000000", -- 000018CC
- X"00000000", -- 000018D0
- X"00000000", -- 000018D4
- X"00000000", -- 000018D8
- X"00000000", -- 000018DC
- X"00000000", -- 000018E0
- X"00000000", -- 000018E4
- X"00000000", -- 000018E8
- X"00000000", -- 000018EC
- X"00000000", -- 000018F0
- X"00000000", -- 000018F4
- X"00000000", -- 000018F8
- X"00000000", -- 000018FC
- X"00000000", -- 00001900
- X"00000000", -- 00001904
- X"00000000", -- 00001908
- X"00000000", -- 0000190C
- X"00000000", -- 00001910
- X"00000000", -- 00001914
- X"00000000", -- 00001918
- X"00000000", -- 0000191C
- X"00000000", -- 00001920
- X"00000000", -- 00001924
- X"00000000", -- 00001928
- X"00000000", -- 0000192C
- X"00000000", -- 00001930
- X"00000000", -- 00001934
- X"00000000", -- 00001938
- X"00000000", -- 0000193C
- X"00000000", -- 00001940
- X"00000000", -- 00001944
- X"00000000", -- 00001948
- X"00000000", -- 0000194C
- X"00000000", -- 00001950
- X"00000000", -- 00001954
- X"00000000", -- 00001958
- X"00000000", -- 0000195C
- X"00000000", -- 00001960
- X"00000000", -- 00001964
- X"00000000", -- 00001968
- X"00000000", -- 0000196C
- X"00000000", -- 00001970
- X"00000000", -- 00001974
- X"00000000", -- 00001978
- X"00000000", -- 0000197C
- X"00000000", -- 00001980
- X"00000000", -- 00001984
- X"00000000", -- 00001988
- X"00000000", -- 0000198C
- X"00000000", -- 00001990
- X"00000000", -- 00001994
- X"00000000", -- 00001998
- X"00000000", -- 0000199C
- X"00000000", -- 000019A0
- X"00000000", -- 000019A4
- X"00000000", -- 000019A8
- X"00000000", -- 000019AC
- X"00000000", -- 000019B0
- X"00000000", -- 000019B4
- X"00000000", -- 000019B8
- X"00000000", -- 000019BC
- X"00000000", -- 000019C0
- X"00000000", -- 000019C4
- X"00000000", -- 000019C8
- X"00000000", -- 000019CC
- X"00000000", -- 000019D0
- X"00000000", -- 000019D4
- X"00000000", -- 000019D8
- X"00000000", -- 000019DC
- X"00000000", -- 000019E0
- X"00000000", -- 000019E4
- X"00000000", -- 000019E8
- X"00000000", -- 000019EC
- X"00000000", -- 000019F0
- X"00000000", -- 000019F4
- X"00000000", -- 000019F8
- X"00000000", -- 000019FC
- X"00000000", -- 00001A00
- X"00000000", -- 00001A04
- X"00000000", -- 00001A08
- X"00000000", -- 00001A0C
- X"00000000", -- 00001A10
- X"00000000", -- 00001A14
- X"00000000", -- 00001A18
- X"00000000", -- 00001A1C
- X"00000000", -- 00001A20
- X"00000000", -- 00001A24
- X"00000000", -- 00001A28
- X"00000000", -- 00001A2C
- X"00000000", -- 00001A30
- X"00000000", -- 00001A34
- X"00000000", -- 00001A38
- X"00000000", -- 00001A3C
- X"00000000", -- 00001A40
- X"00000000", -- 00001A44
- X"00000000", -- 00001A48
- X"00000000", -- 00001A4C
- X"00000000", -- 00001A50
- X"00000000", -- 00001A54
- X"00000000", -- 00001A58
- X"00000000", -- 00001A5C
- X"00000000", -- 00001A60
- X"00000000", -- 00001A64
- X"00000000", -- 00001A68
- X"00000000", -- 00001A6C
- X"00000000", -- 00001A70
- X"00000000", -- 00001A74
- X"00000000", -- 00001A78
- X"00000000", -- 00001A7C
- X"00000000", -- 00001A80
- X"00000000", -- 00001A84
- X"00000000", -- 00001A88
- X"00000000", -- 00001A8C
- X"00000000", -- 00001A90
- X"00000000", -- 00001A94
- X"00000000", -- 00001A98
- X"00000000", -- 00001A9C
- X"00000000", -- 00001AA0
- X"00000000", -- 00001AA4
- X"00000000", -- 00001AA8
- X"00000000", -- 00001AAC
- X"00000000", -- 00001AB0
- X"00000000", -- 00001AB4
- X"00000000", -- 00001AB8
- X"00000000", -- 00001ABC
- X"00000000", -- 00001AC0
- X"00000000", -- 00001AC4
- X"00000000", -- 00001AC8
- X"00000000", -- 00001ACC
- X"00000000", -- 00001AD0
- X"00000000", -- 00001AD4
- X"00000000", -- 00001AD8
- X"00000000", -- 00001ADC
- X"00000000", -- 00001AE0
- X"00000000", -- 00001AE4
- X"00000000", -- 00001AE8
- X"00000000", -- 00001AEC
- X"00000000", -- 00001AF0
- X"00000000", -- 00001AF4
- X"00000000", -- 00001AF8
- X"00000000", -- 00001AFC
- X"00000000", -- 00001B00
- X"00000000", -- 00001B04
- X"00000000", -- 00001B08
- X"00000000", -- 00001B0C
- X"00000000", -- 00001B10
- X"00000000", -- 00001B14
- X"00000000", -- 00001B18
- X"00000000", -- 00001B1C
- X"00000000", -- 00001B20
- X"00000000", -- 00001B24
- X"00000000", -- 00001B28
- X"00000000", -- 00001B2C
- X"00000000", -- 00001B30
- X"00000000", -- 00001B34
- X"00000000", -- 00001B38
- X"00000000", -- 00001B3C
- X"00000000", -- 00001B40
- X"00000000", -- 00001B44
- X"00000000", -- 00001B48
- X"00000000", -- 00001B4C
- X"00000000", -- 00001B50
- X"00000000", -- 00001B54
- X"00000000", -- 00001B58
- X"00000000", -- 00001B5C
- X"00000000", -- 00001B60
- X"00000000", -- 00001B64
- X"00000000", -- 00001B68
- X"00000000", -- 00001B6C
- X"00000000", -- 00001B70
- X"00000000", -- 00001B74
- X"00000000", -- 00001B78
- X"00000000", -- 00001B7C
- X"00000000", -- 00001B80
- X"00000000", -- 00001B84
- X"00000000", -- 00001B88
- X"00000000", -- 00001B8C
- X"00000000", -- 00001B90
- X"00000000", -- 00001B94
- X"00000000", -- 00001B98
- X"00000000", -- 00001B9C
- X"00000000", -- 00001BA0
- X"00000000", -- 00001BA4
- X"00000000", -- 00001BA8
- X"00000000", -- 00001BAC
- X"00000000", -- 00001BB0
- X"00000000", -- 00001BB4
- X"00000000", -- 00001BB8
- X"00000000", -- 00001BBC
- X"00000000", -- 00001BC0
- X"00000000", -- 00001BC4
- X"00000000", -- 00001BC8
- X"00000000", -- 00001BCC
- X"00000000", -- 00001BD0
- X"00000000", -- 00001BD4
- X"00000000", -- 00001BD8
- X"00000000", -- 00001BDC
- X"00000000", -- 00001BE0
- X"00000000", -- 00001BE4
- X"00000000", -- 00001BE8
- X"00000000", -- 00001BEC
- X"00000000", -- 00001BF0
- X"00000000", -- 00001BF4
- X"00000000", -- 00001BF8
- X"00000000", -- 00001BFC
- X"00000000", -- 00001C00
- X"00000000", -- 00001C04
- X"00000000", -- 00001C08
- X"00000000", -- 00001C0C
- X"00000000", -- 00001C10
- X"00000000", -- 00001C14
- X"00000000", -- 00001C18
- X"00000000", -- 00001C1C
- X"00000000", -- 00001C20
- X"00000000", -- 00001C24
- X"00000000", -- 00001C28
- X"00000000", -- 00001C2C
- X"00000000", -- 00001C30
- X"00000000", -- 00001C34
- X"00000000", -- 00001C38
- X"00000000", -- 00001C3C
- X"00000000", -- 00001C40
- X"00000000", -- 00001C44
- X"00000000", -- 00001C48
- X"00000000", -- 00001C4C
- X"00000000", -- 00001C50
- X"00000000", -- 00001C54
- X"00000000", -- 00001C58
- X"00000000", -- 00001C5C
- X"00000000", -- 00001C60
- X"00000000", -- 00001C64
- X"00000000", -- 00001C68
- X"00000000", -- 00001C6C
- X"00000000", -- 00001C70
- X"00000000", -- 00001C74
- X"00000000", -- 00001C78
- X"00000000", -- 00001C7C
- X"00000000", -- 00001C80
- X"00000000", -- 00001C84
- X"00000000", -- 00001C88
- X"00000000", -- 00001C8C
- X"00000000", -- 00001C90
- X"00000000", -- 00001C94
- X"00000000", -- 00001C98
- X"00000000", -- 00001C9C
- X"00000000", -- 00001CA0
- X"00000000", -- 00001CA4
- X"00000000", -- 00001CA8
- X"00000000", -- 00001CAC
- X"00000000", -- 00001CB0
- X"00000000", -- 00001CB4
- X"00000000", -- 00001CB8
- X"00000000", -- 00001CBC
- X"00000000", -- 00001CC0
- X"00000000", -- 00001CC4
- X"00000000", -- 00001CC8
- X"00000000", -- 00001CCC
- X"00000000", -- 00001CD0
- X"00000000", -- 00001CD4
- X"00000000", -- 00001CD8
- X"00000000", -- 00001CDC
- X"00000000", -- 00001CE0
- X"00000000", -- 00001CE4
- X"00000000", -- 00001CE8
- X"00000000", -- 00001CEC
- X"00000000", -- 00001CF0
- X"00000000", -- 00001CF4
- X"00000000", -- 00001CF8
- X"00000000", -- 00001CFC
- X"00000000", -- 00001D00
- X"00000000", -- 00001D04
- X"00000000", -- 00001D08
- X"00000000", -- 00001D0C
- X"00000000", -- 00001D10
- X"00000000", -- 00001D14
- X"00000000", -- 00001D18
- X"00000000", -- 00001D1C
- X"00000000", -- 00001D20
- X"00000000", -- 00001D24
- X"00000000", -- 00001D28
- X"00000000", -- 00001D2C
- X"00000000", -- 00001D30
- X"00000000", -- 00001D34
- X"00000000", -- 00001D38
- X"00000000", -- 00001D3C
- X"00000000", -- 00001D40
- X"00000000", -- 00001D44
- X"00000000", -- 00001D48
- X"00000000", -- 00001D4C
- X"00000000", -- 00001D50
- X"00000000", -- 00001D54
- X"00000000", -- 00001D58
- X"00000000", -- 00001D5C
- X"00000000", -- 00001D60
- X"00000000", -- 00001D64
- X"00000000", -- 00001D68
- X"00000000", -- 00001D6C
- X"00000000", -- 00001D70
- X"00000000", -- 00001D74
- X"00000000", -- 00001D78
- X"00000000", -- 00001D7C
- X"00000000", -- 00001D80
- X"00000000", -- 00001D84
- X"00000000", -- 00001D88
- X"00000000", -- 00001D8C
- X"00000000", -- 00001D90
- X"00000000", -- 00001D94
- X"00000000", -- 00001D98
- X"00000000", -- 00001D9C
- X"00000000", -- 00001DA0
- X"00000000", -- 00001DA4
- X"00000000", -- 00001DA8
- X"00000000", -- 00001DAC
- X"00000000", -- 00001DB0
- X"00000000", -- 00001DB4
- X"00000000", -- 00001DB8
- X"00000000", -- 00001DBC
- X"00000000", -- 00001DC0
- X"00000000", -- 00001DC4
- X"00000000", -- 00001DC8
- X"00000000", -- 00001DCC
- X"00000000", -- 00001DD0
- X"00000000", -- 00001DD4
- X"00000000", -- 00001DD8
- X"00000000", -- 00001DDC
- X"00000000", -- 00001DE0
- X"00000000", -- 00001DE4
- X"00000000", -- 00001DE8
- X"00000000", -- 00001DEC
- X"00000000", -- 00001DF0
- X"00000000", -- 00001DF4
- X"00000000", -- 00001DF8
- X"00000000", -- 00001DFC
- X"00000000", -- 00001E00
- X"00000000", -- 00001E04
- X"00000000", -- 00001E08
- X"00000000", -- 00001E0C
- X"00000000", -- 00001E10
- X"00000000", -- 00001E14
- X"00000000", -- 00001E18
- X"00000000", -- 00001E1C
- X"00000000", -- 00001E20
- X"00000000", -- 00001E24
- X"00000000", -- 00001E28
- X"00000000", -- 00001E2C
- X"00000000", -- 00001E30
- X"00000000", -- 00001E34
- X"00000000", -- 00001E38
- X"00000000", -- 00001E3C
- X"00000000", -- 00001E40
- X"00000000", -- 00001E44
- X"00000000", -- 00001E48
- X"00000000", -- 00001E4C
- X"00000000", -- 00001E50
- X"00000000", -- 00001E54
- X"00000000", -- 00001E58
- X"00000000", -- 00001E5C
- X"00000000", -- 00001E60
- X"00000000", -- 00001E64
- X"00000000", -- 00001E68
- X"00000000", -- 00001E6C
- X"00000000", -- 00001E70
- X"00000000", -- 00001E74
- X"00000000", -- 00001E78
- X"00000000", -- 00001E7C
- X"00000000", -- 00001E80
- X"00000000", -- 00001E84
- X"00000000", -- 00001E88
- X"00000000", -- 00001E8C
- X"00000000", -- 00001E90
- X"00000000", -- 00001E94
- X"00000000", -- 00001E98
- X"00000000", -- 00001E9C
- X"00000000", -- 00001EA0
- X"00000000", -- 00001EA4
- X"00000000", -- 00001EA8
- X"00000000", -- 00001EAC
- X"00000000", -- 00001EB0
- X"00000000", -- 00001EB4
- X"00000000", -- 00001EB8
- X"00000000", -- 00001EBC
- X"00000000", -- 00001EC0
- X"00000000", -- 00001EC4
- X"00000000", -- 00001EC8
- X"00000000", -- 00001ECC
- X"00000000", -- 00001ED0
- X"00000000", -- 00001ED4
- X"00000000", -- 00001ED8
- X"00000000", -- 00001EDC
- X"00000000", -- 00001EE0
- X"00000000", -- 00001EE4
- X"00000000", -- 00001EE8
- X"00000000", -- 00001EEC
- X"00000000", -- 00001EF0
- X"00000000", -- 00001EF4
- X"00000000", -- 00001EF8
- X"00000000", -- 00001EFC
- X"00000000", -- 00001F00
- X"00000000", -- 00001F04
- X"00000000", -- 00001F08
- X"00000000", -- 00001F0C
- X"00000000", -- 00001F10
- X"00000000", -- 00001F14
- X"00000000", -- 00001F18
- X"00000000", -- 00001F1C
- X"00000000", -- 00001F20
- X"00000000", -- 00001F24
- X"00000000", -- 00001F28
- X"00000000", -- 00001F2C
- X"00000000", -- 00001F30
- X"00000000", -- 00001F34
- X"00000000", -- 00001F38
- X"00000000", -- 00001F3C
- X"00000000", -- 00001F40
- X"00000000", -- 00001F44
- X"00000000", -- 00001F48
- X"00000000", -- 00001F4C
- X"00000000", -- 00001F50
- X"00000000", -- 00001F54
- X"00000000", -- 00001F58
- X"00000000", -- 00001F5C
- X"00000000", -- 00001F60
- X"00000000", -- 00001F64
- X"00000000", -- 00001F68
- X"00000000", -- 00001F6C
- X"00000000", -- 00001F70
- X"00000000", -- 00001F74
- X"00000000", -- 00001F78
- X"00000000", -- 00001F7C
- X"00000000", -- 00001F80
- X"00000000", -- 00001F84
- X"00000000", -- 00001F88
- X"00000000", -- 00001F8C
- X"00000000", -- 00001F90
- X"00000000", -- 00001F94
- X"00000000", -- 00001F98
- X"00000000", -- 00001F9C
- X"00000000", -- 00001FA0
- X"00000000", -- 00001FA4
- X"00000000", -- 00001FA8
- X"00000000", -- 00001FAC
- X"00000000", -- 00001FB0
- X"00000000", -- 00001FB4
- X"00000000", -- 00001FB8
- X"00000000", -- 00001FBC
- X"00000000", -- 00001FC0
- X"00000000", -- 00001FC4
- X"00000000", -- 00001FC8
- X"00000000", -- 00001FCC
- X"00000000", -- 00001FD0
- X"00000000", -- 00001FD4
- X"00000000", -- 00001FD8
- X"00000000", -- 00001FDC
- X"00000000", -- 00001FE0
- X"00000000", -- 00001FE4
- X"00000000", -- 00001FE8
- X"00000000", -- 00001FEC
- X"00000000", -- 00001FF0
- X"00000000", -- 00001FF4
- X"00000000", -- 00001FF8
- X"00000000" -- 00001FFC
- );
-
-begin
-
-PROM_READ:
- process(clk)
- begin
- if rising_edge(clk) and ce = '1' then
- dout <= word_array(to_integer(addr(12 downto 2)));
- end if;
- end process;
-
-end data;
diff --git a/lib/misc/sim/ModelSim SE .lnk b/lib/misc/sim/ModelSim SE .lnk
deleted file mode 100644
index 75fb6b5..0000000
Binary files a/lib/misc/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/lib/misc/sim/tb_bbfifo.fdo b/lib/misc/sim/tb_bbfifo.fdo
deleted file mode 100644
index 5a23c76..0000000
--- a/lib/misc/sim/tb_bbfifo.fdo
+++ /dev/null
@@ -1,14 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../bbfifo.vhd"
-vcom -explicit -93 "../tb_bbfifo.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_bbfifo
-do {tb_bbfifo.wdo}
-view wave
-view structure
-view signals
-run 1us
diff --git a/lib/misc/sim/tb_bbfifo.wdo b/lib/misc/sim/tb_bbfifo.wdo
deleted file mode 100644
index 06b107e..0000000
--- a/lib/misc/sim/tb_bbfifo.wdo
+++ /dev/null
@@ -1,31 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_bbfifo/rst
-add wave -noupdate -format Logic /tb_bbfifo/clk
-add wave -noupdate -format Logic /tb_bbfifo/re
-add wave -noupdate -format Logic /tb_bbfifo/we
-add wave -noupdate -format Logic /tb_bbfifo/ready
-add wave -noupdate -format Logic /tb_bbfifo/avail
-add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout
-add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/req
-add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/rdy
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_bbfifo/inst_bbfifo/bucket_array
-add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_in
-add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_out
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {170000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {76738 ps} {299465 ps}
diff --git a/lib/misc/sim/tb_ram_wb.fdo b/lib/misc/sim/tb_ram_wb.fdo
deleted file mode 100644
index 1174591..0000000
--- a/lib/misc/sim/tb_ram_wb.fdo
+++ /dev/null
@@ -1,16 +0,0 @@
-## NOTE: Do not edit this file.
-##
-vlib work
-
-# Top and TB
-vcom -explicit -93 "../ram_sim.vhd"
-vcom -explicit -93 "../ram_wb.vhd"
-vcom -explicit -93 "../tb_ram_wb.vhd"
-
-vsim -t 1ps -lib work tb_ram_wb
-do {tb_ram_wb.wdo}
-view wave
-view structure
-view signals
-run 1.5us
-
\ No newline at end of file
diff --git a/lib/misc/sim/tb_ram_wb.wdo b/lib/misc/sim/tb_ram_wb.wdo
deleted file mode 100644
index 2cdca8e..0000000
--- a/lib/misc/sim/tb_ram_wb.wdo
+++ /dev/null
@@ -1,32 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ram_wb/clk_o
-add wave -noupdate -format Logic /tb_ram_wb/rst_o
-add wave -noupdate -format Logic /tb_ram_wb/cyc_o
-add wave -noupdate -format Logic /tb_ram_wb/stb_o
-add wave -noupdate -format Logic /tb_ram_wb/we_o
-add wave -noupdate -format Literal /tb_ram_wb/sel_o
-add wave -noupdate -format Logic /tb_ram_wb/ack_i
-add wave -noupdate -format Logic /tb_ram_wb/mrdy_o
-add wave -noupdate -format Logic /tb_ram_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg
-add wave -noupdate -format Literal /tb_ram_wb/dout_cnt
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {950000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {1575 ns}
diff --git a/lib/misc/sim/tb_rom_wb.fdo b/lib/misc/sim/tb_rom_wb.fdo
deleted file mode 100644
index e8732f0..0000000
--- a/lib/misc/sim/tb_rom_wb.fdo
+++ /dev/null
@@ -1,16 +0,0 @@
-## NOTE: Do not edit this file.
-##
-vlib work
-
-# Top and TB
-vcom -explicit -93 "../rom_sim.vhd"
-vcom -explicit -93 "../rom_wb.vhd"
-vcom -explicit -93 "../tb_rom_wb.vhd"
-
-vsim -t 1ps -lib work tb_rom_wb
-do {tb_rom_wb.wdo}
-view wave
-view structure
-view signals
-run 1us
-
\ No newline at end of file
diff --git a/lib/misc/sim/tb_rom_wb.wdo b/lib/misc/sim/tb_rom_wb.wdo
deleted file mode 100644
index b8663ed..0000000
--- a/lib/misc/sim/tb_rom_wb.wdo
+++ /dev/null
@@ -1,29 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_rom_wb/clk_o
-add wave -noupdate -format Logic /tb_rom_wb/rst_o
-add wave -noupdate -format Logic /tb_rom_wb/cyc_o
-add wave -noupdate -format Logic /tb_rom_wb/stb_o
-add wave -noupdate -format Logic /tb_rom_wb/ack_i
-add wave -noupdate -format Logic /tb_rom_wb/mrdy_o
-add wave -noupdate -format Logic /tb_rom_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dout_reg
-add wave -noupdate -format Literal /tb_rom_wb/dout_cnt
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {796036 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {1050 ns}
diff --git a/lib/misc/singleshot.vhd b/lib/misc/singleshot.vhd
deleted file mode 100644
index 25f7013..0000000
--- a/lib/misc/singleshot.vhd
+++ /dev/null
@@ -1,155 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 21:52:19 10/22/05
--- Design Name:
--- Module Name: singleshot - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
--- Component Template
---
--- COMPONENT singleshot
--- GENERIC (mode : integer);
--- PORT(
--- rst : IN std_logic;
--- clk : IN std_logic;
--- input : IN std_logic;
--- output : OUT std_logic
--- );
--- END COMPONENT;
---
--- Instantation Template
---
--- singleshot_int: oneshot
--- GENERIC MAP (
--- mode => 1)
--- PORT MAP(
--- rst => ,
--- clk => ,
--- input => ,
--- output =>
--- );
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity singleshot is
- Generic ( mode : integer range 0 to 2 := 1);
- Port ( rst : in std_logic;
- clk : in std_logic;
- input : in std_logic;
- output : out std_logic);
-end singleshot;
-
-architecture Behavioral of singleshot is
-
-type s_t is (idle, shot_in, active, shot_out);
-signal s, sn : s_t;
-
-begin
-
-process (rst, clk, sn)
-begin
- if rising_edge(clk) then
- if rst = '1' then
- s <= idle;
- else
- s <= sn;
- end if;
- end if;
-end process;
-
-mode_1:
-if mode = 1 generate
-begin
- process (input, s)
- begin
- output <= '0';
- sn <= s;
- case s is
- when idle =>
- if input = '1' then
- sn <= shot_in;
- end if;
- when shot_in =>
- output <= '1';
- sn <= active;
- when active =>
- if input = '0' then
- sn <= shot_out;
- end if;
- when shot_out =>
- sn <= idle;
- when others => null;
- end case;
- end process;
-end generate;
-
-mode_0:
-if mode = 0 generate
-begin
- process (input, s)
- begin
- output <= '0';
- sn <= s;
- case s is
- when idle =>
- if input = '1' then
- sn <= shot_in;
- end if;
- when shot_in =>
- sn <= active;
- when active =>
- if input = '0' then
- sn <= shot_out;
- end if;
- when shot_out =>
- output <= '1';
- sn <= idle;
- when others => null;
- end case;
- end process;
-end generate;
-
-mode_2:
-if mode = 2 generate
-begin
- process (input, s)
- begin
- output <= '0';
- sn <= s;
- case s is
- when idle =>
- if input = '1' then
- sn <= shot_in;
- end if;
- when shot_in =>
- output <= '1';
- sn <= active;
- when active =>
- if input = '0' then
- sn <= shot_out;
- end if;
- when shot_out =>
- output <= '1';
- sn <= idle;
- when others => null;
- end case;
- end process;
-end generate;
-
-end Behavioral;
diff --git a/lib/misc/tb_bbfifo.vhd b/lib/misc/tb_bbfifo.vhd
deleted file mode 100644
index 95fa7b9..0000000
--- a/lib/misc/tb_bbfifo.vhd
+++ /dev/null
@@ -1,136 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity tb_bbfifo is
-end;
-
-architecture behave of tb_bbfifo is
-
- -- Number of user data words for simulation
- constant CLK_PERIOD : time := 10 ns;
-
- signal rst : std_logic := '1';
- signal clk : std_logic := '1';
- signal re : std_logic := '0';
- signal we : std_logic := '0';
- signal ready : std_logic;
- signal avail : std_logic;
- signal din : unsigned(7 downto 0) := (others => '0');
- signal dout : unsigned(7 downto 0);
- signal dout_reg : unsigned(7 downto 0);
-
-
-begin
-
-inst_bbfifo : entity work.bbfifo
- GENERIC MAP
- (
- depth => 4,
- data_width => 8
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- re => re,
- we => we,
- ready => ready,
- avail => avail,
- din => din,
- dout => dout
- );
-
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- clk <= not clk;
- end process;
-
-RE_GEN: process
- begin
- wait for 2*CLK_PERIOD;
- wait until rising_edge(clk) and avail = '1';
- re <= '0';
- dout_reg <= dout;
- wait until rising_edge(clk);
- re <= '0';
- end process;
-
-------------------------------------------------------------------------------------------
-
-STIMULUS: process
-
-
- begin
-
- wait for 3*CLK_PERIOD;
- rst <= '0';
- din <= X"10";
- wait until rising_edge(clk) and ready = '1';
- we <= '1';
- wait until rising_edge(clk) and ready = '1';
- din <= din + 1;
- wait until rising_edge(clk) and ready = '1';
- we <= '0';
- wait until rising_edge(clk) and ready = '1';
- wait until rising_edge(clk) and ready = '1';
- we <= '1';
- din <= din + 1;
- wait until rising_edge(clk) and ready = '1';
- din <= din + 1;
- wait until rising_edge(clk) and ready = '1';
- we <= '0';
- wait until rising_edge(clk) and ready = '1';
- wait until rising_edge(clk) and ready = '1';
- wait until rising_edge(clk) and ready = '1';
- wait until rising_edge(clk) and ready = '1';
- we <= '1';
- din <= din + 1;
- wait until rising_edge(clk) and ready = '1';
- we <= '1';
- din <= din + 1;
- wait until rising_edge(clk) and ready = '1';
- we <= '1';
- din <= din + 1;
- wait until rising_edge(clk) and ready = '1';
- we <= '1';
- din <= din + 1;
- wait until rising_edge(clk) and ready = '1';
- we <= '1';
- din <= din + 1;
- wait until rising_edge(clk) and ready = '1';
- we <= '1';
- din <= din + 1;
- wait until rising_edge(clk) and ready = '1';
-
-
- wait;
-
- end process;
-
-end architecture behave;
diff --git a/lib/misc/tb_ram_wb.vhd b/lib/misc/tb_ram_wb.vhd
deleted file mode 100644
index b165069..0000000
--- a/lib/misc/tb_ram_wb.vhd
+++ /dev/null
@@ -1,408 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-ENTITY tb_ram_wb IS
-END tb_ram_wb;
-
-ARCHITECTURE behavior OF tb_ram_wb IS
-
- constant CLK_PERIOD : time := 10 ns;
- signal CLK_O : std_logic := '1';
- signal RST_O : std_logic := '1';
- signal CYC_O : std_logic := '0';
- signal STB_O : std_logic := '0';
- signal WE_O : std_logic := '0';
- signal SEL_O : unsigned(3 downto 0) := (others => '1');
- signal ACK_I : std_logic;
- signal MRDY_O : std_logic := '1';
- signal SRDY_I : std_logic;
- signal ADDR_O : unsigned(31 downto 0) := (others => '-');
- signal DAT_I : unsigned(31 downto 0);
- signal DAT_O : unsigned(31 downto 0) := (others => '-');
-
- signal dout_rst : std_logic := '0';
- signal dout_reg : unsigned(31 downto 0);
- signal dout_cnt : natural range 0 to 255;
-
-BEGIN
-
-inst_ram_wb : entity work.ram_wb
- PORT MAP
- (
- RST_I => RST_O,
- CLK_I => CLK_O,
- CYC_I => CYC_O,
- STB_I => STB_O,
- SEL_I => SEL_O,
- WE_I => WE_O,
- ACK_O => ACK_I,
- SRDY_O => SRDY_I,
- MRDY_I => MRDY_O,
- ADDR_I => ADDR_O,
- DAT_I => DAT_O,
- DAT_O => DAT_I
- );
-
-read_register:
- process(CLK_O)
- begin
- if rising_edge(CLK_O) then
- if dout_rst = '1' then
- dout_cnt <= 0;
- elsif ACK_I = '1' and WE_O = '0' then
- dout_reg <= DAT_I;
- dout_cnt <= dout_cnt + 1;
- end if;
- end if;
- end process;
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- CLK_O <= not CLK_O;
- end process;
-
-STIMULUS: process
-
- begin
-
- wait for 3*CLK_PERIOD;
- RST_O <= '0';
-
- -- 8 single cycles
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '1';
- DAT_O <= X"1234_0000";
- ADDR_O <= X"0000_0000";
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- DAT_O <= DAT_O + 1;
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
- wait until rising_edge(CLK_O) and ACK_I = '1';
- CYC_O <= '0';
-
-
- -- 8-word burst cycle
- wait for 3*CLK_PERIOD;
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '0';
- ADDR_O <= X"0000_0000";
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
-
- wait until rising_edge(CLK_O) and dout_cnt = 7;
- CYC_O <= '0';
-
- wait for 3*CLK_PERIOD;
- wait until rising_edge(CLK_O);
- -- 1-word burst cycle
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '1';
- SEL_O <= "0011";
- ADDR_O <= X"0000_0080";
- DAT_O <= X"DEADBEEF";
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
- wait until rising_edge(CLK_O) and ACK_I = '1';
- CYC_O <= '0';
-
- wait for 3*CLK_PERIOD;
- wait until rising_edge(CLK_O);
- -- 1-word burst cycle
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '0';
- ADDR_O <= X"0000_0080";
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
- wait until rising_edge(CLK_O) and ACK_I = '1';
- CYC_O <= '0';
-
- -- 8-word burst cycle
- wait for 3*CLK_PERIOD;
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
- CYC_O <= '1';
- STB_O <= '1';
- WE_O <= '0';
- ADDR_O <= X"0000_0000";
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
- MRDY_O <= '0';
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '1';
- MRDY_O <= '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
-
- wait until rising_edge(CLK_O) and dout_cnt = 54;
- CYC_O <= '0';
-
- wait;
-
- end process;
-
-END;
diff --git a/lib/misc/tb_rom_wb.vhd b/lib/misc/tb_rom_wb.vhd
deleted file mode 100644
index 0e414f9..0000000
--- a/lib/misc/tb_rom_wb.vhd
+++ /dev/null
@@ -1,223 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-ENTITY tb_rom_wb IS
-END tb_rom_wb;
-
-ARCHITECTURE behavior OF tb_rom_wb IS
-
- constant CLK_PERIOD : time := 10 ns;
- signal CLK_O : std_logic := '1';
- signal RST_O : std_logic := '1';
- signal CYC_O : std_logic := '0';
- signal STB_O : std_logic := '0';
- signal ACK_I : std_logic;
- signal MRDY_O : std_logic := '1';
- signal SRDY_I : std_logic;
- signal ADDR_O : unsigned(31 downto 0) := (others => '-');
- signal DAT_I : unsigned(31 downto 0);
-
- signal dout_rst : std_logic := '0';
- signal dout_reg : unsigned(31 downto 0);
- signal dout_cnt : natural range 0 to 255;
-
-BEGIN
-
-inst_rom_wb : entity work.rom_wb
- PORT MAP
- (
- RST_I => RST_O,
- CLK_I => CLK_O,
- CYC_I => CYC_O,
- STB_I => STB_O,
- ACK_O => ACK_I,
- SRDY_O => SRDY_I,
- MRDY_I => MRDY_O,
- ADDR_I => ADDR_O,
- DAT_O => DAT_I
- );
-
-read_register:
- process(CLK_O)
- begin
- if rising_edge(CLK_O) then
- if dout_rst = '1' then
- dout_cnt <= 0;
- elsif ACK_I = '1' then
- dout_reg <= DAT_I;
- dout_cnt <= dout_cnt + 1;
- end if;
- end if;
- end process;
-
-CLK_GEN: process
- begin
- wait for CLK_PERIOD/2;
- CLK_O <= not CLK_O;
- end process;
-
-STIMULUS: process
-
- begin
-
- wait for 3*CLK_PERIOD;
- RST_O <= '0';
-
- -- 8-word burst cycle
- wait for 3*CLK_PERIOD;
- dout_rst <= '1';
- wait until rising_edge(CLK_O);
- dout_rst <= '0';
- CYC_O <= '1';
- STB_O <= '1';
- ADDR_O <= X"0000_0180";
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
- MRDY_O <= '0';
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '1';
- MRDY_O <= '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- ADDR_O <= ADDR_O + 4;
- wait until rising_edge(CLK_O) and SRDY_I = '1';
- STB_O <= '0';
-
- wait until rising_edge(CLK_O) and dout_cnt = 54;
- CYC_O <= '0';
-
- wait;
-
- end process;
-
-END;
diff --git a/lib/misc/tb_template.vhd b/lib/misc/tb_template.vhd
deleted file mode 100644
index f96f294..0000000
--- a/lib/misc/tb_template.vhd
+++ /dev/null
@@ -1,63 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.MATH_REAL.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE STD.TEXTIO.ALL;
-
--- LIBRARY WORK;
--- USE.YOURLIB.WHATELSE
-
-ENTITY tb_template IS
-END tb_template;
-
-ARCHITECTURE behavior OF tb_template IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT your_comp
- GENERIC
- (
- );
- PORT
- (
- );
- END COMPONENT;
-
- --Constants
- constant PERIOD : time := 10 ns;
-
- --Inputs
- signal clk : STD_LOGIC := '0';
-
- --Outputs
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: your_comp
- GENERIC MAP
- (
- )
- PORT MAP
- (
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
-
- END PROCESS;
-
-END tb_template;
diff --git a/lib/misc/utils_pkg.vhd b/lib/misc/utils_pkg.vhd
deleted file mode 100644
index 7212852..0000000
--- a/lib/misc/utils_pkg.vhd
+++ /dev/null
@@ -1,196 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010-03-22 07:25:40 Jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
-package utils_pkg is
-
- -- Constants
-
- -- Functions
- function MIN (X, Y: INTEGER) return INTEGER;
- function MAX (X, Y: INTEGER) return INTEGER;
-
- function NextPowerOfTwo(x : real) return real;
- function NextExpBaseTwo(x : real) return real;
- function NextPowerOfTwo(x : natural) return natural;
- function NextExpBaseTwo(x : natural) return natural;
- function GCD(a, b : natural) return natural;
- function LCM(a, b : natural) return natural;
- function UTILS_PERIOD_NS(f_in_MHz : real) return real;
- function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
- function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
- function f_correct(f : real) return natural;
-
-end utils_pkg;
-
-
-package body utils_pkg is
-
- -------------------------------------------------------------
- function MIN (X, Y: INTEGER) return INTEGER is
- variable res : integer := X;
- begin
- if Y < X then
- res := Y;
- end if;
-
- return res;
-
- end MIN;
-
- -------------------------------------------------------------
- function MAX (X, Y: INTEGER) return INTEGER is
- variable res : integer := X;
- begin
- if Y > X then
- res := Y;
- end if;
-
- return res;
-
- end MAX;
-
- -------------------------------------------------------------
- function NextExpBaseTwo(x : real) return real is
- begin
- return ceil(log2(x));
- end NextExpBaseTwo;
-
- -------------------------------------------------------------
- function NextPowerOfTwo(x : real) return real is
- begin
-
- return 2.0**NextExpBaseTwo(x);
- end NextPowerOfTwo;
-
- -------------------------------------------------------------
- function NextExpBaseTwo(x : natural) return natural is
- begin
- return natural(NextExpBaseTwo(real(x)));
- end NextExpBaseTwo;
-
- -------------------------------------------------------------
- function NextPowerOfTwo(x : natural) return natural is
- begin
-
- return 2**NextExpBaseTwo(x);
- end NextPowerOfTwo;
-
- -------------------------------------------------------------
- function GCD(a, b : natural) return natural is
- variable aa : natural;
- variable bb : natural;
- begin
- aa := a;
- bb := b;
- while bb /= 0 loop
- if aa > bb then
- aa := aa - bb;
- else
- bb := bb - aa;
- end if;
- end loop;
-
- return aa;
-
- end GCD;
-
- -------------------------------------------------------------
- function LCM(a, b : natural) return natural is
- begin
-
- return (a * b)/GCD(a, b);
-
- end LCM;
-
- -------------------------------------------------------------
- function UTILS_PERIOD_NS(f_in_MHz : real) return real is
- begin
-
- return 1.0E3/f_in_MHz;
-
- end UTILS_PERIOD_NS;
-
- -------------------------------------------------------------
- function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
- variable f_in : natural;
- variable f_out : natural;
- variable C : natural;
- variable M : natural;
- variable D : natural;
- begin
- C := f_correct(f_out_MHz);
- if C < 2 then
- C := f_correct(f_in_MHz);
- end if;
-
- f_out := natural(ceil(real(C)*f_out_MHz));
- f_in := natural(ceil(real(C)*f_in_MHz));
-
- M := LCM(f_in, f_out)/f_in;
- D := f_in/GCD(f_in, f_out);
-
- assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
-
- if M = 1 then
- M := 2;
- end if;
-
- return M;
-
- end UTILS_FREQ_M;
-
- -------------------------------------------------------------
- function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
- variable f_in : natural;
- variable f_out : natural;
- variable C : natural;
- variable M : natural;
- variable D : natural;
- begin
- C := f_correct(f_out_MHz);
- if C < 2 then
- C := f_correct(f_in_MHz);
- end if;
-
- f_out := natural(ceil(real(C)*f_out_MHz));
- f_in := natural(ceil(real(C)*f_in_MHz));
-
- M := LCM(f_in, f_out)/f_in;
- D := f_in/GCD(f_in, f_out);
-
- assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
-
- if M = 1 then
- D := 2*D;
- end if;
-
- return D;
-
- end UTILS_FREQ_D;
-
- -------------------------------------------------------------
- function f_correct(f : real) return natural is
- constant MAX_ITER : positive := 100;
- constant MAX_ERR : real := 0.01;
- variable fpart : real;
- variable err : real;
- begin
- for i in 1 to MAX_ITER loop
- fpart := real(i)*f - ceil(real(i)*f);
- err := abs(fpart);
- if err < max_err then
- return i;
- end if;
- end loop;
- end f_correct;
-
- -------------------------------------------------------------
-end utils_pkg;
-
-
diff --git a/lib/ps2_port/src/ps2_core.vhd b/lib/ps2_port/src/ps2_core.vhd
index 9a3dab0..d6d749f 100644
--- a/lib/ps2_port/src/ps2_core.vhd
+++ b/lib/ps2_port/src/ps2_core.vhd
@@ -29,7 +29,7 @@ USE IEEE.NUMERIC_STD.ALL;
entity ps2_core is
Generic
(
- f_sys_clk : real := 100.0
+ f_sys_clk_hz : integer := 100E6
);
Port
(
@@ -69,7 +69,7 @@ type line_state_tx_t is (tx_idle_st, tx_clock_assert_st, tx_start_latency_st,
tx_ack_trans_st, tx_ack_sample_st, tx_valid_st);
-- Constant
-constant prescaler_us : integer := integer(f_sys_clk);
+constant prescaler_us : integer := f_sys_clk_hz/1E6;
constant timeout_us : integer := 15000;
constant time_clock_assert : integer := 120;
constant time_clock_abort : integer := 500;
diff --git a/lib/ps2_port/src/ps2_wb.vhd b/lib/ps2_port/src/ps2_wb.vhd
index af42d75..34f0cbb 100644
--- a/lib/ps2_port/src/ps2_wb.vhd
+++ b/lib/ps2_port/src/ps2_wb.vhd
@@ -5,7 +5,7 @@ USE IEEE.NUMERIC_STD.ALL;
ENTITY ps2_wb IS
Generic
(
- f_sys_clk : real := 100.0
+ f_sys_clk_hz : integer := 100E6
);
Port
(
@@ -118,7 +118,7 @@ irq_register:
inst_ps2_core: entity work.ps2_core
GENERIC MAP
(
- f_sys_clk => f_sys_clk
+ f_sys_clk_hz => f_sys_clk_hz
)
PORT MAP
(
diff --git a/lib/radio/cordic/eval_cordic.m b/lib/radio/cordic/eval_cordic.m
deleted file mode 100644
index 8754ccd..0000000
--- a/lib/radio/cordic/eval_cordic.m
+++ /dev/null
@@ -1,171 +0,0 @@
-function eval_cordic(Nmax, doplot)
-N = 100;
-
-arctan_tbl = (atan(2.^-(0:N-1))/pi)'
-%gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))'
-
-% Rotation mode
-disp('Rotation:')
-for i=1:N,
- phi(i) = 2*pi*(i-N/2)/N;
- [x(i),y(i)] = cordic_rot(0, 1, phi(i), Nmax, 0);
-end;
-close all;
-figure
-plot(1:N, x, 1:N, y);
-legend('x','y')
-grid;
-
-% Vector mode
-disp('Magnitude and phase:')
-for i=1:N,
- [mag(i), phi(i)] = cordic_vec(x(i), y(i), Nmax, 0);
-end;
-figure
-plot(1:N, mag, 1:N, phi);
-legend('Magnitude','Phase')
-grid;
-
-
-% ------------------------------------------------------------
-function [mag, phi] = cordic_cart2polar(x, y, Nmax, doplot)
- [mag, phi] = cordic_vec(x, y, Nmax, doplot);
-
-% ------------------------------------------------------------
-function [x, y] = cordic_polar2cart(mag, phi, Nmax, doplot)
- [mag, phi] = cordic_vec(x, y, Nmax, doplot);
-
-% ------------------------------------------------------------
-function [xout, yout] = cordic_rot(xin, yin, phi, N, doplot)
-
- % Initialize
- arctan_tbl = atan(2.^-(0:N-1));
- gain_tbl = 1./cumprod(sqrt(1+2.^-(2*(0:N-1))));
-
- coeffs = arctan_tbl';
- gains = gain_tbl';
-
- % Calculate initial rotation
- if (phi < (-pi/2))
- z = phi + pi;
- x = -xin;
- y = -yin;
- else
- if (phi > pi/2)
- z = phi - pi;
- x = -xin;
- y = -yin;
- else
- x = xin;
- y = yin;
- z = phi;
- end;
- end;
-
- % Loop
- for i=1:N,
- xi(i) = x;
- yi(i) = y;
- zi(i) = z;
-
- S = 2^(-(i-1));
- if (z < 0)
- t = x + y*S;
- y = y - x*S;
- z = z + arctan_tbl(i);
- x = t;
- else
- t = x - y*S;
- y = y + x*S;
- z = z - arctan_tbl(i);
- x = t;
- end;
-
- end;
-
- % Result
- k = gain_tbl(i);
- xout = k*x;
- yout = k*y;
-
- % Output
- if(doplot)
- close all;
- figure(1);
- plot(1:N, xi, 1:N, yi, 1:N, zi)
- legend('x','y','z');
- title('Convergence');
- grid;
-
- figure(2);
- plot(xi.*gain_tbl, yi.*gain_tbl, '-x')
- title('Polar plot');
- grid;
- end;
-
-% ------------------------------------------------------------
-function [mag, phi] = cordic_vec(xin, yin, N, doplot)
-
- % Initialize
- arctan_tbl = atan(2.^-(0:N-1));
- gain_tbl = 1./cumprod(sqrt(1+2.^-(2*(0:N-1))));
-
- coeffs = arctan_tbl';
- gains = gain_tbl';
-
- % Calculate initial rotation
- if (xin < 0)
- x = -xin;
- y = -yin;
- if (yin < 0)
- z = -pi;
- else
- z = pi;
- end;
- else
- x = xin;
- y = yin;
- z = 0;
- end;
-
- % Loop
- for i=1:N,
- xi(i) = x;
- yi(i) = y;
- zi(i) = z;
-
- S = 2^(-(i-1));
- if (y < 0)
- t = x - y*S;
- y = y + x*S;
- z = z - arctan_tbl(i);
- x = t;
- else
- t = x + y*S;
- y = y - x*S;
- z = z + arctan_tbl(i);
- x = t;
- end;
-
- end;
-
- % Result
- k = gain_tbl(i);
- mag = k*x;
- phi = z;
-
- % Output
- if(doplot)
- close all;
- figure(1);
- plot(1:N, xi, 1:N, yi, 1:N, zi)
- legend('x','y','z');
- title('Convergence');
- grid;
-
- figure(2);
- plot(xi.*gain_tbl, yi.*gain_tbl, '-x')
- title('Polar plot');
- grid;
- end;
-
\ No newline at end of file
diff --git a/lib/radio/cordic/sim/eval_cordic.m b/lib/radio/cordic/sim/eval_cordic.m
deleted file mode 100644
index dc42068..0000000
--- a/lib/radio/cordic/sim/eval_cordic.m
+++ /dev/null
@@ -1,10 +0,0 @@
-% function eval_cordic(x0,y0,z0, mode)
-function eval_cordic(x0,y0,z0, mode)
-
-if (mode == 'rot')
- Xn = x0*cos(z0) - y0*sin(z0)
- Yn = y0*cos(z0) + x0*sin(z0)
-else
- Xn = sqrt(x0^2 + y0^2)
- Yn = z0 + atan(y0/x0)
-end;
\ No newline at end of file
diff --git a/lib/radio/cordic/sim/tb_cordic_pipe_top.fdo b/lib/radio/cordic/sim/tb_cordic_pipe_top.fdo
deleted file mode 100644
index 562789d..0000000
--- a/lib/radio/cordic/sim/tb_cordic_pipe_top.fdo
+++ /dev/null
@@ -1,18 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/cordic_pkg.vhd"
-vcom -explicit -93 "../src/cordic_pipe_stage.vhd"
-vcom -explicit -93 "../src/cordic_pipe_pre.vhd"
-vcom -explicit -93 "../src/cordic_pipe_post.vhd"
-vcom -explicit -93 "../src/cordic_pipe_top.vhd"
-vcom -explicit -93 "../src/tb_cordic_pipe_top.vhd"
-vsim -t 1ps -lib work tb_cordic_pipe_top
-do {tb_cordic_pipe_top.wdo}
-view wave
-view structure
-view signals
-run 2000us
diff --git a/lib/radio/cordic/sim/tb_cordic_pipe_top.wdo b/lib/radio/cordic/sim/tb_cordic_pipe_top.wdo
deleted file mode 100644
index 3e65178..0000000
--- a/lib/radio/cordic/sim/tb_cordic_pipe_top.wdo
+++ /dev/null
@@ -1,37 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cordic_pipe_top/clk
-add wave -noupdate -format Logic /tb_cordic_pipe_top/rst
-add wave -noupdate -format Logic /tb_cordic_pipe_top/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/xin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/yin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/zin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/xout
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/yout
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/zout
-add wave -noupdate -format Logic /tb_cordic_pipe_top/vld_out
-add wave -noupdate -divider {Pre stage}
-add wave -noupdate -format Logic /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/vld_in
-add wave -noupdate -format Logic /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/xin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/yin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/zin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/xout
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/yout
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/zout
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {10770000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {48466483 ps}
diff --git a/lib/radio/cordic/sim/tb_cordic_top.fdo b/lib/radio/cordic/sim/tb_cordic_top.fdo
deleted file mode 100644
index 1cb5c84..0000000
--- a/lib/radio/cordic/sim/tb_cordic_top.fdo
+++ /dev/null
@@ -1,19 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/cordic_pkg.vhd"
-vcom -explicit -93 "../src/cordic_rom.vhd"
-vcom -explicit -93 "../src/cordic_stage.vhd"
-vcom -explicit -93 "../src/cordic_stage_pre.vhd"
-vcom -explicit -93 "../src/cordic_stage_post.vhd"
-vcom -explicit -93 "../src/cordic_top.vhd"
-vcom -explicit -93 "../src/tb_cordic_top.vhd"
-vsim -t 1ps -lib work tb_cordic_top
-do {tb_cordic_top.wdo}
-view wave
-view structure
-view signals
-run 2000us
diff --git a/lib/radio/cordic/sim/tb_cordic_top.wdo b/lib/radio/cordic/sim/tb_cordic_top.wdo
deleted file mode 100644
index 6cec344..0000000
--- a/lib/radio/cordic/sim/tb_cordic_top.wdo
+++ /dev/null
@@ -1,64 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider Top
-add wave -noupdate -format Literal /tb_cordic_top/uut/cordic_mode
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/zin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/xout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/yout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/zout
-add wave -noupdate -format Logic /tb_cordic_top/ce
-add wave -noupdate -format Logic /tb_cordic_top/valid
-add wave -noupdate -divider {Pre stage}
-add wave -noupdate -format Literal /tb_cordic_top/uut/inst_cordic_stage_pre/cordic_mode
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/zin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/xout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/yout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/zout
-add wave -noupdate -divider {Process stage}
-add wave -noupdate -format Literal /tb_cordic_top/uut/count
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/coeff
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/zin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/xout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/yout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/zout
-add wave -noupdate -divider {Post stage}
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/zin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/xout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/yout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/zout
-add wave -noupdate -divider Signals
-add wave -noupdate -format Logic /tb_cordic_top/uut/ce
-add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_ready
-add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_en
-add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_valid
-add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_ready
-add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_en
-add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_valid
-add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_ready
-add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_en
-add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_valid
-add wave -noupdate -format Literal /tb_cordic_top/uut/state
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1463518 ps} 0}
-configure wave -namecolwidth 184
-configure wave -valuecolwidth 124
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {655140 ps} {1967644 ps}
diff --git a/lib/radio/cordic/sim/tb_results.m b/lib/radio/cordic/sim/tb_results.m
deleted file mode 100644
index 9f68f7c..0000000
--- a/lib/radio/cordic/sim/tb_results.m
+++ /dev/null
@@ -1,34 +0,0 @@
-% Read data
-X = TEXTREAD('x.txt');
-Y = TEXTREAD('y.txt');
-Z = TEXTREAD('z.txt');
-
-% Output
-close all;
-plot(0:length(X)-1, X, 0:length(Y)-1, Y, 0:length(Z)-1, Z);
-title ('Output');
-legend('X','Y','Z');
-grid;
-
-W= 2*pi/100;
-phi = 0;
-
-xd = -cos(phi+W*(0:length(X)-1))';
-yd = -sin(phi+W*(0:length(Y)-1))';
-
-VarErrorX = var(X-xd)
-VarErrorY = var(Y-yd)
-MeanErrorX = mean(X-xd)
-MeanErrorY = mean(Y-yd)
-
-figure;
-plot(0:length(X)-1, X-xd, 0:length(Y)-1, Y-yd, 0:length(Z)-1, Z);
-title ('Error');
-legend('X - X_D','Y - Y_D', 'Z');
-grid;
-
-figure;
-plot(0:length(X)-1, X, 0:length(Y)-1, Y, 0:length(Z)-1, xd, 0:length(yd)-1, yd);
-title ('Output');
-legend('X','Y','X_D','Y_D');
-grid;
diff --git a/lib/radio/cordic/src/cordic_pipe_post.vhd b/lib/radio/cordic/src/cordic_pipe_post.vhd
deleted file mode 100644
index c1203cc..0000000
--- a/lib/radio/cordic/src/cordic_pipe_post.vhd
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage_pre - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_pipe_post is
-Generic
-(
- cordic_mode : cordic_mode_t := cordic_mode_rotate;
- nstages : integer := 0;
- nbits_x : integer := 8;
- nbits_x_frac : integer := 6;
- nbits_y : integer := 8;
- nbits_y_frac : integer := 6;
- nbits_z : integer := 8;
- nbits_z_frac : integer := 8
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- vld_out : out std_logic
-);
-end cordic_pipe_post;
-
-architecture Behavioral of cordic_pipe_post is
-
-constant gain_x : sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_x, nbits_x_frac), fixed_wrap, fixed_round);
-constant gain_y : sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_y, nbits_y_frac), fixed_wrap, fixed_round);
-
-------------------------------------------------------------
-begin
-
-------------------------------------------------------------
-cordic_proc_pre_stage:
- process(clk)
- variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
- variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
- variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
-
- begin
-
- if rising_edge(clk) then
- vld_out <= '0';
- if rst = '1' then
- xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
- yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
- zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
- elsif vld_in = '1' then
-
- vld_out <= '1';
-
- xi := resize(xin, xi);
- yi := resize(yin, yi);
- zi := resize(zin, zi);
-
- xo := resize(xi * gain_x, xo, cordic_saturate_mode, cordic_round_mode);
- yo := resize(yi * gain_y, yo, cordic_saturate_mode, cordic_round_mode);
- zo := zi;
-
- xout <= xo after tpd;
- yout <= yo after tpd;
- zout <= zo after tpd;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_pipe_pre.vhd b/lib/radio/cordic/src/cordic_pipe_pre.vhd
deleted file mode 100644
index ae03c5e..0000000
--- a/lib/radio/cordic/src/cordic_pipe_pre.vhd
+++ /dev/null
@@ -1,137 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage_pre - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_pipe_pre is
-Generic
-(
- cordic_mode : cordic_mode_t := cordic_mode_rotate;
- z_range : real := pi;
- nbits_x : integer := 8;
- nbits_x_frac : integer := 6;
- nbits_y : integer := 8;
- nbits_y_frac : integer := 6;
- nbits_z : integer := 8;
- nbits_z_frac : integer := 8
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- vld_out : out std_logic
-);
-end cordic_pipe_pre;
-
-architecture Behavioral of cordic_pipe_pre is
-
-constant pi_sfix : sfixed := to_sfixed(z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round);
-constant pi2_sfix : sfixed := to_sfixed(z_range/2.0, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round);
-
-------------------------------------------------------------
-begin
-
-------------------------------------------------------------
-cordic_proc_pre_stage:
- process(clk)
- variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
- variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
- variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
-
- begin
-
- if rising_edge(clk) then
- vld_out <= '0';
- if rst = '1' then
- xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
- yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
- zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
- elsif vld_in = '1' then
-
- vld_out <= '1';
-
- xi := xin;
- yi := yin;
- zi := zin;
-
- xo := xi;
- yo := yi;
- zo := zi;
-
- if (zi < -pi2_sfix) then
- xo := resize(-xi, xo);
- yo := resize(-yi, yo);
- zo := resize(zi + pi_sfix, zo);
- elsif (zi > pi2_sfix) then
- xo := resize(-xi, xo);
- yo := resize(-yi, yo);
- zo := resize(zi - pi_sfix, zo);
- end if;
-
- xout <= xo after tpd;
- yout <= yo after tpd;
- zout <= zo after tpd;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
-
--- if (y < 0) then
--- x' = -y
--- y' = x
--- z' = z + pi/2;
--- else
--- x' = y
--- y' = -x
--- z' = z - pi/2;
--- end if;
---
--- if (x < 0) then
--- x' = -x;
--- y' = -y;
--- z' = z - pi
--- else
--- x' = x;
--- y' = y;
--- z' = z
--- end if;
diff --git a/lib/radio/cordic/src/cordic_pipe_stage.vhd b/lib/radio/cordic/src/cordic_pipe_stage.vhd
deleted file mode 100644
index 0428f8a..0000000
--- a/lib/radio/cordic/src/cordic_pipe_stage.vhd
+++ /dev/null
@@ -1,115 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_pipe_stage is
-Generic
-(
- cordic_mode : cordic_mode_t := cordic_mode_rotate;
- z_range : real := pi;
- stage_num : integer := 0;
- nbits_x : integer := 8;
- nbits_x_frac : integer := 6;
- nbits_y : integer := 8;
- nbits_y_frac : integer := 6;
- nbits_z : integer := 8;
- nbits_z_frac : integer := 8
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- vld_out : out std_logic
-);
-end cordic_pipe_stage;
-
-architecture Behavioral of cordic_pipe_stage is
-
-constant coeff : sfixed := to_sfixed(arctan_tbl(stage_num)*z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round);
-
-begin
-
-------------------------------------------------------------
-cordic_proc_stage:
- process(clk)
- variable xi, xt, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
- variable yi, yt, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
- variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
-
- begin
-
- if rising_edge(clk) then
- vld_out <= '0';
- if rst = '1' then
- xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
- yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
- zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
- elsif vld_in = '1' then
-
- vld_out <= '1';
-
- xi := xin;
- yi := yin;
- zi := zin;
-
- xt := xi sra stage_num;
- yt := yi sra stage_num;
-
- if zi(zi'high) = '1' then
- xo := resize(xi + yt, xo);
- yo := resize(yi - xt, yo);
- zo := resize(zi + coeff, zo);
- else
- xo := resize(xi - yt, xo);
- yo := resize(yi + xt, yo);
- zo := resize(zi - coeff, zo);
- end if;
-
- xout <= xo after tpd;
- yout <= yo after tpd;
- zout <= zo after tpd;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_pipe_top.vhd b/lib/radio/cordic/src/cordic_pipe_top.vhd
deleted file mode 100644
index e4b73f8..0000000
--- a/lib/radio/cordic/src/cordic_pipe_top.vhd
+++ /dev/null
@@ -1,319 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 11:52:30 10/02/05
--- Design Name:
--- Module Name: cordic_top - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity cordic_pipe_top is
-Generic
-(
- cordic_mode : cordic_mode_t := cordic_mode_rotate;
- z_range : real := 1.0;
- gain_corr_mode : gain_corr_mode_t := gain_mode_disabled;
- nstages : integer := 18;
- nbits_x_in : integer := 18;
- nbits_y_in : integer := 18;
- nbits_z_in : integer := 18;
- nbits_frac_x_in : integer := 16;
- nbits_frac_y_in : integer := 16;
- nbits_frac_z_in : integer := 16;
- nbits_x_out : integer := 18;
- nbits_y_out : integer := 18;
- nbits_z_out : integer := 18;
- nbits_frac_x_out : integer := 17;
- nbits_frac_y_out : integer := 17;
- nbits_frac_z_out : integer := 17
-);
-Port
-(
- rst : in std_logic;
- clk : in std_logic;
- vld_in : in std_logic;
- xin : in sfixed(shi(nbits_x_in, nbits_frac_x_in) downto slo(nbits_x_in, nbits_frac_x_in));
- yin : in sfixed(shi(nbits_y_in, nbits_frac_y_in) downto slo(nbits_y_in, nbits_frac_y_in));
- zin : in sfixed(shi(nbits_z_in, nbits_frac_z_in) downto slo(nbits_z_in, nbits_frac_z_in));
- xout : out sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
- yout : out sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
- zout : out sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
- vld_out : out std_logic
-);
-end cordic_pipe_top;
-
-architecture Behavioral of cordic_pipe_top is
-
------------------------------------------------------------------------
-COMPONENT cordic_pipe_pre is
-GENERIC
-(
- cordic_mode : cordic_mode_t;
- z_range : real;
- nbits_x : integer;
- nbits_x_frac : integer;
- nbits_y : integer;
- nbits_y_frac : integer;
- nbits_z : integer;
- nbits_z_frac : integer
-);
-PORT(
- rst : IN std_logic;
- clk : IN std_logic;
- vld_in : IN std_logic;
- xin : IN sfixed;
- yin : IN sfixed;
- zin : IN sfixed;
- xout : OUT sfixed;
- yout : OUT sfixed;
- zout : OUT sfixed;
- vld_out : out std_logic
-);
-END COMPONENT;
-
-COMPONENT cordic_pipe_stage
-GENERIC
-(
- cordic_mode : cordic_mode_t;
- z_range : real;
- stage_num : integer;
- nbits_x : integer;
- nbits_x_frac : integer;
- nbits_y : integer;
- nbits_y_frac : integer;
- nbits_z : integer;
- nbits_z_frac : integer
-);
-PORT(
- rst : IN std_logic;
- clk : IN std_logic;
- vld_in : IN std_logic;
- xin : IN sfixed;
- yin : IN sfixed;
- zin : IN sfixed;
- xout : OUT sfixed;
- yout : OUT sfixed;
- zout : OUT sfixed;
- vld_out : out std_logic
-);
-END COMPONENT;
-
-COMPONENT cordic_pipe_post is
-GENERIC
-(
- cordic_mode : cordic_mode_t;
- nstages : integer;
- nbits_x : integer;
- nbits_x_frac : integer;
- nbits_y : integer;
- nbits_y_frac : integer;
- nbits_z : integer;
- nbits_z_frac : integer
-);
-PORT(
- rst : IN std_logic;
- clk : IN std_logic;
- vld_in : IN std_logic;
- xin : IN sfixed;
- yin : IN sfixed;
- zin : IN sfixed;
- xout : OUT sfixed;
- yout : OUT sfixed;
- zout : OUT sfixed;
- vld_out : out std_logic
-);
-END COMPONENT;
-
------------------------------------------------------------------------
-
--- Define number of internal stage bits
-constant stage_x_nbits : integer := nbits_x_in + integer(log2(real(nbits_x_in))+0.5);
-constant stage_x_nbits_frac : integer := nbits_frac_x_in + integer(log2(real(nbits_x_in))+0.5);
-constant stage_y_nbits : integer := nbits_y_in + integer(log2(real(nbits_y_in))+0.5);
-constant stage_y_nbits_frac : integer := nbits_frac_y_in + integer(log2(real(nbits_y_in))+0.5);
-constant stage_z_nbits : integer := nbits_z_in + integer(log2(real(nbits_z_in))+0.5);
-constant stage_z_nbits_frac : integer := nbits_frac_z_in + integer(log2(real(nbits_z_in))+0.5);
-
--- INPUT
--- Input pre stage
-signal pre_xin : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
-signal pre_yin : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
-signal pre_zin : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
-signal pre_xout : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
-signal pre_yout : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
-signal pre_zout : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
-
--- Input processing stage
-subtype stage_x_t is sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
-subtype stage_y_t is sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
-subtype stage_z_t is sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
-type stage_x_array_t is array(0 to nstages) of stage_x_t;
-type stage_y_array_t is array(0 to nstages) of stage_y_t;
-type stage_z_array_t is array(0 to nstages) of stage_z_t;
-
-signal stage_vld: unsigned(0 to nstages);
-signal stage_x : stage_x_array_t;
-signal stage_y : stage_y_array_t;
-signal stage_z : stage_z_array_t;
-
--- Output post stage
-signal post_xin : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
-signal post_yin : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
-signal post_zin : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
-signal post_xout : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
-signal post_yout : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
-signal post_zout : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
-signal post_vld : std_logic;
-
-begin
-
- pre_xin <= resize(xin, pre_xin);
- pre_yin <= resize(yin, pre_yin);
- pre_zin <= resize(zin, pre_zin);
-
- stage_x(0) <= resize(pre_xout, stage_x(0));
- stage_y(0) <= resize(pre_yout, stage_y(0));
- stage_z(0) <= resize(pre_zout, stage_z(0));
-
- post_xin <= resize(stage_x(nstages), post_xin, cordic_saturate_mode, cordic_round_mode);
- post_yin <= resize(stage_y(nstages), post_yin, cordic_saturate_mode, cordic_round_mode);
- post_zin <= resize(stage_z(nstages), post_zin, cordic_saturate_mode, cordic_round_mode);
-
-gen_output_unity:
- if gain_corr_mode = gain_mode_unity generate
- begin
- xout <= post_xout;
- yout <= post_yout;
- zout <= post_zout;
- vld_out <= post_vld;
- end generate;
-
-gen_output_disabled:
- if gain_corr_mode = gain_mode_disabled generate
- begin
- xout <= post_xin;
- yout <= post_yin;
- zout <= post_zin;
- vld_out <= stage_vld(nstages);
- end generate;
-
------------------------------------------------------------------------
-Inst_cordic_pipe_pre: cordic_pipe_pre
-GENERIC MAP
-(
- cordic_mode => cordic_mode_rotate,
- z_range => z_range,
- nbits_x => stage_x_nbits,
- nbits_x_frac => stage_x_nbits_frac,
- nbits_y => stage_y_nbits,
- nbits_y_frac => stage_y_nbits_frac,
- nbits_z => stage_z_nbits,
- nbits_z_frac => stage_z_nbits_frac
-)
-PORT MAP
-(
- rst => rst,
- clk => clk,
- vld_in => vld_in,
- xin => pre_xin,
- yin => pre_yin,
- zin => pre_zin,
- xout => pre_xout,
- yout => pre_yout,
- zout => pre_zout,
- vld_out => stage_vld(0)
-);
-
-gen_pipe:
- for i in 1 to nstages generate
-
- Inst_cordic_pipe: cordic_pipe_stage
- GENERIC MAP
- (
- cordic_mode => cordic_mode_rotate,
- z_range => z_range,
- stage_num => i-1,
- nbits_x => stage_x_nbits,
- nbits_x_frac => stage_x_nbits_frac,
- nbits_y => stage_y_nbits,
- nbits_y_frac => stage_y_nbits_frac,
- nbits_z => stage_z_nbits,
- nbits_z_frac => stage_z_nbits_frac
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- vld_in => stage_vld(i-1),
- xin => stage_x(i-1),
- yin => stage_y(i-1),
- zin => stage_z(i-1),
- xout => stage_x(i),
- yout => stage_y(i),
- zout => stage_z(i),
- vld_out => stage_vld(i)
- );
-
- end generate;
-
-gen_post_process:
- if gain_corr_mode = gain_mode_unity generate
- begin
-
- Inst_cordic_pipe_post: cordic_pipe_post
- GENERIC MAP
- (
- cordic_mode => cordic_mode_rotate,
- nstages => nstages,
- nbits_x => nbits_x_out,
- nbits_x_frac => nbits_frac_x_out,
- nbits_y => nbits_y_out,
- nbits_y_frac => nbits_frac_y_out,
- nbits_z => nbits_z_out,
- nbits_z_frac => nbits_frac_z_out
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- vld_in => stage_vld(nstages),
- xin => post_xin,
- yin => post_yin,
- zin => post_zin,
- xout => post_xout,
- yout => post_yout,
- zout => post_zout,
- vld_out => post_vld
- );
-
- end generate;
-
---------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_pkg.vhd b/lib/radio/cordic/src/cordic_pkg.vhd
deleted file mode 100644
index d26d2b6..0000000
--- a/lib/radio/cordic/src/cordic_pkg.vhd
+++ /dev/null
@@ -1,208 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
-package cordic_pkg is
-
- constant tpd : time := 0 ns;
-
- type cordic_mode_t is (none, cordic_mode_rotate, cordic_mode_vector);
- type reg_mode_t is (none, reg_mode_in, reg_mode_out, reg_mode_inout);
- type gain_corr_mode_t is (gain_mode_disabled, gain_mode_unity);
-
- -- Global set arithmetic rounding mode
- constant cordic_round_mode : fixed_round_style_type := fixed_round;
-
- -- Global set arithmetic saturating mode
- constant cordic_saturate_mode : fixed_overflow_style_type := fixed_wrap;
-
- constant max_iteration : integer := 80;
-
- -- Normalized Arctan table (for phases z = -1..+1)
- -- MatLab command: arctan_tbl = (atan(2.^-(0:N-1))/pi)'
- -- (Print format: long e, compact)
- constant arctan_tbl : real_array_t (0 to max_iteration-1) :=
- (
- 2.500000000000000e-001,
- 1.475836176504333e-001,
- 7.797913037736932e-002,
- 3.958342416056555e-002,
- 1.986852430554084e-002,
- 9.943947823589275e-003,
- 4.973187278950414e-003,
- 2.486745393669739e-003,
- 1.243391668714101e-003,
- 6.216982059233716e-004,
- 3.108493994100204e-004,
- 1.554247367611316e-004,
- 7.771237301258342e-005,
- 3.885618708529400e-005,
- 1.942809361502228e-005,
- 9.714046816558053e-006,
- 4.857023409409890e-006,
- 2.428511704846303e-006,
- 1.214255852440821e-006,
- 6.071279262226194e-007,
- 3.035639631115858e-007,
- 1.517819815558274e-007,
- 7.589099077791802e-008,
- 3.794549538895954e-008,
- 1.897274769447984e-008,
- 9.486373847239929e-009,
- 4.743186923619965e-009,
- 2.371593461809983e-009,
- 1.185796730904992e-009,
- 5.928983654524958e-010,
- 2.964491827262479e-010,
- 1.482245913631239e-010,
- 7.411229568156197e-011,
- 3.705614784078099e-011,
- 1.852807392039049e-011,
- 9.264036960195246e-012,
- 4.632018480097623e-012,
- 2.316009240048812e-012,
- 1.158004620024406e-012,
- 5.790023100122029e-013,
- 2.895011550061015e-013,
- 1.447505775030507e-013,
- 7.237528875152536e-014,
- 3.618764437576268e-014,
- 1.809382218788134e-014,
- 9.046911093940670e-015,
- 4.523455546970335e-015,
- 2.261727773485168e-015,
- 1.130863886742584e-015,
- 5.654319433712919e-016,
- 2.827159716856459e-016,
- 1.413579858428230e-016,
- 7.067899292141149e-017,
- 3.533949646070574e-017,
- 1.766974823035287e-017,
- 8.834874115176436e-018,
- 4.417437057588218e-018,
- 2.208718528794109e-018,
- 1.104359264397055e-018,
- 5.521796321985272e-019,
- 2.760898160992636e-019,
- 1.380449080496318e-019,
- 6.902245402481590e-020,
- 3.451122701240795e-020,
- 1.725561350620398e-020,
- 8.627806753101988e-021,
- 4.313903376550994e-021,
- 2.156951688275497e-021,
- 1.078475844137749e-021,
- 5.392379220688743e-022,
- 2.696189610344371e-022,
- 1.348094805172186e-022,
- 6.740474025860928e-023,
- 3.370237012930464e-023,
- 1.685118506465232e-023,
- 8.425592532326160e-024,
- 4.212796266163080e-024,
- 2.106398133081540e-024,
- 1.053199066540770e-024,
- 5.265995332703850e-025
- );
-
- -- Gain correction table
- -- MatLab command: gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))'
- -- (Print format: long e, compact)
- constant gain_tbl : real_array_t (0 to max_iteration-1) :=
- (
- 7.071067811865475e-001,
- 6.324555320336759e-001,
- 6.135719910778963e-001,
- 6.088339125177524e-001,
- 6.076482562561681e-001,
- 6.073517701412959e-001,
- 6.072776440935260e-001,
- 6.072591122988928e-001,
- 6.072544793325624e-001,
- 6.072533210898752e-001,
- 6.072530315291344e-001,
- 6.072529591389448e-001,
- 6.072529410413973e-001,
- 6.072529365170103e-001,
- 6.072529353859135e-001,
- 6.072529351031394e-001,
- 6.072529350324457e-001,
- 6.072529350147724e-001,
- 6.072529350103540e-001,
- 6.072529350092495e-001,
- 6.072529350089733e-001,
- 6.072529350089043e-001,
- 6.072529350088870e-001,
- 6.072529350088827e-001,
- 6.072529350088816e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001,
- 6.072529350088813e-001
- );
-
-end; -- package cordic_pkg;
-
--------------------------------------------------------------------------------
-package body cordic_pkg is
-
-end; -- package body cordic_pkg;
diff --git a/lib/radio/cordic/src/cordic_rom.vhd b/lib/radio/cordic/src/cordic_rom.vhd
deleted file mode 100644
index 9af2ac8..0000000
--- a/lib/radio/cordic/src/cordic_rom.vhd
+++ /dev/null
@@ -1,84 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:37:26 10/02/05
--- Design Name:
--- Module Name: coeff_rom - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity rom_arctan is
- Generic
- (
- nbits : integer := 8;
- nbits_frac : integer := 8
- );
- Port
- (
- addr : in unsigned(6 downto 0);
- dout : out sfixed
- );
-end rom_arctan;
-
-architecture Behavioral of rom_arctan is
-
-subtype word_t is sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-type rom_t is array (natural range <>) of word_t;
-
--------------------------------------------------------------------------------
-function rom_gen(nstages : integer; round_mode : fixed_round_style_type) return rom_t is
-variable rom : rom_t (0 to nstages-1);
-variable word : word_t;
-begin
-
- for i in 0 to nstages-1 loop
- word := to_sfixed(arctan_tbl(i)*pi, word, fixed_wrap, round_mode);
- rom(i) := word;
- end loop;
-
- return rom;
-end rom_gen;
-
--------------------------------------------------------------------------------
--- Create ROM
-constant arctan_rom : rom_t (0 to max_iteration-1) := rom_gen(max_iteration, cordic_round_mode);
-
--------------------------------------------------------------------------------
-
-begin
-
--- ROM implementation
-rom_arctan: process(addr)
-begin
- dout <= arctan_rom(to_integer(addr));
-end process;
-
--------------------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_stage.vhd b/lib/radio/cordic/src/cordic_stage.vhd
deleted file mode 100644
index 26953ce..0000000
--- a/lib/radio/cordic/src/cordic_stage.vhd
+++ /dev/null
@@ -1,291 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_stage is
-Generic
-(
- nbits : integer := 8;
- nbits_frac : integer := 6;
- nbits_out : integer := 8;
- nbits_frac_out : integer := 6;
- reg_mode : reg_mode_t := reg_mode_in
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- ce : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- coeff : in sfixed;
- dir_cw : in std_logic;
- stage_count : in integer;
- cordic_mode : in cordic_mode_t;
- ready : out std_logic;
- valid : out std_logic
-);
-end cordic_stage;
-
-architecture Behavioral of cordic_stage is
-
-type xyz_in_t is record
- x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
- y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
- z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-end record;
-
-type xyz_out_t is record
- x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-end record;
-
-constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-
-signal xyz_in : xyz_in_t;
-signal xyz_out : xyz_out_t;
-signal valid_r, ready_r : std_logic;
-
-begin
-------------------------------------------------------------
-gen_direct: if reg_mode = none generate
-
- reg_in : process (rst, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
-
- else
- ready_r <= '1';
- valid_r <= ce;
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end process;
-
- reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- else
- ready <= ready_r;
- valid <= valid_r;
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end process;
-
-end generate;
-------------------------------------------------------------
-
-gen_reg_in: if (reg_mode = reg_mode_in) generate
-
- reg_in : process (rst, clk, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
- elsif rising_edge(clk) then
- ready_r <= '1';
- valid_r <= ce;
- if (ce = '1') then
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end if;
- end process;
-
- reg_out : process (rst, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- else
- ready <= ready_r;
- valid <= valid_r;
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end process;
-
-end generate;
-
-------------------------------------------------------------
-gen_reg_out: if (reg_mode = reg_mode_out) generate
-
- reg_in : process (rst, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
- else
- ready_r <= '1';
- valid_r <= ce;
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end process;
-
- reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- elsif rising_edge(clk) then
- ready <= ready_r;
- valid <= valid_r;
- if (ce = '1') then
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end if;
- end process;
-
-end generate;
-
-------------------------------------------------------------
-gen_reg_inout: if (reg_mode = reg_mode_inout) generate
-
- reg_in : process (rst, clk, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
- elsif rising_edge(clk) then
- ready_r <= '1';
- valid_r <= ce;
- if (ce = '1') then
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end if;
- end process;
-
- reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- elsif rising_edge(clk) then
- ready <= ready_r;
- valid <= valid_r;
- if (ce = '1') then
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end if;
- end process;
-
-end generate;
-
-------------------------------------------------------------
-cordic_proc_stage: process(rst, clk, ce, stage_count, coeff, dir_cw, xyz_in)
-variable dir_cw_r : std_logic;
-variable stage_count_r : integer range 0 to nbits-1;
-variable x2, y2 : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-
-begin
-
- if (rst = '1') then
- dir_cw_r := dir_cw;
- stage_count_r := 0;
- x2 := zero_in_sfix;
- y2 := zero_in_sfix;
- xyz_out.x <= zero_out_sfix;
- xyz_out.y <= zero_out_sfix;
- xyz_out.z <= zero_out_sfix;
- else
- if (clk'event and clk = '1') then
- dir_cw_r := dir_cw;
- stage_count_r := stage_count;
- end if;
-
- x2 := xyz_in.x sra stage_count_r;
- y2 := xyz_in.y sra stage_count_r;
-
- if (dir_cw_r = '1') then
- xyz_out.x <= resize(xyz_in.x + y2, xyz_out.x'left, xyz_out.x'right) after tpd;
- xyz_out.y <= resize(xyz_in.y - x2, xyz_out.y'left, xyz_out.y'right) after tpd;
- xyz_out.z <= resize(xyz_in.z + coeff, xyz_out.z'left, xyz_out.z'right) after tpd;
- else
- xyz_out.x <= resize(xyz_in.x - y2, xyz_out.x'left, xyz_out.x'right) after tpd;
- xyz_out.y <= resize(xyz_in.y + x2, xyz_out.y'left, xyz_out.y'right) after tpd;
- xyz_out.z <= resize(xyz_in.z - coeff, xyz_out.z'left, xyz_out.z'right) after tpd;
- end if;
- end if;
-end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_stage_post.vhd b/lib/radio/cordic/src/cordic_stage_post.vhd
deleted file mode 100644
index a17c665..0000000
--- a/lib/radio/cordic/src/cordic_stage_post.vhd
+++ /dev/null
@@ -1,279 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage_post - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_stage_post is
-Generic
-(
- nbits : integer := 8;
- nbits_frac : integer := 6;
- nbits_out : integer := 8;
- nbits_frac_out : integer := 6;
- reg_mode : reg_mode_t := reg_mode_in
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- ce : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- cordic_mode : in cordic_mode_t;
- ready : out std_logic;
- valid : out std_logic
-);
-end cordic_stage_post;
-
-architecture Behavioral of cordic_stage_post is
-
-type xyz_in_t is record
- x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
- y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
- z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-end record;
-
-type xyz_out_t is record
- x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-end record;
-
-constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-
-signal xyz_in : xyz_in_t;
-signal xyz_out : xyz_out_t;
-signal valid_r, ready_r : std_logic;
-
-------------------------------------------------------------
-begin
-
-gen_direct: if reg_mode = none generate
-
- reg_in : process (rst, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
-
- else
- ready_r <= '1';
- valid_r <= ce;
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end process;
-
- reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- else
- ready <= ready_r;
- valid <= valid_r;
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end process;
-
-end generate;
-------------------------------------------------------------
-
-gen_reg_in: if (reg_mode = reg_mode_in) generate
-
- reg_in : process (rst, clk, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
- elsif rising_edge(clk) then
- ready_r <= '1';
- valid_r <= ce;
- if (ce = '1') then
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end if;
- end process;
-
- reg_out : process (rst, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- else
- ready <= ready_r;
- valid <= valid_r;
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end process;
-
-end generate;
-
-------------------------------------------------------------
-gen_reg_out: if (reg_mode = reg_mode_out) generate
-
- reg_in : process (rst, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
- else
- ready_r <= '1';
- valid_r <= ce;
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end process;
-
- reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- elsif rising_edge(clk) then
- ready <= ready_r;
- valid <= valid_r;
- if (ce = '1') then
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end if;
- end process;
-
-end generate;
-
-------------------------------------------------------------
-gen_reg_inout: if (reg_mode = reg_mode_inout) generate
-
- reg_in : process (rst, clk, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
- elsif rising_edge(clk) then
- ready_r <= '1';
- valid_r <= ce;
- if (ce = '1') then
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end if;
- end process;
-
- reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- elsif rising_edge(clk) then
- ready <= ready_r;
- valid <= valid_r;
- if (ce = '1') then
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end if;
- end process;
-
- end generate;
-
-------------------------------------------------------------
-cordic_post_stage: process(xyz_in, cordic_mode)
-begin
-
- xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right);
- xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right);
- xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right);
-
- case cordic_mode is
-
- when cordic_mode_rotate =>
-
- xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode);
- xyz_out.y <= resize(xyz_in.y * to_sfixed(gain_tbl(nbits_out-1), xyz_in.y), xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode);
- xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode);
-
- when cordic_mode_vector =>
-
- xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode);
- xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode);
- xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode);
-
- when others => null;
-
- end case;
-end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_stage_pre.vhd b/lib/radio/cordic/src/cordic_stage_pre.vhd
deleted file mode 100644
index 0e9f82a..0000000
--- a/lib/radio/cordic/src/cordic_stage_pre.vhd
+++ /dev/null
@@ -1,320 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage_pre - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_stage_pre is
-Generic
-(
- nbits : integer := 8;
- nbits_frac : integer := 6;
- nbits_out : integer := 8;
- nbits_frac_out : integer := 6;
- reg_mode : reg_mode_t := reg_mode_in
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- ce : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- cordic_mode : in cordic_mode_t;
- ready : out std_logic;
- valid : out std_logic
-);
-end cordic_stage_pre;
-
-architecture Behavioral of cordic_stage_pre is
-
-type xyz_in_t is record
- x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
- y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
- z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-end record;
-
-type xyz_out_t is record
- x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-end record;
-
-constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-constant pi_out_sfix : sfixed := to_sfixed(pi, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-constant pi2_out_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-constant pi2_in_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-
-signal xyz_in : xyz_in_t;
-signal xyz_out : xyz_out_t;
-signal valid_r, ready_r : std_logic;
-
-------------------------------------------------------------
-begin
-
-gen_direct: if reg_mode = none generate
-
- reg_in : process (rst, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
-
- else
- ready_r <= '1';
- valid_r <= ce;
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end process;
-
- reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- else
- ready <= ready_r;
- valid <= valid_r;
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end process;
-
-end generate;
-------------------------------------------------------------
-
-gen_reg_in: if (reg_mode = reg_mode_in) generate
-
- reg_in : process (rst, clk, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
- elsif rising_edge(clk) then
- ready_r <= '1';
- valid_r <= ce;
- if (ce = '1') then
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end if;
- end process;
-
- reg_out : process (rst, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- else
- ready <= ready_r;
- valid <= valid_r;
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end process;
-
-end generate;
-
-------------------------------------------------------------
-gen_reg_out: if (reg_mode = reg_mode_out) generate
-
- reg_in : process (rst, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
- else
- ready_r <= '1';
- valid_r <= ce;
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end process;
-
- reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- elsif rising_edge(clk) then
- ready <= ready_r;
- valid <= valid_r;
- if (ce = '1') then
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end if;
- end process;
-
-end generate;
-
-------------------------------------------------------------
-gen_reg_inout: if (reg_mode = reg_mode_inout) generate
-
- reg_in : process (rst, clk, ce, xin, yin, zin)
- begin
- if (rst = '1') then
- ready_r <= '0';
- valid_r <= '0';
- xyz_in.x <= zero_in_sfix;
- xyz_in.y <= zero_in_sfix;
- xyz_in.z <= zero_in_sfix;
- elsif rising_edge(clk) then
- ready_r <= '1';
- valid_r <= ce;
- if (ce = '1') then
- xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- end if;
- end if;
- end process;
-
- reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- begin
- if (rst = '1') then
- ready <= '0';
- valid <= '0';
- xout <= zero_out_sfix;
- yout <= zero_out_sfix;
- zout <= zero_out_sfix;
- elsif rising_edge(clk) then
- ready <= ready_r;
- valid <= valid_r;
- if (ce = '1') then
- xout <= xyz_out.x;
- yout <= xyz_out.y;
- zout <= xyz_out.z;
- end if;
- end if;
- end process;
-
- end generate;
-
-------------------------------------------------------------
-cordic_proc_pre_stage: process(xyz_in, cordic_mode)
-begin
-
- xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right);
- xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right);
- xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right);
-
- case cordic_mode is
-
- when cordic_mode_rotate =>
-
- if (xyz_in.z < -pi2_in_sfix) then
- xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
- xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
- xyz_out.z <= resize(xyz_in.z + pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
- elsif (xyz_in.z > pi2_in_sfix) then
- xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
- xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
- xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
- end if;
-
-
- when cordic_mode_vector =>
-
--- if (xyz_in.x < zero_in_sfix) then
--- xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
--- xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
--- xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
--- end if;
- if (xyz_in.y < zero_in_sfix) then
- xyz_out.x <= resize(-xyz_in.y, xyz_out.x'left, xyz_out.x'right);
- xyz_out.y <= resize(xyz_in.x, xyz_out.y'left, xyz_out.y'right);
- xyz_out.z <= resize(xyz_in.z + pi2_out_sfix, xyz_out.z'left, xyz_out.z'right);
- else
- xyz_out.x <= resize(xyz_in.y, xyz_out.x'left, xyz_out.x'right);
- xyz_out.y <= resize(-xyz_in.x, xyz_out.y'left, xyz_out.y'right);
- xyz_out.z <= resize(xyz_in.z - pi2_out_sfix, xyz_out.z'left, xyz_out.z'right);
- end if;
-
- when others => null;
-
- end case;
-end process;
-
-------------------------------------------------------------
-end Behavioral;
-
--- if (y < 0) then
--- x' = -y
--- y' = x
--- z' = z + pi/2;
--- else
--- x' = y
--- y' = -x
--- z' = z - pi/2;
--- end if;
---
--- if (x < 0) then
--- x' = -x;
--- y' = -y;
--- z' = z - pi
--- else
--- x' = x;
--- y' = y;
--- z' = z
--- end if;
diff --git a/lib/radio/cordic/src/cordic_top.vhd b/lib/radio/cordic/src/cordic_top.vhd
deleted file mode 100644
index 8f41847..0000000
--- a/lib/radio/cordic/src/cordic_top.vhd
+++ /dev/null
@@ -1,466 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 11:52:30 10/02/05
--- Design Name:
--- Module Name: cordic_top - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity cordic_top is
-Generic
-(
- nbits : integer := 8;
- nbits_frac : integer := 6;
- nbits_out : integer := 8;
- nbits_frac_out : integer := 6
-);
-Port (
- rst : in std_logic;
- clk : in std_logic;
- ce : in std_logic;
- xin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
- yin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
- zin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
- xout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- yout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- zout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- ready : out std_logic;
- valid : out std_logic;
- cordic_mode : in cordic_mode_t
-);
-end cordic_top;
-
-architecture Behavioral of cordic_top is
-
------------------------------------------------------------------------
-COMPONENT cordic_stage_pre is
-GENERIC
-(
- nbits : integer;
- nbits_frac : integer;
- nbits_out : integer;
- nbits_frac_out : integer;
- reg_mode : reg_mode_t
-);
-PORT
-(
- rst : in std_logic;
- clk : in std_logic;
- ce : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- cordic_mode : in cordic_mode_t;
- ready : OUT std_logic;
- valid : out std_logic
-);
-END COMPONENT;
-
-COMPONENT cordic_stage
-GENERIC
-(
- nbits : integer;
- nbits_frac : integer;
- nbits_out : integer;
- nbits_frac_out : integer;
- reg_mode : reg_mode_t
-);
-PORT(
- rst : IN std_logic;
- clk : IN std_logic;
- ce : IN std_logic;
- xin : IN sfixed;
- yin : IN sfixed;
- zin : IN sfixed;
- xout : OUT sfixed;
- yout : OUT sfixed;
- zout : OUT sfixed;
- coeff : in sfixed;
- dir_cw : in std_logic;
- stage_count : IN integer;
- cordic_mode : in cordic_mode_t;
- ready : OUT std_logic;
- valid : out std_logic
-);
-END COMPONENT;
-
-COMPONENT cordic_stage_post is
-GENERIC
-(
- nbits : integer;
- nbits_frac : integer;
- nbits_out : integer;
- nbits_frac_out : integer;
- reg_mode : reg_mode_t
-);
-PORT
-(
- rst : in std_logic;
- clk : in std_logic;
- ce : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- cordic_mode : in cordic_mode_t;
- ready : OUT std_logic;
- valid : out std_logic
-);
-END COMPONENT;
-
-COMPONENT rom_arctan is
-GENERIC
-(
- nbits : integer := 8;
- nbits_frac : integer := 8
-);
-PORT
-(
- addr : in unsigned(6 downto 0);
- dout : out sfixed
-);
-END COMPONENT;
-
------------------------------------------------------------------------
-type state_type is (st_input, st_ready, st_pre_stage_in, st_pre_stage_out, st_proc_stage_in, st_proc_stage_out, st_post_stage_in, st_post_stage_out);
-
-constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-
--- Define number of LSB guard bits
-constant guard_nbits : integer := integer(log2(real(nbits))+0.5);
-
--- Define number of internal stage bits
-constant stage_nbits : integer := nbits + guard_nbits; -- add more internal precision
-constant stage_nbits_frac : integer := nbits_frac;
-
--- Set number of coefficient bits
-constant coeff_nbits : integer := nbits;
-constant coeff_nbits_frac : integer := nbits; -- coeffs have no integer part
-
--- Set number of iteration with respect to bit size
-constant max_stage_count : integer := stage_nbits;
-
--- INPUT
--- Input pre stage
-signal pre_stage_en : std_logic;
-signal xin_pre, yin_pre, zin_pre : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-
--- Output pre stage
-signal pre_stage_ready, pre_stage_valid : std_logic;
-signal xout_pre, yout_pre, zout_pre : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-
--- Input processing stage
-signal proc_stage_en: std_logic;
-signal xin_stage, yin_stage, zin_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-
--- Output processing stage
-signal proc_stage_ready, proc_stage_valid : std_logic;
-signal xout_stage, yout_stage, zout_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-
--- Input post stage
-signal post_stage_en : std_logic;
-signal xin_post, yin_post, zin_post : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-
--- Output post stage
-signal post_stage_ready, post_stage_valid : std_logic;
-signal xout_post, yout_post, zout_post : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-
--- ROM
-signal rom_addr : unsigned (6 downto 0);
-signal rom_data : sfixed(sproto(coeff_nbits, coeff_nbits_frac)'high downto sproto(coeff_nbits, coeff_nbits_frac)'low);
-
--- Misc.
-signal state, next_state : state_type;
-signal count : integer range 0 to max_stage_count-1 := 0;
-signal count_en, dir_cw, valid_s : std_logic;
-
-
-begin
-
------------------------------------------------------------------------
-cordic_proc_mode : process(rst, zin_stage, yin_stage, cordic_mode)
-
-begin
-
- if (rst = '1') then
- dir_cw <= '0';
- else
- dir_cw <= '0';
- case cordic_mode is
-
- when cordic_mode_rotate =>
- if (zin_stage(zin_stage'high) = '1') then
- dir_cw <= '1';
- end if;
-
- when cordic_mode_vector =>
- if (yin_stage(yin_stage'high) = '1') then
- dir_cw <= '0';
- else
- dir_cw <= '1';
- end if;
-
- when others => null;
-
- end case;
- end if;
-end process;
-
------------------------------------------------------------------------
-counter: process (clk, rst, count, count_en)
-begin
- if (rst = '1') then
- count <= 0;
- rom_addr <= (others => '0');
- else
- if (clk'event and clk = '1') then
- rom_addr <= to_unsigned(count, rom_addr'length);
- if (count_en = '1' and count < max_stage_count-1) then
- count <= count + 1 after tpd;
- else
- count <= 0;
- end if;
- end if;
- end if;
-end process;
-
------------------------------------------------------------------------
-OUTPUT_PROC: process (clk, rst, state, xout_stage, yout_stage, zout_stage)
-begin
- if (rst='1') then
- valid <= '0';
- xout <= zero_sfix after tpd;
- yout <= zero_sfix after tpd;
- zout <= zero_sfix after tpd;
-
- -- assign other outputs to reset value
- elsif (clk'event and clk = '1') then
- valid <= '0';
- if(post_stage_valid = '1') then
- xout <= xout_post;
- yout <= yout_post;
- zout <= zout_post;
- valid <= '1';
- end if;
- end if;
-end process;
-
------------------------------------------------------------------------
---Insert the following in the architecture after the begin keyword
- FSM_PROC: process (clk, rst, xout_stage, yout_stage, zout_stage)
- begin
- if (rst='1') then
- state <= st_ready;
- -- assign other outputs to reset value
- elsif (clk'event and clk = '1') then
- state <= next_state after tpd;
- -- assign other outputs to internal signals
- end if;
- end process;
-
- --MOORE State Machine - Outputs based on state only
-Control_proc: process (state, xin, yin, zin, xout_pre, yout_pre, zout_pre, xout_stage, yout_stage, zout_stage)
-begin
- --insert statements to decode internal output signals
- --below is simple example
- ready <= '0';
- valid_s <= '0';
- count_en <= '0';
- pre_stage_en <= '0';
- proc_stage_en <= '0';
- post_stage_en <= '0';
-
- xin_pre <= xin;
- yin_pre <= yin;
- zin_pre <= zin;
- xin_stage <= xout_stage;
- yin_stage <= yout_stage;
- zin_stage <= zout_stage;
- xin_post <= xout_stage;
- yin_post <= yout_stage;
- zin_post <= zout_stage;
-
- case (state) is
- when st_ready =>
- ready <= '1';
- when st_pre_stage_in =>
- pre_stage_en <= '1';
- when st_pre_stage_out =>
- count_en <= '1';
- proc_stage_en <= '1';
- xin_stage <= xout_pre;
- yin_stage <= yout_pre;
- zin_stage <= zout_pre;
- when st_proc_stage_in =>
- count_en <= '1';
- proc_stage_en <= '1';
- when st_post_stage_in =>
- post_stage_en <= '1';
-
- when others =>
- end case;
-end process;
-
-NEXT_STATE_DECODE: process (state, ce, count)
-begin
- --declare default state for next_state to avoid latches
- next_state <= state; --default is to stay in current state
- --insert statements to decode next_state
- --below is a simple example
- case (state) is
- when st_ready =>
- if ce = '1' then
- next_state <= st_input;
- end if;
-
- when st_input =>
- if ce = '0' then
- next_state <= st_pre_stage_in;
- end if;
-
- when st_pre_stage_in =>
- next_state <= st_pre_stage_out;
-
- when st_pre_stage_out =>
- next_state <= st_proc_stage_in;
-
- when st_proc_stage_in =>
- if (count = max_stage_count-2) then
- next_state <= st_post_stage_in;
- end if;
-
- when st_post_stage_in =>
- next_state <= st_ready;
-
- when others =>
- next_state <= st_ready;
-
- end case;
-end process;
-
------------------------------------------------------------------------
-Inst_cordic_stage_pre: cordic_stage_pre
-GENERIC MAP
-(
- nbits => nbits,
- nbits_frac => nbits_frac,
- nbits_out => stage_nbits,
- nbits_frac_out => stage_nbits_frac,
- reg_mode => reg_mode_in
-)
-PORT MAP
-(
- rst => rst,
- clk => clk,
- ce => pre_stage_en,
- xin => xin_pre,
- yin => yin_pre,
- zin => zin_pre,
- xout => xout_pre,
- yout => yout_pre,
- zout => zout_pre,
- ready => pre_stage_ready,
- valid => pre_stage_valid,
- cordic_mode => cordic_mode
-);
-
-Inst_cordic_stage: cordic_stage
-GENERIC MAP
-(
- nbits => stage_nbits,
- nbits_frac => stage_nbits_frac,
- nbits_out => stage_nbits,
- nbits_frac_out => stage_nbits_frac,
- reg_mode => reg_mode_in
-)
-PORT MAP
-(
- rst => rst,
- clk => clk,
- ce => proc_stage_en,
- xin => xin_stage,
- yin => yin_stage,
- zin => zin_stage,
- xout => xout_stage,
- yout => yout_stage,
- zout => zout_stage,
- coeff => rom_data,
- dir_cw => dir_cw,
- stage_count => count,
- ready => proc_stage_ready,
- valid => proc_stage_valid,
- cordic_mode => cordic_mode
-);
-
-Inst_cordic_stage_post: cordic_stage_post
-GENERIC MAP
-(
- nbits => stage_nbits,
- nbits_frac => stage_nbits_frac,
- nbits_out => nbits_out,
- nbits_frac_out => nbits_frac_out,
- reg_mode => reg_mode_in
-)
-PORT MAP
-(
- rst => rst,
- clk => clk,
- ce => post_stage_en,
- xin => xin_post,
- yin => yin_post,
- zin => zin_post,
- xout => xout_post,
- yout => yout_post,
- zout => zout_post,
- ready => post_stage_ready,
- valid => post_stage_valid,
- cordic_mode => cordic_mode
-);
-
-Inst_rom_arctan: rom_arctan
-GENERIC MAP
-(
- nbits => coeff_nbits,
- nbits_frac => coeff_nbits_frac
-)
-PORT MAP
-(
- addr => rom_addr,
- dout => rom_data
-);
-
---------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/tb_cordic_pipe_top.vhd b/lib/radio/cordic/src/tb_cordic_pipe_top.vhd
deleted file mode 100644
index c88dd33..0000000
--- a/lib/radio/cordic/src/tb_cordic_pipe_top.vhd
+++ /dev/null
@@ -1,653 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 10/02/2005
--- Design Name: cordic_top
--- Module Name: tb_cordic_top.vhd
--- Project Name: cordic
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: cordic_top
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
--- Results:In 16i2 and Out 16i0
-------------------------------
--- xmean = -3.051757808671257e-7
--- ymean = 1.525878906192144e-6
--- zmean = 0.0
--- xvar = 7.723598281502283e-10
--- yvar = 8.539443970667266e-10
--- zvar = 0.0
--- xstd = 2.779136247380161e-5
--- ystd = 2.922232703031582e-5
--- zstd = 0.0
---
-------------------------------
--- Results:In 16i2 and Out 16i1
-------------------------------
--- xmean = 6.103515628828741e-7
--- ymean = -1.220703125057855e-6
--- zmean = 0.0
--- xvar = 9.76293486677989e-10
--- yvar = 7.934037490259732e-10
--- zvar = 0.0
--- xstd = 3.124569549038697e-5
--- ystd = 2.816742354256017e-5
--- zstd = 0.0
---
-------------------------------
--- Results:In 16i2 and Out 16i2
-------------------------------
--- xmean = 2.441406250382875e-6
--- ymean = -1.220703125057855e-6
--- zmean = 0.0
--- xvar = 2.126680036682826e-9
--- yvar = 2.117107754473399e-9
--- zvar = 0.0
--- xstd = 4.611594124251206e-5
--- ystd = 4.601203923402438e-5
--- zstd = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i0
-------------------------------
--- xmean = -9.312842871812748e-12
--- ymean = -5.78558739545293e-17
--- zmean = 0.0
--- xvar = 1.671709854744817e-19
--- yvar = 1.790442305004033e-19
--- zvar = 0.0
--- xstd = 4.088654857951228e-10
--- ystd = 4.231361843430591e-10
--- zstd = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i1
-------------------------------
--- xmean = 9.313608620496825e-12
--- ymean = 9.31316789028083e-12
--- zmean = 0.0
--- xvar = 1.876480788588237e-19
--- yvar = 2.238344116260579e-19
--- zvar = 0.0
--- xstd = 4.331836548841885e-10
--- ystd = 4.731114156581492e-10
--- zstd = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i2
-------------------------------
--- xmean = -3.72525201102771e-11
--- ymean = -5.78558739545293e-17
--- zmean = 0.0
--- xvar = 5.458335981037092e-19
--- yvar = 5.704280631341228e-19
--- zvar = 0.0
--- xstd = 7.388055211648797e-10
--- ystd = 7.552668820583376e-10
--- zstd = 0.0
---
-------------------------------
--- Results:In 64i2 and Out 64i0
-------------------------------
--- xmean = 3.45418680637588e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205267218835516e-16
--- xvar = 5.54111959258452e-28
--- yvar = 5.549496221074054e-28
--- zvar = 7.916891206490056e-29
--- xstd = 2.353958281827551e-14
--- ystd = 2.355736874329146e-14
--- zstd = 8.897691389619023e-15
---
-------------------------------
--- Results:In 64i2 and Out 64i1
-------------------------------
--- xmean = 3.45418680637588e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205267218835516e-16
--- xvar = 5.541120861185077e-28
--- yvar = 5.549497432144743e-28
--- zvar = 7.916856202525234e-29
--- xstd = 2.353958551288674e-14
--- ystd = 2.355737131376237e-14
--- zstd = 8.897671719346156e-15
---
-------------------------------
--- Results:In 64i2 and Out 64i2
-------------------------------
--- xmean = 3.343164503913365e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205223850748616e-16
--- xvar = 5.540559656182732e-28
--- yvar = 5.549495010008071e-28
--- zvar = 7.916821581863743e-29
--- xstd = 2.353839343749427e-14
--- ystd = 2.355736617283025e-14
--- zstd = 8.897652264425568e-15
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_cordic_pipe_top IS
- Generic (
- nbits_x_in : integer := 18;
- nbits_y_in : integer := 18;
- nbits_z_in : integer := 24;
- nbits_frac_x_in : integer := 17;
- nbits_frac_y_in : integer := 17;
- nbits_frac_z_in : integer := 22;
- nbits_x_out : integer := 18;
- nbits_y_out : integer := 18;
- nbits_z_out : integer := 18;
- nbits_frac_x_out : integer := 17;
- nbits_frac_y_out : integer := 17;
- nbits_frac_z_out : integer := 17
- );
-END tb_cordic_pipe_top;
-
-ARCHITECTURE behavior OF tb_cordic_pipe_top IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT cordic_pipe_top
- GENERIC
- (
- cordic_mode : cordic_mode_t;
- z_range : real;
- gain_corr_mode : gain_corr_mode_t;
- nstages : integer;
- nbits_x_in : integer;
- nbits_y_in : integer;
- nbits_z_in : integer;
- nbits_frac_x_in : integer;
- nbits_frac_y_in : integer;
- nbits_frac_z_in : integer;
- nbits_x_out : integer;
- nbits_y_out : integer;
- nbits_z_out : integer;
- nbits_frac_x_out : integer;
- nbits_frac_y_out : integer;
- nbits_frac_z_out : integer
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- vld_in : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
- --Constants
- constant num_cycles : integer := 5;
- constant num_steps_per_cycle : integer := 100;
- constant PERIOD : time := 10 ns;
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL rst : std_logic := '1';
- SIGNAL vld_in : std_logic := '0';
- SIGNAL xin : sfixed(sproto(nbits_x_in, nbits_frac_x_in)'high downto sproto(nbits_x_in, nbits_frac_x_in)'low) := to_sfixed(0.0, sproto(nbits_x_in, nbits_frac_x_in)'high, sproto(nbits_x_in, nbits_frac_x_in)'low);
- SIGNAL yin : sfixed(sproto(nbits_y_in, nbits_frac_y_in)'high downto sproto(nbits_y_in, nbits_frac_y_in)'low) := to_sfixed(0.0, sproto(nbits_y_in, nbits_frac_y_in)'high, sproto(nbits_y_in, nbits_frac_y_in)'low);
- SIGNAL zin : sfixed(sproto(nbits_z_in, nbits_frac_z_in)'high downto sproto(nbits_z_in, nbits_frac_z_in)'low) := to_sfixed(0.0, sproto(nbits_z_in, nbits_frac_z_in)'high, sproto(nbits_z_in, nbits_frac_z_in)'low);
-
- --Outputs
- SIGNAL xout : sfixed(sproto(nbits_x_out, nbits_frac_x_out)'high downto sproto(nbits_x_out, nbits_frac_x_out)'low);
- SIGNAL yout : sfixed(sproto(nbits_y_out, nbits_frac_y_out)'high downto sproto(nbits_y_out, nbits_frac_y_out)'low);
- SIGNAL zout : sfixed(sproto(nbits_z_out, nbits_frac_z_out)'high downto sproto(nbits_z_out, nbits_frac_z_out)'low);
- SIGNAL vld_out : std_logic;
-
- --------------------------------------------------------------------
- --Functions
- --------------------------------------------------------------------
- type real_vector_t is array (natural range <>) of real;
- function mean(x : real_vector_t; len : integer) return real is
- variable xm : real := 0.0;
- begin
- for i in 0 to len-1 loop
- xm := xm + x(i);
- end loop;
-
- return xm / real(len);
- end mean;
-
- --------------------------------------------------------------------
- function var(x : real_vector_t; len : integer) return real is
- variable xv, xm, xp : real := 0.0;
- begin
- xm := mean(x, len);
-
- for i in 0 to len-1 loop
- xp := x(i) - xm;
- xv := xv + xp*xp;
- end loop;
-
- return xv / real(len);
- end var;
-
- --------------------------------------------------------------------
- function stddev(x : real_vector_t; len : integer) return real is
- variable xv, xs : real := 0.0;
- begin
- xv := var(x, len);
- if xv > 0.0 then
- xs := sqrt(xv);
- end if;
-
- return xs;
- end stddev;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: cordic_pipe_top
- GENERIC MAP
- (
- cordic_mode => cordic_mode_rotate,
- z_range => pi,
- gain_corr_mode => gain_mode_disabled,
- nstages => 18,
- nbits_x_in => nbits_x_in,
- nbits_frac_x_in => nbits_frac_x_in,
- nbits_y_in => nbits_y_in,
- nbits_frac_y_in => nbits_frac_y_in,
- nbits_z_in => nbits_z_in,
- nbits_frac_z_in => nbits_frac_z_in,
- nbits_x_out => nbits_x_out,
- nbits_frac_x_out => nbits_frac_x_out,
- nbits_y_out => nbits_y_out,
- nbits_frac_y_out => nbits_frac_y_out,
- nbits_z_out => nbits_z_out,
- nbits_frac_z_out => nbits_frac_z_out
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- vld_in => vld_in,
- xin => xin,
- yin => yin,
- zin => zin,
- xout => xout,
- yout => yout,
- zout => zout,
- vld_out => vld_out
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- variable xerr, yerr, zerr : real_vector_t (0 to num_steps_per_cycle*num_cycles-1);
- variable xvar, xstd, xmean, yvar, ystd, ymean, zvar, zstd, zmean : real;
- variable argx, argy, argz : real := 0.0;
- variable phi, dphi : real := 0.0;
- file RESULT: text open write_mode is "STD_OUTPUT";
- file RESULT_X: text open write_mode is "x.txt";
- file RESULT_Y: text open write_mode is "y.txt";
- file RESULT_Z: text open write_mode is "z.txt";
- variable L: line;
- variable j : integer := 0;
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- rst <= '0';
-
- wait for 2*PERIOD;
-
- for i in 0 to arctan_tbl'length-1 loop
- fprint(RESULT, L,"coeff arctan (%d) = %s\n", fo(i), REAL'image(arctan_tbl(i)));
- end loop;
- for i in 0 to gain_tbl'length-1 loop
- fprint(RESULT, L,"coeff gain (%d) = %s\n", fo(i), REAL'image(gain_tbl(i)));
- end loop;
- fprint(RESULT, L,"Pi = %s\n", REAL'image(MATH_PI));
- fprint(RESULT, L,"sqrt(2) = %s\n", REAL'image(SQRT(2.0)));
- fprint(RESULT, L,"1/sqrt(2) = %s\n", REAL'image(1.0/SQRT(2.0)));
-
- -------------------------------------------
- -- 1
- argx := 1.0;
- argy := 0.0;
- argz := -pi/4.0;
-
- wait until rising_edge(clk);
- xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
- yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
- zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
- vld_in <= '1';
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait until rising_edge(clk) and vld_out = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
--- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
- fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 2
- argx := 1.0;
- argy := 0.0;
- argz := pi/2.0;
-
- wait until rising_edge(clk);
- xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
- yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
- zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
- vld_in <= '1';
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait until rising_edge(clk) and vld_out = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
--- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
- fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 3
- argx := sqrt2_inv;
- argy := -sqrt2_inv;
- argz := pi/2.0;
-
- wait until rising_edge(clk);
- xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
- yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
- zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
- vld_in <= '1';
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait until rising_edge(clk) and vld_out = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
--- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
- fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 4
- argx := sqrt2_inv;
- argy := -sqrt2_inv;
- argz := -pi/4.0;
-
- wait until rising_edge(clk);
- xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
- yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
- zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
- vld_in <= '1';
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait until rising_edge(clk) and vld_out = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
--- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
- fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 5
- argx := 1.0;
- argy := 1.0;
- argz := 0.0;
-
- wait until rising_edge(clk);
- xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
- yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
- zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
- vld_in <= '1';
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait until rising_edge(clk) and vld_out = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
--- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
- fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 6
- argx := sqrt2_inv;
- argy := -sqrt2_inv;
- argz := 0.0;
-
- wait until rising_edge(clk);
- xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
- yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
- zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
- vld_in <= '1';
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait until rising_edge(clk) and vld_out = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
- fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
- fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 7
- argx := -sqrt2_inv;
- argy := sqrt2_inv;
- argz := 0.0;
-
- wait until rising_edge(clk);
- xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
- yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
- zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
- vld_in <= '1';
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait until rising_edge(clk) and vld_out = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
--- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
- fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 8
- argx := -sqrt2_inv;
- argy := -sqrt2_inv;
- argz := 0.0;
-
- wait until rising_edge(clk);
- xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
- yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
- zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
- vld_in <= '1';
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait until rising_edge(clk) and vld_out = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
--- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
- fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- Place stimulus here
- wait for 10*PERIOD;
- wait until rising_edge(clk) and vld_out = '0';
- j := 0;
- dphi := 2.0*pi/real(num_steps_per_cycle);
- for k in 0 to num_cycles-1 loop
- phi := -pi;
- for i in 0 to num_steps_per_cycle-1 loop
- xin <= to_sfixed(1.0, xin);
- yin <= to_sfixed(0.0, yin);
- zin <= to_sfixed(phi, zin, fixed_wrap, fixed_round);
-
- vld_in <= '1';
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait until rising_edge(clk) and vld_out = '1';
-
- fprint(RESULT_X, L,"%s\n", REAL'image(to_real(xout)));
- fprint(RESULT_Y, L,"%s\n", REAL'image(to_real(yout)));
- fprint(RESULT_Z, L,"%s\n", REAL'image(to_real(zout)));
-
--- fprint(RESULT_X, L,"%s\n", REAL'image(cos(phi)));
--- fprint(RESULT_Y, L,"%s\n", REAL'image(sin(phi)));
--- fprint(RESULT_Z, L,"%s\n", REAL'image(0.0));
-
- xerr(j) := to_real(xout) - cos(phi);
- yerr(j) := to_real(yout) - sin(phi);
- zerr(j) := to_real(zout);
- j := j + 1;
- phi := (phi + dphi);
- end loop;
- end loop;
- xmean := mean(xerr, j);
- ymean := mean(yerr, j);
- zmean := mean(zerr, j);
- xvar := var(xerr, j);
- yvar := var(yerr, j);
- zvar := var(zerr, j);
- xstd := stddev(xerr, j);
- ystd := stddev(yerr, j);
- zstd := stddev(zerr, j);
- fprint(RESULT, L,"------------------------------------------\n");
- fprint(RESULT, L,"Results: \n");
- fprint(RESULT, L,"xmean = %s\n", REAL'image(xmean));
- fprint(RESULT, L,"ymean = %s\n", REAL'image(ymean));
- fprint(RESULT, L,"zmean = %s\n", REAL'image(zmean));
- fprint(RESULT, L,"xvar = %s\n", REAL'image(xvar));
- fprint(RESULT, L,"yvar = %s\n", REAL'image(yvar));
- fprint(RESULT, L,"zvar = %s\n", REAL'image(zvar));
- fprint(RESULT, L,"xstd = %s\n", REAL'image(xstd));
- fprint(RESULT, L,"ystd = %s\n", REAL'image(ystd));
- fprint(RESULT, L,"zstd = %s\n", REAL'image(zstd));
- fprint(RESULT, L,"------------------------------------------\n");
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
-END;
diff --git a/lib/radio/cordic/src/tb_cordic_top.vhd b/lib/radio/cordic/src/tb_cordic_top.vhd
deleted file mode 100644
index ff75043..0000000
--- a/lib/radio/cordic/src/tb_cordic_top.vhd
+++ /dev/null
@@ -1,649 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 10/02/2005
--- Design Name: cordic_top
--- Module Name: tb_cordic_top.vhd
--- Project Name: cordic
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: cordic_top
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
--- Results:In 16i2 and Out 16i0
-------------------------------
--- xmean = -3.051757808671257e-7
--- ymean = 1.525878906192144e-6
--- zmean = 0.0
--- xvar = 7.723598281502283e-10
--- yvar = 8.539443970667266e-10
--- zvar = 0.0
--- xstd = 2.779136247380161e-5
--- ystd = 2.922232703031582e-5
--- zstd = 0.0
---
-------------------------------
--- Results:In 16i2 and Out 16i1
-------------------------------
--- xmean = 6.103515628828741e-7
--- ymean = -1.220703125057855e-6
--- zmean = 0.0
--- xvar = 9.76293486677989e-10
--- yvar = 7.934037490259732e-10
--- zvar = 0.0
--- xstd = 3.124569549038697e-5
--- ystd = 2.816742354256017e-5
--- zstd = 0.0
---
-------------------------------
--- Results:In 16i2 and Out 16i2
-------------------------------
--- xmean = 2.441406250382875e-6
--- ymean = -1.220703125057855e-6
--- zmean = 0.0
--- xvar = 2.126680036682826e-9
--- yvar = 2.117107754473399e-9
--- zvar = 0.0
--- xstd = 4.611594124251206e-5
--- ystd = 4.601203923402438e-5
--- zstd = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i0
-------------------------------
--- xmean = -9.312842871812748e-12
--- ymean = -5.78558739545293e-17
--- zmean = 0.0
--- xvar = 1.671709854744817e-19
--- yvar = 1.790442305004033e-19
--- zvar = 0.0
--- xstd = 4.088654857951228e-10
--- ystd = 4.231361843430591e-10
--- zstd = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i1
-------------------------------
--- xmean = 9.313608620496825e-12
--- ymean = 9.31316789028083e-12
--- zmean = 0.0
--- xvar = 1.876480788588237e-19
--- yvar = 2.238344116260579e-19
--- zvar = 0.0
--- xstd = 4.331836548841885e-10
--- ystd = 4.731114156581492e-10
--- zstd = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i2
-------------------------------
--- xmean = -3.72525201102771e-11
--- ymean = -5.78558739545293e-17
--- zmean = 0.0
--- xvar = 5.458335981037092e-19
--- yvar = 5.704280631341228e-19
--- zvar = 0.0
--- xstd = 7.388055211648797e-10
--- ystd = 7.552668820583376e-10
--- zstd = 0.0
---
-------------------------------
--- Results:In 64i2 and Out 64i0
-------------------------------
--- xmean = 3.45418680637588e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205267218835516e-16
--- xvar = 5.54111959258452e-28
--- yvar = 5.549496221074054e-28
--- zvar = 7.916891206490056e-29
--- xstd = 2.353958281827551e-14
--- ystd = 2.355736874329146e-14
--- zstd = 8.897691389619023e-15
---
-------------------------------
--- Results:In 64i2 and Out 64i1
-------------------------------
--- xmean = 3.45418680637588e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205267218835516e-16
--- xvar = 5.541120861185077e-28
--- yvar = 5.549497432144743e-28
--- zvar = 7.916856202525234e-29
--- xstd = 2.353958551288674e-14
--- ystd = 2.355737131376237e-14
--- zstd = 8.897671719346156e-15
---
-------------------------------
--- Results:In 64i2 and Out 64i2
-------------------------------
--- xmean = 3.343164503913365e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205223850748616e-16
--- xvar = 5.540559656182732e-28
--- yvar = 5.549495010008071e-28
--- zvar = 7.916821581863743e-29
--- xstd = 2.353839343749427e-14
--- ystd = 2.355736617283025e-14
--- zstd = 8.897652264425568e-15
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_cordic_top IS
- Generic (
- nbits : integer := 32;
- nbits_frac : integer := 30;
- nbits_out : integer := 32;
- nbits_frac_out : integer := 31
- );
-END tb_cordic_top;
-
-ARCHITECTURE behavior OF tb_cordic_top IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT cordic_top
- GENERIC (
- nbits : integer;
- nbits_frac : integer;
- nbits_out : integer;
- nbits_frac_out : integer
- );
- PORT(
- rst : IN std_logic;
- clk : IN std_logic;
- ce : in std_logic;
- xin : IN sfixed;
- yin : IN sfixed;
- zin : IN sfixed;
- xout : OUT sfixed;
- yout : OUT sfixed;
- zout : OUT sfixed;
- ready : OUT std_logic;
- valid : out std_logic;
- cordic_mode : in cordic_mode_t
- );
- END COMPONENT;
-
- --Constants
- constant num_cycles : integer := 5;
- constant num_steps_per_cycle : integer := 100;
- constant PERIOD : time := 10 ns;
-
- constant one_sfix : sfixed := to_sfixed(1.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
- constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL rst : std_logic := '1';
- SIGNAL ce : std_logic := '0';
- SIGNAL xin, yin, zin : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low) := zero_sfix;
-
- --Outputs
- SIGNAL xout, yout, zout : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
- SIGNAL valid, ready : std_logic;
- SIGNAL cordic_mode : cordic_mode_t := cordic_mode_vector;
-
-
- --------------------------------------------------------------------
- --Functions
- --------------------------------------------------------------------
- type real_vector_t is array (natural range <>) of real;
- function mean(x : real_vector_t; len : integer) return real is
- variable xm : real := 0.0;
- begin
- for i in 0 to len-1 loop
- xm := xm + x(i);
- end loop;
-
- return xm / real(len);
- end mean;
-
- --------------------------------------------------------------------
- function var(x : real_vector_t; len : integer) return real is
- variable xv, xm, xp : real := 0.0;
- begin
- xm := mean(x, len);
-
- for i in 0 to len-1 loop
- xp := x(i) - xm;
- xv := xv + xp*xp;
- end loop;
-
- return xv / real(len);
- end var;
-
- --------------------------------------------------------------------
- function stddev(x : real_vector_t; len : integer) return real is
- variable xv, xs : real := 0.0;
- begin
- xv := var(x, len);
- if xv > 0.0 then
- xs := sqrt(xv);
- end if;
-
- return xs;
- end stddev;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: cordic_top
- GENERIC MAP (
- nbits => nbits,
- nbits_frac => nbits_frac,
- nbits_out => nbits_out,
- nbits_frac_out => nbits_frac_out
- )
- PORT MAP(
- rst => rst,
- clk => clk,
- ce => ce,
- xin => xin,
- yin => yin,
- zin => zin,
- xout => xout,
- yout => yout,
- zout => zout,
- ready => ready,
- valid => valid,
- cordic_mode => cordic_mode
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- variable xerr, yerr, zerr : real_vector_t (0 to num_steps_per_cycle*num_cycles-1);
- variable xvar, xstd, xmean, yvar, ystd, ymean, zvar, zstd, zmean : real;
- variable argx, argy, argz : real := 0.0;
- variable phi, dphi : real := 0.0;
- file RESULT: text open write_mode is "STD_OUTPUT";
- file RESULT_X: text open write_mode is "x.txt";
- file RESULT_Y: text open write_mode is "y.txt";
- file RESULT_Z: text open write_mode is "z.txt";
- variable L: line;
- variable j : integer := 0;
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- rst <= '0';
-
- wait for 2*PERIOD;
-
- for i in 0 to arctan_tbl'length-1 loop
- fprint(RESULT, L,"coeff arctan (%d) = %s\n", fo(i), REAL'image(arctan_tbl(i)));
- end loop;
- for i in 0 to gain_tbl'length-1 loop
- fprint(RESULT, L,"coeff gain (%d) = %s\n", fo(i), REAL'image(gain_tbl(i)));
- end loop;
- fprint(RESULT, L,"Pi = %s\n", REAL'image(MATH_PI));
- fprint(RESULT, L,"sqrt(2) = %s\n", REAL'image(SQRT(2.0)));
- fprint(RESULT, L,"1/sqrt(2) = %s\n", REAL'image(1.0/SQRT(2.0)));
-
- -------------------------------------------
- -- 1
- wait until rising_edge(clk) and ready = '1';
-
- cordic_mode <= cordic_mode_rotate;
- argx := 1.0;
- argy := 0.0;
- argz := -pi/4.0;
-
- xin <= to_sfixed(argx, xin);
- yin <= to_sfixed(argy, yin);
- zin <= to_sfixed(argz, zin);
-
- ce <= '1';
- wait until rising_edge(clk);
- ce <= '0';
-
- wait until rising_edge(clk) and ready = '0';
- wait until rising_edge(clk) and valid = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
- fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 2
- wait until rising_edge(clk) and ready = '1';
-
- cordic_mode <= cordic_mode_rotate;
- argx := 1.0;
- argy := 0.0;
- argz := pi/2.0;
-
- xin <= to_sfixed(argx, xin);
- yin <= to_sfixed(argy, yin);
- zin <= to_sfixed(argz, zin);
-
- ce <= '1';
- wait until rising_edge(clk);
- ce <= '0';
-
- wait until rising_edge(clk) and ready = '0';
- wait until rising_edge(clk) and valid = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
- fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 3
- wait until rising_edge(clk) and ready = '1';
-
- cordic_mode <= cordic_mode_rotate;
- argx := sqrt2_inv;
- argy := -sqrt2_inv;
- argz := pi/2.0;
-
- xin <= to_sfixed(argx, xin);
- yin <= to_sfixed(argy, yin);
- zin <= to_sfixed(argz, zin);
-
- ce <= '1';
- wait until rising_edge(clk);
- ce <= '0';
-
- wait until rising_edge(clk) and ready = '0';
- wait until rising_edge(clk) and valid = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
- fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 4
- wait until rising_edge(clk) and ready = '1';
-
- cordic_mode <= cordic_mode_rotate;
- argx := sqrt2_inv;
- argy := -sqrt2_inv;
- argz := -pi/4.0;
-
- xin <= to_sfixed(argx, xin);
- yin <= to_sfixed(argy, yin);
- zin <= to_sfixed(argz, zin);
-
- ce <= '1';
- wait until rising_edge(clk);
- ce <= '0';
-
- wait until rising_edge(clk) and ready = '0';
- wait until rising_edge(clk) and valid = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
- fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 5
- wait until rising_edge(clk) and ready = '1';
-
- cordic_mode <= cordic_mode_vector;
- argx := 1.0;
- argy := 1.0;
- argz := 0.0;
-
- xin <= to_sfixed(argx, xin);
- yin <= to_sfixed(argy, yin);
- zin <= to_sfixed(argz, zin);
-
- ce <= '1';
- wait until rising_edge(clk);
- ce <= '0';
-
- wait until rising_edge(clk) and ready = '0';
- wait until rising_edge(clk) and valid = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
- fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 6
- wait until rising_edge(clk) and ready = '1';
-
- cordic_mode <= cordic_mode_vector;
- argx := sqrt2_inv;
- argy := -sqrt2_inv;
- argz := 0.0;
-
- xin <= to_sfixed(argx, xin);
- yin <= to_sfixed(argy, yin);
- zin <= to_sfixed(argz, zin);
-
- ce <= '1';
- wait until rising_edge(clk);
- ce <= '0';
-
- wait until rising_edge(clk) and ready = '0';
- wait until rising_edge(clk) and valid = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
- fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 7
- wait until rising_edge(clk) and ready = '1';
-
- cordic_mode <= cordic_mode_vector;
- argx := -sqrt2_inv;
- argy := sqrt2_inv;
- argz := 0.0;
-
- xin <= to_sfixed(argx, xin);
- yin <= to_sfixed(argy, yin);
- zin <= to_sfixed(argz, zin);
-
- ce <= '1';
- wait until rising_edge(clk);
- ce <= '0';
-
- wait until rising_edge(clk) and ready = '0';
- wait until rising_edge(clk) and valid = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
- fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- 8
- wait until rising_edge(clk) and ready = '1';
-
- cordic_mode <= cordic_mode_vector;
- argx := -sqrt2_inv;
- argy := -sqrt2_inv;
- argz := 0.0;
-
- xin <= to_sfixed(argx, xin);
- yin <= to_sfixed(argy, yin);
- zin <= to_sfixed(argz, zin);
-
- ce <= '1';
- wait until rising_edge(clk);
- ce <= '0';
-
- wait until rising_edge(clk) and ready = '0';
- wait until rising_edge(clk) and valid = '1';
-
- fprint(RESULT, L,"--------------------------------\n");
- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
- fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
- fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
- fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
- fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
- fprint(RESULT, L,"\n");
- fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
- fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
- fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
- fprint(RESULT, L,"\n");
-
- -------------------------------------------
- -- Place stimulus here
- wait for 10*PERIOD;
- j := 0;
- cordic_mode <= cordic_mode_rotate;
- dphi := 2.0*pi/real(num_steps_per_cycle);
- for k in 0 to num_cycles-1 loop
- phi := -pi;
- for i in 0 to num_steps_per_cycle-1 loop
- xin <= one_sfix;
- yin <= zero_sfix;
- zin <= to_sfixed(phi, zin, fixed_wrap, fixed_round);
-
- wait until rising_edge(clk) and ready = '1';
- ce <= '1';
- wait until rising_edge(clk);
- ce <= '0';
-
- wait until rising_edge(clk) and ready = '0';
- wait until rising_edge(clk) and valid = '1';
-
- fprint(RESULT_X, L,"%s\n", REAL'image(to_real(xout)));
- fprint(RESULT_Y, L,"%s\n", REAL'image(to_real(yout)));
- fprint(RESULT_Z, L,"%s\n", REAL'image(to_real(zout)));
-
--- fprint(RESULT_X, L,"%s\n", REAL'image(cos(phi)));
--- fprint(RESULT_Y, L,"%s\n", REAL'image(sin(phi)));
--- fprint(RESULT_Z, L,"%s\n", REAL'image(0.0));
-
- xerr(j) := to_real(xout) - cos(phi);
- yerr(j) := to_real(yout) - sin(phi);
- zerr(j) := to_real(zout);
- j := j + 1;
- phi := (phi + dphi);
- end loop;
- end loop;
- xmean := mean(xerr, j);
- ymean := mean(yerr, j);
- zmean := mean(zerr, j);
- xvar := var(xerr, j);
- yvar := var(yerr, j);
- zvar := var(zerr, j);
- xstd := stddev(xerr, j);
- ystd := stddev(yerr, j);
- zstd := stddev(zerr, j);
- fprint(RESULT, L,"------------------------------------------\n");
- fprint(RESULT, L,"Results: \n");
- fprint(RESULT, L,"xmean = %s\n", REAL'image(xmean));
- fprint(RESULT, L,"ymean = %s\n", REAL'image(ymean));
- fprint(RESULT, L,"zmean = %s\n", REAL'image(zmean));
- fprint(RESULT, L,"xvar = %s\n", REAL'image(xvar));
- fprint(RESULT, L,"yvar = %s\n", REAL'image(yvar));
- fprint(RESULT, L,"zvar = %s\n", REAL'image(zvar));
- fprint(RESULT, L,"xstd = %s\n", REAL'image(xstd));
- fprint(RESULT, L,"ystd = %s\n", REAL'image(ystd));
- fprint(RESULT, L,"zstd = %s\n", REAL'image(zstd));
- fprint(RESULT, L,"------------------------------------------\n");
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
-END;
diff --git a/lib/radio/ddc/sim/tb_ddc.fdo b/lib/radio/ddc/sim/tb_ddc.fdo
deleted file mode 100644
index 0a69c83..0000000
--- a/lib/radio/ddc/sim/tb_ddc.fdo
+++ /dev/null
@@ -1,34 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w1r.vhd"
-vcom -explicit -93 "../../../filter/src/filter_pkg.vhd"
-vcom -explicit -93 "../../../filter/src/fir_pkg.vhd"
-vcom -explicit -93 "../../../filter/src/fir_stage_sys.vhd"
-vcom -explicit -93 "../../../filter/src/delay_line.vhd"
-vcom -explicit -93 "../../../filter/src/fir_semi_parallel.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd"
-vcom -explicit -93 "../../nco/src/mix_cordic.vhd"
-vcom -explicit -93 "../../decimator/CIC/src/cic_i_pipe.vhd"
-vcom -explicit -93 "../../decimator/CIC/src/cic_c_pipe.vhd"
-vcom -explicit -93 "../../decimator/CIC/src/cic_decim_pipe.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
-vcom -explicit -93 "../src/ddc.vhd"
-vcom -explicit -93 "../src/tb_ddc.vhd"
-vsim -t 1ps -lib work tb_ddc
-do {tb_ddc.wdo}
-view wave
-view structure
-view signals
-run 1000us
-
diff --git a/lib/radio/ddc/sim/tb_ddc.wdo b/lib/radio/ddc/sim/tb_ddc.wdo
deleted file mode 100644
index ce7f996..0000000
--- a/lib/radio/ddc/sim/tb_ddc.wdo
+++ /dev/null
@@ -1,126 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ddc/clk
-add wave -noupdate -format Logic /tb_ddc/rst
-add wave -noupdate -format Logic /tb_ddc/ddc_nco_rst
-add wave -noupdate -format Logic /tb_ddc/ddc_nco_en
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_freq_in
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_phase_in
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_q
-add wave -noupdate -format Logic /tb_ddc/ddc_dout_vld
-add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
-add wave -noupdate -format Logic /tb_ddc/rfgen_nco_rst
-add wave -noupdate -format Logic /tb_ddc/rfgen_nco_en
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_q
-add wave -noupdate -format Logic /tb_ddc/fileout_enable
-add wave -noupdate -divider DDC
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/din_vld
-add wave -noupdate -format Logic /tb_ddc/uut/dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/mix_dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q
-add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_i_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_q_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f
-add wave -noupdate -format Logic /tb_ddc/clk
-add wave -noupdate -format Logic /tb_ddc/rst
-add wave -noupdate -format Logic /tb_ddc/ddc_nco_rst
-add wave -noupdate -format Logic /tb_ddc/ddc_nco_en
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_freq_in
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_phase_in
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_q
-add wave -noupdate -format Logic /tb_ddc/ddc_dout_vld
-add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
-add wave -noupdate -format Logic /tb_ddc/rfgen_nco_rst
-add wave -noupdate -format Logic /tb_ddc/rfgen_nco_en
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_q
-add wave -noupdate -format Logic /tb_ddc/fileout_enable
-add wave -noupdate -divider DDC
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/din_vld
-add wave -noupdate -format Logic /tb_ddc/uut/dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/mix_dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q
-add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_i_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_q_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f
-add wave -noupdate -divider CFIR
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_write_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_q
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_start_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_start_q
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_din_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_din_vld_q
-add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_i
-add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_q
-add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_i
-add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_q
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_h_data
-add wave -noupdate -format Literal /tb_ddc/uut/cfir_h_addr
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_h_we
-add wave -noupdate -format Logic /tb_ddc/uut/hclr_mode
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_i/coef_addr
-add wave -noupdate -format Literal /tb_ddc/uut/cfir_i/coef_we
-add wave -noupdate -format Literal /tb_ddc/uut/cfir_i/coef_din
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_i/coef_dout
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {2590000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {98190775 ps} {100095223 ps}
diff --git a/lib/radio/ddc/sim/tb_results.m b/lib/radio/ddc/sim/tb_results.m
deleted file mode 100644
index 4d25ce5..0000000
--- a/lib/radio/ddc/sim/tb_results.m
+++ /dev/null
@@ -1,57 +0,0 @@
-% Read data
-function tb_results()
-%fa = 100.0;
-fa = TEXTREAD('fa.txt')/1E6
-R = TEXTREAD('ratio.txt');
-N = TEXTREAD('nstages.txt');;
-M = 1;
-fa_dec = fa/R
-N_pfir = 63;
-
-I_out_dec = TEXTREAD('i_dec.txt')';
-Q_out_dec = TEXTREAD('q_dec.txt')';
-I_out_fir = TEXTREAD('i_fir.txt')';
-Q_out_fir = TEXTREAD('q_fir.txt')';
-
-N_dec = length(I_out_dec)-2*N_pfir;
-N_fft_dec = N_dec
-N_fft2_dec = N_fft_dec/2;
-
-N_fir = length(I_out_fir)-2*N_pfir;
-N_fft_fir = N_fir
-N_fft2_fir = N_fft_fir/2;
-
-fft_y2_fir = 2/N_fft_fir*abs(fft(I_out_fir(2*N_pfir+1:N_fft_fir+2*N_pfir).*hann(N_fft_fir)'));
-
-fft_y2_dec = 2/N_fft_dec*abs(fft(I_out_dec(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)'));
-
-f = (1:N_fft_dec)/N_fft_dec;
-g = (R*M)^N;
-H = abs(sin(pi*M.*f)./sin(pi.*f/R)).^N;
-
-[v, j] = max(fft_y2_dec(1:N_fft2_dec/2))
-H = v*H/H(j);
-
-wavwrite(0.5*[I_out_dec' Q_out_dec'], 16000, 16, 'iq.wav');
-wavwrite(0.5*[I_out_fir' Q_out_fir'], 8000, 16, 'iq_cfir.wav');
-
-% Output
-close all;
-
-plot(1:length(I_out_dec), I_out_dec, 1:length(Q_out_dec), Q_out_dec); grid;
-
-figure;
-cic_plot(M, N, R);
-
-figure;
-subplot(2,1,1)
-plot(fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec(1:N_fft2_dec+1)), '-', fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(H(1:N_fft2_dec+1)), 'r-');
-legend('CIC', 'Droop');
-xlabel('MHz');
-grid;
-subplot(2,1,2)
-plot(fa/(2*R*N_fft_fir)*(0:N_fft2_fir),20*log10(fft_y2_fir(1:N_fft2_fir+1)), '-');
-legend('CFIR');
-xlabel('MHz');
-grid;
-
diff --git a/lib/radio/ddc/src/ddc.vhd b/lib/radio/ddc/src/ddc.vhd
deleted file mode 100644
index a70b50b..0000000
--- a/lib/radio/ddc/src/ddc.vhd
+++ /dev/null
@@ -1,508 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_nco
--- Module Name: tb_nco.vhd
--- Project Name: nco
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-ENTITY ddc IS
- Generic
- (
- nbits_in : integer := 18;
- nbits_in_frac : integer := 16;
- nbits_out : integer := 18;
- nbits_out_frac : integer := 16;
- lo_nbits_phase : integer := 20;
- lo_nbits_freq : integer := 20;
- cic_nstages : integer := 3;
- cic_ratio : integer := 64;
- cic_scale_nbits : integer := 18
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- lo_nco_rst : in std_logic;
- lo_nco_en : in std_logic;
- lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
- lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
- din_i : in sfixed;
- din_q : in sfixed;
- din_vld : in std_logic;
- dec_i : out sfixed;
- dec_q : out sfixed;
- dec_vld : out std_logic;
- dout_i : out sfixed;
- dout_q : out sfixed;
- dout_vld : out std_logic
- );
-END ddc;
-
-ARCHITECTURE behavior OF ddc IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT mix
- GENERIC
- (
- nbits_din : integer;
- nbits_din_frac : integer;
- nbits_dout : integer;
- nbits_dout_frac : integer;
- nbits_phase : integer;
- nbits_freq : integer
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- nco_rst : in std_logic;
- nco_en : in std_logic;
- freq_in : in unsigned(nbits_freq-1 downto 0);
- phase_in : in unsigned(nbits_phase-1 downto 0);
- din_i : in sfixed;
- din_q : in sfixed;
- dout_i : out sfixed;
- dout_q : out sfixed;
- din_vld : in std_logic;
- dout_vld : out std_logic
- );
- END COMPONENT;
-
- COMPONENT cic_decim_pipe
- GENERIC
- (
- nstages : integer;
- ratio : integer;
- scale_nbits : integer;
- in_width : integer;
- in_width_frac : integer;
- out_width : integer;
- out_width_frac : integer
- );
- PORT
- (
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
- COMPONENT fifo_sync
- GENERIC
- (
- addr_width : natural;
- data_width : natural;
- almost_full_thresh : integer;
- almost_empty_thresh : integer
- );
- PORT
- (
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- we : in STD_LOGIC;
- re : in STD_LOGIC;
- fifo_full : out STD_LOGIC;
- fifo_empty : out STD_LOGIC;
- fifo_afull : out STD_LOGIC;
- fifo_aempty : out STD_LOGIC;
- data_w : in unsigned (data_width-1 downto 0);
- data_r : out unsigned (data_width-1 downto 0)
- );
- END COMPONENT;
-
- COMPONENT fir_semi_parallel
- GENERIC
- (
- ntaps_per_stage : integer;
- nstages : integer;
- pipe_latency : integer;
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_stages : integer;
- nbits_stages_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- h_addr : in natural range 0 to nstages*ntaps_per_stage-1;
- h_we : in std_logic;
- h_in : in sfixed;
- din_vld : in std_logic;
- din : in sfixed;
- dout_vld : out std_logic;
- rdy : out std_logic;
- dout : out sfixed
- );
- END COMPONENT;
-
- constant lo_nbits_in : integer := nbits_in;
- constant lo_nbits_in_frac : integer := nbits_in_frac;
- constant lo_nbits_out : integer := nbits_in;
- constant lo_nbits_out_frac : integer := nbits_in_frac;
-
- constant cic_nbits_in : integer := lo_nbits_out;
- constant cic_nbits_in_frac : integer := lo_nbits_out_frac;
- constant cic_nbits_out : integer := nbits_out;
- constant cic_nbits_out_frac : integer := nbits_out_frac;
-
- constant cfir_pipe_latency : integer := 5;
- constant cfir_ntaps : integer := 63;
- constant cfir_nstages : integer := 2;
- constant cfir_nbits_in : integer := cic_nbits_out;
- constant cfir_nbits_in_frac : integer := cic_nbits_out_frac;
- constant cfir_nbits_out : integer := nbits_out;
- constant cfir_nbits_out_frac : integer := nbits_out_frac;
- constant cfir_nbits_stages : integer := cfir_nbits_in;
- constant cfir_nbits_stages_frac : integer := cfir_nbits_in_frac;
-
- constant cfir_ntaps_per_stage : integer := NextPowerOfTwo(cfir_ntaps)/cfir_nstages;
-
- SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
- SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
- SIGNAL mix_dout_vld : std_logic;
-
- SIGNAL dec_dout_i : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
- SIGNAL dec_dout_q : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
- SIGNAL dec_dout_vld_i : std_logic;
- SIGNAL dec_dout_vld_q : std_logic;
-
- SIGNAL cfir_h_data : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
- SIGNAL cfir_h_addr : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1;
- SIGNAL cfir_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL cfir_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL cfir_h_we : std_logic;
- SIGNAL cfir_vld_i : std_logic;
- SIGNAL cfir_vld_q : std_logic;
- SIGNAL cfir_ready_i : std_logic;
- SIGNAL cfir_ready_q : std_logic;
- SIGNAL cfir_start_i : std_logic;
- SIGNAL cfir_start_q : std_logic;
- SIGNAL cfir_din_vld_i : std_logic;
- SIGNAL cfir_din_vld_q : std_logic;
- SIGNAL cfir_din_i : sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac));
- SIGNAL cfir_din_q : sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac));
- SIGNAL cfir_write_i : std_logic;
- SIGNAL cfir_write_q : std_logic;
-
- SIGNAL fifo_empty_i : std_logic;
- SIGNAL fifo_empty_q : std_logic;
- SIGNAL fifo_full_i : std_logic;
- SIGNAL fifo_full_q : std_logic;
- SIGNAL fifo_din_i : unsigned(cfir_nbits_in-1 downto 0);
- SIGNAL fifo_din_q : unsigned(cfir_nbits_in-1 downto 0);
- SIGNAL fifo_dout_i : unsigned(cfir_nbits_in-1 downto 0);
- SIGNAL fifo_dout_q : unsigned(cfir_nbits_in-1 downto 0);
-
- constant cfir_coef : real_array_t(0 to cfir_ntaps-1) := FilterCoef_Lowpass(cfir_ntaps, 0.40, 1.0);
-
- type h_mem_t is array (0 to cfir_ntaps-1) of sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
-
- function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
- variable res : h_mem_t;
- begin
- for i in 0 to ntaps-1 loop
- res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round);
- end loop;
-
- return res;
- end to_h_mem;
-
- SIGNAL hclr_mode : std_logic;
- CONSTANT h_mem : h_mem_t := to_h_mem(cfir_coef, cfir_ntaps, cfir_h_data);
-
-BEGIN
-
--- assert false report "cfir_h_addr_i'length = " & natural'image(cfir_h_addr_i'length) & "." severity note;
- dec_vld <= dec_dout_vld_i and dec_dout_vld_q;
- dec_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
- dec_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-
- dout_vld <= cfir_vld_i and cfir_vld_q;
- dout_i <= resize(cfir_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
- dout_q <= resize(cfir_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-
--- cfir_start <= dec_dout_vld_i and dec_dout_vld_q;
-
- -- Instantiate the Unit Under Test (UUT)
- inst_mixer: mix
- GENERIC MAP
- (
- nbits_din => lo_nbits_in,
- nbits_din_frac => lo_nbits_in_frac,
- nbits_dout => lo_nbits_out,
- nbits_dout_frac => lo_nbits_out_frac,
- nbits_phase => lo_nbits_phase,
- nbits_freq => lo_nbits_freq
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- nco_rst => lo_nco_rst,
- nco_en => lo_nco_en,
- freq_in => lo_freq_in,
- phase_in => lo_phase_in,
- din_i => din_i,
- din_q => din_q,
- dout_i => mix_dout_i,
- dout_q => mix_dout_q,
- din_vld => din_vld,
- dout_vld => mix_dout_vld
- );
-
- inst_cic_decim_pipe_I : cic_decim_pipe
- GENERIC MAP
- (
- nstages => cic_nstages,
- ratio => cic_ratio,
- scale_nbits => cic_scale_nbits,
- in_width => cic_nbits_in,
- in_width_frac => cic_nbits_in_frac,
- out_width => cic_nbits_out,
- out_width_frac => cic_nbits_out_frac
- )
- PORT MAP
- (
- clk => clk,
- rst => rst,
- vld_in => mix_dout_vld,
- din => mix_dout_i,
- dout => dec_dout_i,
- vld_out => dec_dout_vld_i
- );
-
- inst_cic_decim_pipe_Q : cic_decim_pipe
- GENERIC MAP
- (
- nstages => cic_nstages,
- ratio => cic_ratio,
- scale_nbits => cic_scale_nbits,
- in_width => cic_nbits_in,
- in_width_frac => cic_nbits_in_frac,
- out_width => cic_nbits_out,
- out_width_frac => cic_nbits_out_frac
- )
- PORT MAP
- (
- clk => clk,
- rst => rst,
- vld_in => mix_dout_vld,
- din => mix_dout_q,
- dout => dec_dout_q,
- vld_out => dec_dout_vld_q
- );
-
- cfir_I : entity work.fir_semi_parallel
- GENERIC MAP
- (
- ntaps_per_stage => cfir_ntaps_per_stage,
- nstages => cfir_nstages,
- pipe_latency => cfir_pipe_latency,
- nbits_in => cfir_nbits_in,
- nbits_in_frac => cfir_nbits_in_frac,
- nbits_stages => cfir_nbits_stages,
- nbits_stages_frac => cfir_nbits_stages_frac,
- nbits_out => cfir_nbits_out,
- nbits_out_frac => cfir_nbits_out_frac
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- h_addr => cfir_h_addr,
- h_we => cfir_h_we,
- h_in => cfir_h_data,
- din_vld => cfir_din_vld_i,
- din => cfir_din_i,
- dout_vld => cfir_vld_i,
- start => cfir_start_i,
- rdy => cfir_ready_i,
- dout => cfir_dout_i
- );
-
- cfir_Q : entity work.fir_semi_parallel
- GENERIC MAP
- (
- ntaps_per_stage => cfir_ntaps_per_stage,
- nstages => cfir_nstages,
- pipe_latency => cfir_pipe_latency,
- nbits_in => cfir_nbits_in,
- nbits_in_frac => cfir_nbits_in_frac,
- nbits_stages => cfir_nbits_stages,
- nbits_stages_frac => cfir_nbits_stages_frac,
- nbits_out => cfir_nbits_out,
- nbits_out_frac => cfir_nbits_out_frac
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- h_addr => cfir_h_addr,
- h_we => cfir_h_we,
- h_in => cfir_h_data,
- din_vld => cfir_din_vld_q,
- din => cfir_din_q,
- dout_vld => cfir_vld_q,
- start => cfir_start_q,
- rdy => cfir_ready_q,
- dout => cfir_dout_q
- );
-
- cfir_din_vld_i <= not fifo_empty_i and cfir_ready_i and cfir_write_i;
- cfir_start_i <= fifo_empty_i and cfir_write_i;
-
- fifo_din_i <= to_unsigned(ufixed(dec_dout_i));
- cfir_din_i <= sfixed(fifo_dout_i);
-
--- cfir_din_vld_i <= dec_dout_vld_i;
--- cfir_start_i <= dec_dout_vld_i;
---
--- cfir_din_i <= dec_dout_i;
-
-inst_fifo_sync_i : fifo_sync
- GENERIC MAP
- (
- addr_width => 1,
- data_width => cfir_nbits_in,
- almost_full_thresh => 1,
- almost_empty_thresh => 1
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- we => dec_dout_vld_i,
- re => cfir_write_i,
- fifo_full => fifo_full_i,
- fifo_empty => fifo_empty_i,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => fifo_din_i,
- data_r => fifo_dout_i
- );
-
- cfir_din_vld_q <= not fifo_empty_q and cfir_ready_q and cfir_write_q;
- cfir_start_q <= fifo_empty_q and cfir_write_q;
-
- fifo_din_q <= to_unsigned(ufixed(dec_dout_q));
- cfir_din_q <= sfixed(fifo_dout_q);
-
--- cfir_din_vld_q <= dec_dout_vld_q;
--- cfir_start_q <= dec_dout_vld_q;
---
--- cfir_din_q <= dec_dout_q;
-
-inst_fifo_sync_q : fifo_sync
- GENERIC MAP
- (
- addr_width => 1,
- data_width => cfir_nbits_in,
- almost_full_thresh => 1,
- almost_empty_thresh => 1
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- we => dec_dout_vld_q,
- re => cfir_write_q,
- fifo_full => fifo_full_q,
- fifo_empty => fifo_empty_q,
- fifo_afull => open,
- fifo_aempty => open,
- data_w => fifo_din_q,
- data_r => fifo_dout_q
- );
-
-cfir_write_logic_i:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- cfir_write_i <= '0';
- elsif fifo_full_i = '1' then
- cfir_write_i <= '1';
- elsif fifo_empty_i = '1' then
- cfir_write_i <= '0';
- end if;
- end if;
- end process;
-
-cfir_write_logic_q:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- cfir_write_q <= '0';
- elsif fifo_full_q = '1' then
- cfir_write_q <= '1';
- elsif fifo_empty_q = '1' then
- cfir_write_q <= '0';
- end if;
- end if;
- end process;
-
-coef_load_counter:
- process(clk)
- variable count : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1;
- variable we : std_logic;
- begin
- if rising_edge(clk) then
- cfir_h_addr <= count;
- cfir_h_we <= we;
- if rst = '1' then
- we := '1';
- hclr_mode <= '1';
- count := 0;
- else
- if hclr_mode = '1' then
- cfir_h_data <= to_sfixed(0.0, cfir_h_data);
- if count /= NextPowerOfTwo(cfir_ntaps)-1 then
- we := '1';
- count := count + 1;
- else
- count := 0;
- hclr_mode <= '0';
- end if;
- else
- cfir_h_data <= h_mem(count);
- if count /= cfir_ntaps-1 then
- we := '1';
- count := count + 1;
- else
- we := '0';
- end if;
- end if;
- end if;
- end if;
- end process;
-
-
-END;
diff --git a/lib/radio/ddc/src/syn_ddc.vhd b/lib/radio/ddc/src/syn_ddc.vhd
deleted file mode 100644
index 751ca44..0000000
--- a/lib/radio/ddc/src/syn_ddc.vhd
+++ /dev/null
@@ -1,419 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_nco
--- Module Name: tb_nco.vhd
--- Project Name: nco
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library altera;
-use altera.altera_syn_attributes.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
- ENTITY syn_ddc IS
- Generic
- (
- nbits_in : integer := 16;
- nbits_in_frac : integer := 14;
- nbits_out : integer := 32;
- nbits_out_frac : integer := 30;
- lo_nbits_phase : integer := 24;
- lo_nbits_freq : integer := 24;
- cic_nstages : integer := 5;
- cic_ratio : integer := 25;
- cic_scale_nbits : integer := 22
- );
- PORT
- (
- rst : in std_logic;
-
- adc_clk : in std_logic;
- adc_da : in signed(15 downto 0);
- adc_ofa : in std_logic;
- adc_rand : out std_logic;
- adc_pga : out std_logic;
- adc_dith : out std_logic;
- adc_shdn : out std_logic;
-
- usb_usbclk : in std_logic;
- usb_ifclk : in std_logic;
- usb_fd : out signed(15 downto 0);
- usb_pktend : out std_logic;
- usb_fifoadr : out unsigned(1 downto 0);
- usb_slcs_n : out std_logic;
- usb_slwr_n : out std_logic;
- usb_slrd_n : out std_logic;
- usb_sloe : out std_logic;
- usb_flaga : in std_logic;
- usb_flagb : in std_logic;
- usb_flagc : in std_logic;
-
- cl_clk_out : out std_logic;
- cl_dout : out unsigned(23 downto 0);
- cl_pat_sel : out std_logic;
- cl_prbs_en : out std_logic;
- cl_ds_opt : out std_logic;
- cl_bal : out std_logic;
- cl_pd_n : out std_logic;
- cl_tsen : in std_logic;
-
- reg_aen : in std_logic;
- reg_dio : inout unsigned(7 downto 0);
- reg_oe : in std_logic;
- reg_we : in std_logic
-
- );
- END syn_ddc;
-
-ARCHITECTURE behavior OF syn_ddc IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT ddc
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- lo_nbits_phase : integer;
- lo_nbits_freq : integer;
- cic_nstages : integer;
- cic_ratio : integer;
- cic_scale_nbits : integer
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- lo_nco_rst : in std_logic;
- lo_nco_en : in std_logic;
- lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
- lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
- din_vld : in std_logic;
- din_i : in sfixed;
- din_q : in sfixed;
- dec_vld : out std_logic;
- dec_i : out sfixed;
- dec_q : out sfixed;
- dout_vld : out std_logic;
- dout_i : out sfixed;
- dout_q : out sfixed
- );
- END COMPONENT;
-
- --Outputs
- SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
- SIGNAL dec_vld : std_logic;
- SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
-
- SIGNAL reg_lo_nco_rst : std_logic;
- SIGNAL reg_lo_nco_en : std_logic;
- SIGNAL reg_lo_freq_in : unsigned(31 downto 0);
- SIGNAL reg_lo_phase_in : unsigned(31 downto 0);
-
- SIGNAL reg_en_addr : std_logic;
- SIGNAL reg_en_data : std_logic;
- SIGNAL reg_addr_last : std_logic;
- SIGNAL reg_data_last : std_logic;
- SIGNAL reg_addr_async : unsigned (7 downto 0);
- SIGNAL reg_data_async : unsigned (7 downto 0);
- SIGNAL reg_addr : unsigned (7 downto 0);
- SIGNAL reg_data : unsigned (7 downto 0);
-
- SIGNAL fifo_usb_we : std_logic;
- SIGNAL fifo_usb_re : std_logic;
- SIGNAL fifo_usb_ff : std_logic;
- SIGNAL fifo_usb_ef : std_logic;
- SIGNAL fifo_usb_aff : std_logic;
- SIGNAL fifo_usb_aef : std_logic;
-
- type fifo_usb_array_t is array (0 to 3) of unsigned (15 downto 0);
- SIGNAL fifo_usb_in : fifo_usb_array_t;
- SIGNAL fifo_usb_out : unsigned (15 downto 0);
-
- SIGNAL fifo_usb_we_pipe : unsigned(3 downto 0);
- SIGNAL enable : std_logic;
- SIGNAL ddc_din_vld : std_logic;
- SIGNAL ddc_dout_vld : std_logic;
-
- SIGNAL cl_we_pipe : unsigned(1 downto 0);
- type cl_data_array_t is array (0 to 1) of unsigned (31 downto 0);
- SIGNAL cl_sd_data : cl_data_array_t;
-
- SIGNAL cl_dout_L : std_logic_vector(24 downto 0);
- SIGNAL cl_dout_H : std_logic_vector(24 downto 0);
- SIGNAL cl_dout_clk : std_logic_vector(24 downto 0);
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- inst_ddc : ddc
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- lo_nbits_phase => lo_nbits_phase,
- lo_nbits_freq => lo_nbits_freq,
- cic_nstages => cic_nstages,
- cic_ratio => cic_ratio,
- cic_scale_nbits => cic_scale_nbits
- )
- PORT MAP
- (
- rst => rst,
- clk => adc_clk,
- lo_nco_rst => reg_lo_nco_rst,
- lo_nco_en => reg_lo_nco_en,
- lo_freq_in => reg_lo_freq_in(lo_nbits_freq-1 downto 0),
- lo_phase_in => reg_lo_phase_in(lo_nbits_phase-1 downto 0),
- din_vld => ddc_din_vld,
- din_i => ddc_din_i,
- din_q => ddc_din_q,
- dec_vld => dec_vld,
- dec_i => ddc_dec_i,
- dec_q => ddc_dec_q,
- dout_vld => ddc_dout_vld,
- dout_i => ddc_dout_i,
- dout_q => ddc_dout_q
- );
-
-reg_dio <= reg_addr when reg_oe = '1' else (others => 'Z');
-
-----------------------------------------------------------
--- Register control
-----------------------------------------------------------
-proc_reg_da_async:
- process(reg_we)
- begin
- if rising_edge(reg_we) then
- if reg_aen = '1' then
- reg_addr_async <= reg_dio;
- else
- reg_data_async <= reg_dio;
- end if;
- end if;
- end process;
-
-proc_reg_da_sync:
- process(adc_clk)
--- process(usb_usbclk)
- begin
- if rising_edge(adc_clk) then
--- if rising_edge(usb_usbclk) then
- if rst = '1' then
- reg_en_addr <= '0';
- reg_en_data <= '0';
- reg_addr_last <= '0';
- reg_data_last <= '0';
- elsif reg_we = '1' then
- reg_en_addr <= reg_aen and not reg_addr_last;
- reg_en_data <= not (reg_aen or reg_data_last);
- reg_addr_last <= reg_aen;
- reg_data_last <= not reg_aen;
- else
- reg_addr_last <= '0';
- reg_data_last <= '0';
- end if;
- reg_data <= reg_data_async;
- reg_addr <= reg_addr_async;
- end if;
- end process;
-
- -- Registers
-proc_register_write:
- process(adc_clk)
--- process(usb_usbclk)
- begin
- if rising_edge(adc_clk) then
--- if rising_edge(usb_usbclk) then
- if rst = '1' then
- reg_lo_nco_rst <= '0';
- reg_lo_nco_en <= '0';
- elsif reg_en_data = '1' then
- case reg_addr is
- when X"00" => -- Control
- reg_lo_nco_rst <= reg_data(0);
- reg_lo_nco_en <= reg_data(1);
-
- when X"10" => -- freqency
- reg_lo_freq_in(7 downto 0) <= reg_data;
-
- when X"11" => -- freqency
- reg_lo_freq_in(15 downto 8) <= reg_data;
-
- when X"12" => -- freqency
- reg_lo_freq_in(23 downto 16) <= reg_data;
-
- when X"13" => -- freqency
- reg_lo_freq_in(31 downto 24) <= reg_data;
-
- when X"20" => -- phase
- reg_lo_phase_in(7 downto 0) <= reg_data;
-
- when X"21" => -- phase
- reg_lo_phase_in(15 downto 8) <= reg_data;
-
- when X"22" => -- phase
- reg_lo_phase_in(23 downto 16) <= reg_data;
-
- when X"23" => -- phase
- reg_lo_phase_in(31 downto 24) <= reg_data;
-
- when others => null;
- end case;
- end if;
- end if;
- end process;
-
-----------------------------------------------------------
--- DDC input
-----------------------------------------------------------
-proc_adc_input_register:
- process(adc_clk)
- begin
- if rising_edge(adc_clk) then
- ddc_din_vld <= enable;
- if enable = '1' then
- ddc_din_i <= sfixed(resize(adc_da, nbits_in));
- end if;
- end if;
- end process;
-
- ddc_din_q <= to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
-
- enable <= '1';
- adc_rand <= '0';
- adc_pga <= '0';
- adc_dith <= '0';
- adc_shdn <= not enable;
-
-----------------------------------------------------------
--- USB FIFO output
-----------------------------------------------------------
-proc_usb_interleave_iq:
- process(adc_clk)
- variable i, q : unsigned(31 downto 0);
- begin
- if rising_edge(adc_clk) then
- if rst = '1' then
- fifo_usb_we_pipe <= (others => '0');
- elsif ddc_dout_vld = '1' then
- fifo_usb_we_pipe <= (others => '1');
- i := unsigned(ddc_dout_i);
- q := unsigned(ddc_dout_q);
- fifo_usb_in(0) <= i(15 downto 0);
- fifo_usb_in(1) <= i(31 downto 16);
- fifo_usb_in(2) <= q(15 downto 0);
- fifo_usb_in(3) <= q(31 downto 16);
- elsif fifo_usb_ff = '0' then
- fifo_usb_we_pipe <= fifo_usb_we_pipe(fifo_usb_we_pipe'left-1 downto 0) & '0';
- fifo_usb_in(0) <= fifo_usb_in(1);
- fifo_usb_in(1) <= fifo_usb_in(2);
- fifo_usb_in(2) <= fifo_usb_in(3);
- end if;
- end if;
- end process;
-
-inst_usbfifo: entity work.fifo_async
- GENERIC MAP
- (
- addr_width => 7,
- data_width => 16,
- almost_full_thresh => 96,
- almost_empty_thresh => 32
- )
- PORT MAP
- (
- rst => rst,
- clk_w => adc_clk,
- clk_r => usb_ifclk,
- we => fifo_usb_we,
- re => fifo_usb_re,
- data_w => fifo_usb_in(0),
- data_r => fifo_usb_out,
- fifo_full => fifo_usb_ff,
- fifo_empty => fifo_usb_ef,
- fifo_afull => fifo_usb_aff,
- fifo_aempty => fifo_usb_aef
-
- );
-
- fifo_usb_we <= fifo_usb_we_pipe(fifo_usb_we_pipe'left);
- usb_fd <= signed(fifo_usb_out);
- fifo_usb_re <= usb_flaga;
- usb_slcs_n <= '0';
- usb_slwr_n <= not usb_flaga;
- usb_slrd_n <= '1';
- usb_sloe <= '0';
-
-
-----------------------------------------------------------
--- Channel-Link DDR output
-----------------------------------------------------------
-proc_cl_interleave_iq:
- process(adc_clk)
- variable i, q : unsigned(31 downto 0);
- begin
- if rising_edge(adc_clk) then
- if rst = '1' then
- cl_we_pipe <= (others => '0');
- elsif ddc_dout_vld = '1' then
- cl_we_pipe <= (others => '1');
- i := unsigned(ddc_dout_i);
- q := unsigned(ddc_dout_q);
- cl_sd_data(0) <= i;
- cl_sd_data(1) <= q;
- else
- cl_we_pipe <= cl_we_pipe(cl_we_pipe'left-1 downto 0) & '0';
- cl_sd_data(0) <= cl_sd_data(1);
- end if;
- end if;
- end process;
-
-inst_cl_ddr_out: entity work.cl_ddr_out
- PORT MAP
- (
- aclr => rst,
- datain_h => cl_dout_H,
- datain_l => cl_dout_L,
- outclock => adc_clk,
- outclocken => '1',
- dataout => cl_dout_clk
- );
-
- cl_dout_H <= '0' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(31 downto 16));
- cl_dout_L <= '1' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(15 downto 0));
- cl_dout <= unsigned(cl_dout_clk(23 downto 0));
- cl_clk_out <= cl_dout_clk(24);
- cl_pat_sel <= '0';
- cl_prbs_en <= '0';
- cl_ds_opt <= '0';
- cl_bal <= '0';
- cl_pd_n <= '1';
-
-----------------------------------------------------------
-END;
diff --git a/lib/radio/ddc/src/tb_ddc.vhd b/lib/radio/ddc/src/tb_ddc.vhd
deleted file mode 100644
index fa3a61e..0000000
--- a/lib/radio/ddc/src/tb_ddc.vhd
+++ /dev/null
@@ -1,397 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_nco
--- Module Name: tb_nco.vhd
--- Project Name: nco
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_ddc IS
- Generic
- (
- nbits_in : integer := 16;
- nbits_in_frac : integer := 14;
- nbits_out : integer := 32;
- nbits_out_frac : integer := 30;
- lo_nbits_phase : integer := 24;
- lo_nbits_freq : integer := 24;
- cic_nstages : integer := 5;
- cic_ratio : integer := 25;
- cic_scale_nbits : integer := 22;
- rfgen_nbits_phase : integer := 32;
- rfgen_nbits_freq : integer := 32
- );
-END tb_ddc;
-
-ARCHITECTURE behavior OF tb_ddc IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT ddc
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- lo_nbits_phase : integer;
- lo_nbits_freq : integer;
- cic_nstages : integer;
- cic_ratio : integer;
- cic_scale_nbits : integer
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- lo_nco_rst : in std_logic;
- lo_nco_en : in std_logic;
- lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
- lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
- din_i : in sfixed;
- din_q : in sfixed;
- din_vld : in std_logic;
- dec_i : out sfixed;
- dec_q : out sfixed;
- dec_vld : out std_logic;
- dout_i : out sfixed;
- dout_q : out sfixed;
- dout_vld : out std_logic
- );
- END COMPONENT;
-
- -- Rf-Generator
- COMPONENT mix
- GENERIC
- (
- nbits_din : integer;
- nbits_din_frac : integer;
- nbits_dout : integer;
- nbits_dout_frac : integer;
- nbits_phase : integer;
- nbits_freq : integer
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- nco_rst : in std_logic;
- nco_en : in std_logic;
- freq_in : in unsigned(nbits_freq-1 downto 0);
- phase_in : in unsigned(nbits_phase-1 downto 0);
- din_i : in sfixed;
- din_q : in sfixed;
- dout_i : out sfixed;
- dout_q : out sfixed;
- din_vld : in std_logic;
- dout_vld : out std_logic
- );
- END COMPONENT;
-
- --Constants
- constant fa : REAL := 2.0**27;
- constant frf1 : REAL := 33.99E6;
- constant frf2 : REAL := 2.1E6;
- constant frf3 : REAL := 19.01E6;
- constant flo : REAL := 2.00E6;
- constant PERIOD : time := 10 ns;
-
- SIGNAL rfgen1_freq_word : integer := integer(frf1/fa*2.0**rfgen_nbits_freq);
- SIGNAL rfgen2_freq_word : integer := integer(frf2/fa*2.0**rfgen_nbits_freq);
- SIGNAL rfgen3_freq_word : integer := integer(frf3/fa*2.0**rfgen_nbits_freq);
- SIGNAL lo_freq_word : integer := integer(flo/fa*2.0**lo_nbits_freq);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL rst : std_logic := '1';
- SIGNAL ddc_nco_rst : std_logic := '0';
- SIGNAL ddc_nco_en : std_logic := '0';
- SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
- SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
-
- --Outputs
- SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL ddc_din_vld : std_logic := '0';
-
- SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL ddc_dec_vld : std_logic;
-
- SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL ddc_dout_vld : std_logic;
-
- SIGNAL rfgen_nco_rst : std_logic := '0';
- SIGNAL rfgen_nco_en : std_logic := '0';
- SIGNAL rfgen1_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
- SIGNAL rfgen1_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
- SIGNAL rfgen2_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
- SIGNAL rfgen2_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
- SIGNAL rfgen3_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
- SIGNAL rfgen3_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
-
- --Outputs
- signal rfgen_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
- signal rfgen_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(1.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
- SIGNAL rfgen_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL rfgen_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL rfgen1_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL rfgen1_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL rfgen1_dout_vld : std_logic;
- SIGNAL rfgen2_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL rfgen2_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL rfgen2_dout_vld : std_logic;
- SIGNAL rfgen3_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL rfgen3_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- SIGNAL rfgen3_dout_vld : std_logic;
-
- SIGNAL fileout_enable : std_logic := '0';
-
- -- Debug
- signal ddc_i_out_f : real;
- signal ddc_q_out_f : real;
- signal rfgen_i_out_f : real;
- signal rfgen_q_out_f : real;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut : ddc
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- lo_nbits_phase => lo_nbits_phase,
- lo_nbits_freq => lo_nbits_freq,
- cic_nstages => cic_nstages,
- cic_ratio => cic_ratio,
- cic_scale_nbits => cic_scale_nbits
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- lo_nco_rst => ddc_nco_rst,
- lo_nco_en => ddc_nco_en,
- lo_freq_in => ddc_freq_in,
- lo_phase_in => ddc_phase_in,
- din_i => ddc_din_i,
- din_q => ddc_din_q,
- din_vld => ddc_din_vld,
- dec_i => ddc_dec_i,
- dec_q => ddc_dec_q,
- dec_vld => ddc_dec_vld,
- dout_i => ddc_dout_i,
- dout_q => ddc_dout_q,
- dout_vld => ddc_dout_vld
- );
-
- rfgen1: mix
- GENERIC MAP
- (
- nbits_din => nbits_in,
- nbits_din_frac => nbits_in_frac,
- nbits_dout => nbits_in,
- nbits_dout_frac => nbits_in_frac,
- nbits_phase => rfgen_nbits_phase,
- nbits_freq => rfgen_nbits_freq
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- nco_rst => rfgen_nco_rst,
- nco_en => rfgen_nco_en,
- freq_in => rfgen1_freq_in,
- phase_in => rfgen1_phase_in,
- din_i => rfgen_din_i,
- din_q => rfgen_din_q,
- dout_i => rfgen1_dout_i,
- dout_q => rfgen1_dout_q,
- din_vld => '1',
- dout_vld => rfgen1_dout_vld
- );
-
- rfgen2: mix
- GENERIC MAP
- (
- nbits_din => nbits_in,
- nbits_din_frac => nbits_in_frac,
- nbits_dout => nbits_in,
- nbits_dout_frac => nbits_in_frac,
- nbits_phase => rfgen_nbits_phase,
- nbits_freq => rfgen_nbits_freq
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- nco_rst => rfgen_nco_rst,
- nco_en => rfgen_nco_en,
- freq_in => rfgen2_freq_in,
- phase_in => rfgen2_phase_in,
- din_i => rfgen_din_i,
- din_q => rfgen_din_q,
- dout_i => rfgen2_dout_i,
- dout_q => rfgen2_dout_q,
- din_vld => '1',
- dout_vld => rfgen2_dout_vld
- );
-
- rfgen3: mix
- GENERIC MAP
- (
- nbits_din => nbits_in,
- nbits_din_frac => nbits_in_frac,
- nbits_dout => nbits_in,
- nbits_dout_frac => nbits_in_frac,
- nbits_phase => rfgen_nbits_phase,
- nbits_freq => rfgen_nbits_freq
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- nco_rst => rfgen_nco_rst,
- nco_en => rfgen_nco_en,
- freq_in => rfgen3_freq_in,
- phase_in => rfgen3_phase_in,
- din_i => rfgen_din_i,
- din_q => rfgen_din_q,
- dout_i => rfgen3_dout_i,
- dout_q => rfgen3_dout_q,
- din_vld => '1',
- dout_vld => rfgen3_dout_vld
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- rfgen_dout_i <= resize(0.333*rfgen1_dout_i + 0.333*rfgen2_dout_i + 0.333*rfgen3_dout_i, rfgen_dout_i);
- rfgen_dout_q <= resize(0.333*rfgen1_dout_q + 0.333*rfgen2_dout_q + 0.333*rfgen3_dout_q, rfgen_dout_q);
-
- ddc_din_i <= rfgen_dout_i;
- ddc_din_q <= to_sfixed(0.0, ddc_din_q);
- ddc_din_vld <= rfgen1_dout_vld and rfgen2_dout_vld and rfgen3_dout_vld;
-
- ddc_i_out_f <= to_real(ddc_dout_i);
- ddc_q_out_f <= to_real(ddc_dout_q);
-
- rfgen_i_out_f <= to_real(rfgen_dout_i);
- rfgen_q_out_f <= to_real(rfgen_dout_q);
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- rst <= '0';
-
- wait for 2*PERIOD;
- -------------------------------------------
- -- Program gains
- wait for 2*PERIOD;
- wait until rising_edge(clk);
-
- -- start DDC
- ddc_phase_in <= to_unsigned(0,lo_nbits_phase);
- ddc_freq_in <= to_unsigned(lo_freq_word,lo_nbits_freq);
- wait until rising_edge(clk);
- ddc_nco_en <= '1';
-
- wait for 20*PERIOD;
- fileout_enable <= '1';
-
- wait;
- END PROCESS;
-
-
- rfgen_ctrl : PROCESS
-
- BEGIN
- wait until rising_edge(clk) and rst = '0';
- rfgen1_freq_in <= to_unsigned(rfgen1_freq_word,rfgen_nbits_freq);
- rfgen1_phase_in <= to_unsigned(0,rfgen_nbits_phase);
- rfgen2_freq_in <= to_unsigned(rfgen2_freq_word,rfgen_nbits_freq);
- rfgen2_phase_in <= to_unsigned(0,rfgen_nbits_phase);
- rfgen3_freq_in <= to_unsigned(rfgen3_freq_word,rfgen_nbits_freq);
- rfgen3_phase_in <= to_unsigned(0,rfgen_nbits_phase);
- wait until rising_edge(clk);
- rfgen_nco_en <= '1';
-
-
- wait;
- END PROCESS;
-
- tb_param : PROCESS
- file RESULT_R: text open write_mode is "ratio.txt";
- file RESULT_N: text open write_mode is "nstages.txt";
- file FSAMPLE: text open write_mode is "fa.txt";
- variable L: line;
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait until rising_edge(clk) and rst = '0';
- fprint(RESULT_R, L,"%s\n", natural'image(cic_ratio));
- fprint(RESULT_N, L,"%s\n", natural'image(cic_nstages));
- fprint(FSAMPLE, L,"%s\n", real'image(fa));
- wait;
-
- END PROCESS;
-
- tb_fo : PROCESS(clk)
- file RESULT_Ii: text open write_mode is "i_in.txt";
- file RESULT_Qi: text open write_mode is "q_in.txt";
- file RESULT_Ifir: text open write_mode is "i_fir.txt";
- file RESULT_Qfir: text open write_mode is "q_fir.txt";
- file RESULT_Idec: text open write_mode is "i_dec.txt";
- file RESULT_Qdec: text open write_mode is "q_dec.txt";
- variable L: line;
-
- BEGIN
- if rising_edge(clk) then
- if fileout_enable = '1' then
- if ddc_din_vld = '1' then
- fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i)));
- fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q)));
- end if;
- if ddc_dout_vld = '1' then
- fprint(RESULT_Ifir, L,"%s\n", REAL'image(to_real(ddc_dout_i)));
- fprint(RESULT_Qfir, L,"%s\n", REAL'image(to_real(ddc_dout_q)));
- end if;
- if ddc_dec_vld = '1' then
- fprint(RESULT_Idec, L,"%s\n", REAL'image(to_real(ddc_dec_i)));
- fprint(RESULT_Qdec, L,"%s\n", REAL'image(to_real(ddc_dec_q)));
- end if;
- end if;
- end if;
- END PROCESS;
-
-END;
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo
deleted file mode 100644
index 40910c8..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo
+++ /dev/null
@@ -1,14 +0,0 @@
-vmap ieee_proposed ../../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/cic_c_pipe.vhd"
-vcom -explicit -93 "../src/tb_cic_c_pipe.vhd"
-vsim -t 1ps -lib work tb_cic_c_pipe
-do {tb_cic_c_pipe.wdo}
-view wave
-view structure
-view signals
-run 500ns
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo
deleted file mode 100644
index 901e089..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo
+++ /dev/null
@@ -1,26 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cic_c_pipe/clk
-add wave -noupdate -format Logic /tb_cic_c_pipe/srst
-add wave -noupdate -format Logic /tb_cic_c_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/din
-add wave -noupdate -format Literal /tb_cic_c_pipe/diff_delay
-add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/dout
-add wave -noupdate -format Logic /tb_cic_c_pipe/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/uut/word_pipe
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {500608 ps}
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo
deleted file mode 100644
index b0525de..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/cic_i_pipe.vhd"
-vcom -explicit -93 "../src/cic_c_pipe.vhd"
-vcom -explicit -93 "../src/cic_decim_pipe.vhd"
-vcom -explicit -93 "../src/tb_cic_decim_pipe.vhd"
-vsim -t 1ps -lib work tb_cic_decim_pipe
-do {tb_cic_decim_pipe.wdo}
-view wave
-view structure
-view signals
-run 140us
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo
deleted file mode 100644
index 0296151..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo
+++ /dev/null
@@ -1,39 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cic_decim_pipe/clk
-add wave -noupdate -format Logic /tb_cic_decim_pipe/srst
-add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout
-add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out
-add wave -noupdate -divider Debug
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/xr
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/yr
-add wave -noupdate -divider -height 50 Trenn
-add wave -noupdate -format Literal -radix decimal -expand /tb_cic_decim_pipe/uut/word_i_pipe
-add wave -noupdate -format Literal /tb_cic_decim_pipe/uut/vld_i_pipe
-add wave -noupdate -format Logic /tb_cic_decim_pipe/clk
-add wave -noupdate -format Logic /tb_cic_decim_pipe/srst
-add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout
-add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/uut/word_c_pipe
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {34745455 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {147 us}
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo
deleted file mode 100644
index b1c190a..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo
+++ /dev/null
@@ -1,14 +0,0 @@
-vmap ieee_proposed ../../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/cic_i_pipe.vhd"
-vcom -explicit -93 "../src/tb_cic_i_pipe.vhd"
-vsim -t 1ps -lib work tb_cic_i_pipe
-do {tb_cic_i_pipe.wdo}
-view wave
-view structure
-view signals
-run 500ns
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo
deleted file mode 100644
index 140032c..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo
+++ /dev/null
@@ -1,30 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cic_i_pipe/srst
-add wave -noupdate -format Logic /tb_cic_i_pipe/clk
-add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din
-add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout
-add wave -noupdate -format Logic /tb_cic_i_pipe/srst
-add wave -noupdate -format Logic /tb_cic_i_pipe/clk
-add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din
-add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {373333 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {1050 ns}
diff --git a/lib/radio/decimator/CIC/src/cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/cic_c_pipe.vhd
deleted file mode 100644
index 41063f0..0000000
--- a/lib/radio/decimator/CIC/src/cic_c_pipe.vhd
+++ /dev/null
@@ -1,104 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage_pre - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cic_c_pipe is
-Generic
-(
- max_diff_delay : integer := 1;
- max_width : integer := 32;
- max_width_frac : integer := 20
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- diff_delay : in natural range 1 to max_diff_delay;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
-);
-end cic_c_pipe;
-
-architecture Behavioral of cic_c_pipe is
-
-subtype word_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-type word_pipe_t is array (1 to max_diff_delay) of word_t;
-
-signal word_pipe : word_pipe_t;
-
-------------------------------------------------------------
-begin
-
-------------------------------------------------------------
-delay_pipe_proc:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
--- for i in 1 to max_diff_delay loop
--- word_pipe(i) <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
--- end loop;
- elsif vld_in = '1' then
- word_pipe(1) <= resize(din, word_pipe(1));
- for i in 2 to max_diff_delay loop
- word_pipe(i) <= word_pipe(i-1);
- end loop;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-comb_proc:
- process(clk)
- variable x0, x1 : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-
- begin
- if rising_edge(clk) then
- vld_out <= '0';
- x0 := resize(din, x0);
- x1 := word_pipe(diff_delay);
- if rst = '1' then
- dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
- elsif vld_in = '1' then
- vld_out <= '1';
- dout <= resize(x0 - x1, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
-
diff --git a/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd b/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
deleted file mode 100644
index 139c81a..0000000
--- a/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
+++ /dev/null
@@ -1,203 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_mix_cpx
--- Module Name: tb_mix_cpx.vhd
--- Project Name: mix_cpx
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.utils_pkg.all;
-
-ENTITY cic_decim_pipe IS
- Generic
- (
- nstages : integer := 3;
- diff_delay : integer := 1;
- ratio : integer := 64;
- scale_nbits : integer := 9;
- in_width : integer := 32;
- in_width_frac : integer := 20;
- out_width : integer := 32;
- out_width_frac : integer := 20
- );
- Port
- (
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
- );
-END cic_decim_pipe;
-
-ARCHITECTURE behavior OF cic_decim_pipe IS
-
- COMPONENT cic_i_pipe
- GENERIC
- (
- max_width : integer;
- max_width_frac : integer
- );
- PORT
- (
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
- COMPONENT cic_c_pipe
- GENERIC
- (
- max_diff_delay : integer;
- max_width : integer;
- max_width_frac : integer
- );
- PORT
- (
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- diff_delay : in natural range 1 to max_diff_delay;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
- constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio)**real(nstages)));
-
- constant integ_nbits : natural := in_width + max_gain_bits;
- constant integ_nbits_frac : natural := integ_nbits - (in_width - in_width_frac);
-
- constant comb_nbits : natural := out_width+1;
- constant comb_nbits_frac : natural := out_width_frac+1;
-
- subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
- type word_i_pipe_t is array (0 to nstages) of word_i_t;
-
- signal word_i_pipe : word_i_pipe_t;
- signal vld_i_pipe : unsigned (0 to nstages);
- signal vld_i : std_logic;
-
- subtype word_c_t is sfixed(shi(comb_nbits, comb_nbits_frac) downto slo(comb_nbits, comb_nbits_frac));
- type word_c_pipe_t is array (0 to nstages) of word_c_t;
-
- signal word_c_pipe : word_c_pipe_t;
- signal vld_c_pipe : unsigned (0 to nstages);
- signal vld_c : std_logic;
-
- signal resample_cnt : natural range 1 to ratio;
- signal resample_vld : std_logic;
-
-BEGIN
-
- assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note;
- assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note;
- assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note;
-
- vld_i <= vld_i_pipe(nstages);
-
-input_scale:
- process(clk)
- variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
- variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
- variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
- begin
- if rising_edge(clk) then
- x := resize(din, x);
- xs := x sra scale_nbits;
- word_i_pipe(0) <= xs;
- vld_i_pipe(0) <= vld_in;
- end if;
- end process;
-
- gen_i_stages:
- for i in 1 to nstages generate
- begin
- inst_cic_i_pipe: cic_i_pipe
- GENERIC MAP
- (
- max_width => integ_nbits,
- max_width_frac => integ_nbits_frac
- )
- PORT MAP
- (
- clk => clk,
- rst => rst,
- vld_in => vld_i_pipe(i-1),
- din => word_i_pipe(i-1),
- dout => word_i_pipe(i),
- vld_out => vld_i_pipe(i)
- );
- end generate;
-
- word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0), fixed_wrap, fixed_truncate);
- vld_c_pipe(0) <= resample_vld;
- vld_c <= vld_c_pipe(nstages);
-
- vld_out <= vld_c;
-
- gen_c_stages:
- for i in 1 to nstages generate
- begin
- inst_cic_c_pipe: cic_c_pipe
- GENERIC MAP
- (
- max_diff_delay => diff_delay,
- max_width => comb_nbits,
- max_width_frac => comb_nbits_frac
- )
- PORT MAP
- (
- clk => clk,
- rst => rst,
- vld_in => vld_c_pipe(i-1),
- diff_delay => diff_delay,
- din => word_c_pipe(i-1),
- dout => word_c_pipe(i),
- vld_out => vld_c_pipe(i)
- );
- end generate;
-
-resampler_proc:
- process(clk)
- begin
- if rising_edge(clk) then
- resample_vld <= '0';
- if rst = '1' then
- resample_cnt <= 1;
- elsif vld_i = '1' then
- if resample_cnt = ratio then
- resample_vld <= '1';
- resample_cnt <= 1;
- else
- resample_cnt <= resample_cnt + 1;
- end if ;
- end if;
- end if;
- end process;
-
- dout <= resize(word_c_pipe(nstages), shi(out_width, out_width_frac), slo(out_width, out_width_frac));
-
-END;
diff --git a/lib/radio/decimator/CIC/src/cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/cic_i_pipe.vhd
deleted file mode 100644
index 0880ca3..0000000
--- a/lib/radio/decimator/CIC/src/cic_i_pipe.vhd
+++ /dev/null
@@ -1,81 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage_pre - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cic_i_pipe is
-Generic
-(
- max_width : integer := 32;
- max_width_frac : integer := 20
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
-);
-end cic_i_pipe;
-
-architecture Behavioral of cic_i_pipe is
-
-signal accu : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-
-------------------------------------------------------------
-begin
-
- dout <= resize(accu, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
-
-------------------------------------------------------------
-integ_proc:
- process(clk)
- variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
- begin
- if rising_edge(clk) then
- vld_out <= '0';
- if rst = '1' then
- accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
- elsif vld_in = '1' then
- vld_out <= '1';
- x := resize(din, x);
- accu <= resize(x + accu, accu);
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
-
diff --git a/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
deleted file mode 100644
index 70e3007..0000000
--- a/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
+++ /dev/null
@@ -1,98 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_mix_cpx
--- Module Name: tb_mix_cpx.vhd
--- Project Name: mix_cpx
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
-entity syn_cic_c_pipe is
-Generic
-(
- max_diff_delay : integer := 2;
- max_width : integer := 32;
- max_width_frac : integer := 20
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- diff_delay : in natural range 1 to max_diff_delay;
- din : in signed(max_width-1 downto 0);
- dout : out signed(max_width-1 downto 0);
- vld_out : out std_logic
-);
-end syn_cic_c_pipe;
-
-ARCHITECTURE behavior OF syn_cic_c_pipe IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT cic_c_pipe
- GENERIC
- (
- max_diff_delay : integer;
- max_width : integer;
- max_width_frac : integer
- );
- PORT
- (
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- diff_delay : in natural range 1 to max_diff_delay;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
- --Inputs
- SIGNAL sdin : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-
- --Outputs
- SIGNAL sdout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: cic_c_pipe
- GENERIC MAP
- (
- max_diff_delay => max_diff_delay,
- max_width => max_width,
- max_width_frac => max_width_frac
- )
- PORT MAP
- (
- clk => clk,
- rst => rst,
- vld_in => vld_in,
- diff_delay => diff_delay,
- din => sdin,
- dout => sdout,
- vld_out => vld_out
- );
-
- sdin <= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
- dout <= signed(sdout);
-
-END;
diff --git a/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
deleted file mode 100644
index 52428ed..0000000
--- a/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
+++ /dev/null
@@ -1,92 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_mix_cpx
--- Module Name: tb_mix_cpx.vhd
--- Project Name: mix_cpx
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
-entity syn_cic_i_pipe is
-Generic
-(
- max_width : integer := 32;
- max_width_frac : integer := 20
-);
-Port
-(
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- din : in signed(max_width-1 downto 0);
- dout : out signed(max_width-1 downto 0);
- vld_out : out std_logic
-);
-end syn_cic_i_pipe;
-
-ARCHITECTURE behavior OF syn_cic_i_pipe IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT cic_i_pipe
- GENERIC
- (
- max_width : integer;
- max_width_frac : integer
- );
- PORT
- (
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
- --Inputs
- SIGNAL sdin : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-
- --Outputs
- SIGNAL sdout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: cic_i_pipe
- GENERIC MAP
- (
- max_width => max_width,
- max_width_frac => max_width_frac
- )
- PORT MAP
- (
- clk => clk,
- rst => rst,
- vld_in => vld_in,
- din => sdin,
- dout => sdout,
- vld_out => vld_out
- );
-
- sdin <= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
- dout <= signed(sdout);
-
-END;
diff --git a/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd
deleted file mode 100644
index d36268d..0000000
--- a/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd
+++ /dev/null
@@ -1,136 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_mix_cpx
--- Module Name: tb_mix_cpx.vhd
--- Project Name: mix_cpx
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.PCK_FIO.all;
-use work.fixed_util_pkg.all;
-
-ENTITY tb_cic_c_pipe IS
- Generic
- (
- max_width : integer := 32;
- max_width_frac : integer := 20
- );
-END tb_cic_c_pipe;
-
-ARCHITECTURE behavior OF tb_cic_c_pipe IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT cic_c_pipe
- GENERIC
- (
- max_diff_delay : integer;
- max_width : integer;
- max_width_frac : integer
- );
- PORT
- (
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- diff_delay : in natural range 1 to max_diff_delay;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
- --Constants
- constant PERIOD : time := 10 ns;
-
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL vld_in : std_logic := '0';
- SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
- SIGNAL diff_delay : natural := 1;
-
- --Outputs
- SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
- SIGNAL vld_out : std_logic;
-
- SIGNAL fileout_enable : std_logic := '0';
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: cic_c_pipe
- GENERIC MAP
- (
- max_diff_delay => 2,
- max_width => max_width,
- max_width_frac => max_width_frac
- )
- PORT MAP
- (
- clk => clk,
- rst => srst,
- vld_in => vld_in,
- diff_delay => diff_delay,
- din => din,
- dout => dout,
- vld_out => vld_out
- );
-
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
- wait until rising_edge(clk);
- din <= to_sfixed(0.0, din);
- vld_in <= '1';
-
- wait for 9*PERIOD;
- wait until rising_edge(clk);
-
- din <= to_sfixed(0.5, din);
-
- wait for 9*PERIOD;
- wait until rising_edge(clk);
-
- din <= to_sfixed(0.0, din);
-
- wait for 9*PERIOD;
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
-END;
diff --git a/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
deleted file mode 100644
index f6f1d91..0000000
--- a/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
+++ /dev/null
@@ -1,153 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_mix_cpx
--- Module Name: tb_mix_cpx.vhd
--- Project Name: mix_cpx
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.PCK_FIO.all;
-use work.fixed_util_pkg.all;
-
-ENTITY tb_cic_decim_pipe IS
- Generic
- (
- nstages : integer := 3;
- ratio : integer := 64;
- scale_nbits : integer := 18;
- in_width : integer := 18;
- in_width_frac : integer := 16;
- out_width : integer := 18;
- out_width_frac : integer := 16
- );
-END tb_cic_decim_pipe;
-
-ARCHITECTURE behavior OF tb_cic_decim_pipe IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT cic_decim_pipe
- GENERIC
- (
- nstages : integer;
- ratio : integer;
- scale_nbits : integer;
- in_width : integer;
- in_width_frac : integer;
- out_width : integer;
- out_width_frac : integer
- );
- PORT
- (
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
- --Constants
- constant PERIOD : time := 10 ns;
-
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL vld_in : std_logic := '0';
- SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
-
- --Outputs
- SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
- SIGNAL vld_out : std_logic;
-
- SIGNAL fileout_enable : std_logic := '0';
-
- signal XR, YR : real;
-
-BEGIN
-
- XR <= to_real(din);
- YR <= to_real(dout);
-
- -- Instantiate the Unit Under Test (UUT)
- uut : cic_decim_pipe
- GENERIC MAP
- (
- nstages => nstages,
- ratio => ratio,
- scale_nbits => scale_nbits,
- in_width => in_width,
- in_width_frac => in_width_frac,
- out_width => out_width,
- out_width_frac => out_width_frac
- )
- PORT MAP
- (
- clk => clk,
- rst => srst,
- vld_in => vld_in,
- din => din,
- dout => dout,
- vld_out => vld_out
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
-
- ------------------------------------------
- wait for 2*PERIOD;
- wait until rising_edge(clk);
- din <= to_sfixed(0.0, din);
- vld_in <= '1';
-
- wait for 49*PERIOD;
- wait until rising_edge(clk);
-
- din <= to_sfixed(0.5, din);
-
- wait for 4999*PERIOD;
- wait until rising_edge(clk);
-
- din <= to_sfixed(-0.5, din);
-
- wait for 99*PERIOD;
- wait until rising_edge(clk);
-
- din <= to_sfixed(0.0, din);
-
- wait for 499*PERIOD;
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait;
- END PROCESS;
-
-END;
diff --git a/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd
deleted file mode 100644
index b3ae7d5..0000000
--- a/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd
+++ /dev/null
@@ -1,126 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_mix_cpx
--- Module Name: tb_mix_cpx.vhd
--- Project Name: mix_cpx
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.PCK_FIO.all;
-use work.fixed_util_pkg.all;
-
-ENTITY tb_cic_i_pipe IS
- Generic
- (
- max_width : integer := 32;
- max_width_frac : integer := 20
- );
-END tb_cic_i_pipe;
-
-ARCHITECTURE behavior OF tb_cic_i_pipe IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT cic_i_pipe
- GENERIC
- (
- max_width : integer;
- max_width_frac : integer
- );
- PORT
- (
- clk : in std_logic;
- rst : in std_logic;
- vld_in : in std_logic;
- din : in sfixed;
- dout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
- --Constants
- constant PERIOD : time := 10 ns;
-
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL vld_in : std_logic := '0';
- SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-
- --Outputs
- SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
- SIGNAL vld_out : std_logic;
-
- SIGNAL fileout_enable : std_logic := '0';
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: cic_i_pipe
- GENERIC MAP
- (
- max_width => max_width,
- max_width_frac => max_width_frac
- )
- PORT MAP
- (
- clk => clk,
- rst => srst,
- vld_in => vld_in,
- din => din,
- dout => dout,
- vld_out => vld_out
- );
-
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
- wait until rising_edge(clk);
- din <= to_sfixed(0.0, din);
- vld_in <= '1';
-
- wait for 9*PERIOD;
- wait until rising_edge(clk);
-
- din <= to_sfixed(0.5, din);
-
- wait for 9*PERIOD;
- wait until rising_edge(clk);
- vld_in <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
-END;
diff --git a/lib/radio/mix/sim/tb_mix_cpx.fdo b/lib/radio/mix/sim/tb_mix_cpx.fdo
deleted file mode 100644
index 78a7729..0000000
--- a/lib/radio/mix/sim/tb_mix_cpx.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/mix_cpx.vhd"
-vcom -explicit -93 "../src/tb_mix_cpx.vhd"
-vsim -t 1ps -lib work tb_mix_cpx
-do {tb_mix_cpx.wdo}
-view wave
-view structure
-view signals
-run 500ns
diff --git a/lib/radio/mix/sim/tb_mix_cpx.wdo b/lib/radio/mix/sim/tb_mix_cpx.wdo
deleted file mode 100644
index c84c651..0000000
--- a/lib/radio/mix/sim/tb_mix_cpx.wdo
+++ /dev/null
@@ -1,42 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_mix_cpx/clk
-add wave -noupdate -format Logic /tb_mix_cpx/srst
-add wave -noupdate -divider {Fixed In}
-add wave -noupdate -format Logic /tb_mix_cpx/in_valid
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_re_in
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_im_in
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_re_in
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_im_in
-add wave -noupdate -divider {Fixed OUT}
-add wave -noupdate -format Logic /tb_mix_cpx/out_valid
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_re_out
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_im_out
-add wave -noupdate -divider {Convenient real out}
-add wave -noupdate -format Literal /tb_mix_cpx/x_re
-add wave -noupdate -format Literal /tb_mix_cpx/x_im
-add wave -noupdate -format Literal /tb_mix_cpx/y_re
-add wave -noupdate -format Literal /tb_mix_cpx/y_im
-add wave -noupdate -format Literal /tb_mix_cpx/z_re
-add wave -noupdate -format Literal /tb_mix_cpx/z_im
-add wave -noupdate -format Logic /tb_mix_cpx/fileout_enable
-add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_left
-add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_right
-add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_left
-add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_right
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {90000 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {348406 ps}
diff --git a/lib/radio/mix/sim/tb_mix_real.fdo b/lib/radio/mix/sim/tb_mix_real.fdo
deleted file mode 100644
index 0dbc45f..0000000
--- a/lib/radio/mix/sim/tb_mix_real.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/mix_real.vhd"
-vcom -explicit -93 "../src/tb_mix_real.vhd"
-vsim -t 1ps -lib work tb_mix_real
-do {tb_mix_real.wdo}
-view wave
-view structure
-view signals
-run 500ns
diff --git a/lib/radio/mix/sim/tb_mix_real.wdo b/lib/radio/mix/sim/tb_mix_real.wdo
deleted file mode 100644
index 6643ce3..0000000
--- a/lib/radio/mix/sim/tb_mix_real.wdo
+++ /dev/null
@@ -1,36 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_mix_real/clk
-add wave -noupdate -format Logic /tb_mix_real/srst
-add wave -noupdate -divider {Fixed In}
-add wave -noupdate -format Logic /tb_mix_real/in_valid
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/x_re_din
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_re_din
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_im_din
-add wave -noupdate -divider {Fixed OUT}
-add wave -noupdate -format Logic /tb_mix_real/out_valid
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_re_dout
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_im_dout
-add wave -noupdate -divider {Convenient real out}
-add wave -noupdate -format Literal /tb_mix_real/x_re
-add wave -noupdate -format Literal /tb_mix_real/y_re
-add wave -noupdate -format Literal /tb_mix_real/y_im
-add wave -noupdate -format Literal /tb_mix_real/z_re
-add wave -noupdate -format Literal /tb_mix_real/z_im
-add wave -noupdate -format Logic /tb_mix_real/fileout_enable
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {120000 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {348406 ps}
diff --git a/lib/radio/mix/sim/tb_undc_real.fdo b/lib/radio/mix/sim/tb_undc_real.fdo
deleted file mode 100644
index 2450220..0000000
--- a/lib/radio/mix/sim/tb_undc_real.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/undc_real.vhd"
-vcom -explicit -93 "../src/tb_undc_real.vhd"
-vsim -t 1ps -lib work tb_undc_real
-do {tb_undc_real.wdo}
-view wave
-view structure
-view signals
-run 500us
diff --git a/lib/radio/mix/sim/tb_undc_real.wdo b/lib/radio/mix/sim/tb_undc_real.wdo
deleted file mode 100644
index f965905..0000000
--- a/lib/radio/mix/sim/tb_undc_real.wdo
+++ /dev/null
@@ -1,38 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_undc_real/clk
-add wave -noupdate -format Logic /tb_undc_real/srst
-add wave -noupdate -format Logic /tb_undc_real/din_valid
-add wave -noupdate -format Logic /tb_undc_real/kin_valid
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/kin
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dc_out
-add wave -noupdate -format Logic /tb_undc_real/dout_valid
-add wave -noupdate -format Literal /tb_undc_real/k
-add wave -noupdate -format Literal /tb_undc_real/x
-add wave -noupdate -format Literal /tb_undc_real/y
-add wave -noupdate -format Literal /tb_undc_real/dc
-add wave -noupdate -divider UUT
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/k
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/x
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y1
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y2
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/dc
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {97905405 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {157500 ns}
diff --git a/lib/radio/mix/src/mix_cpx.vhd b/lib/radio/mix/src/mix_cpx.vhd
deleted file mode 100644
index 3df161e..0000000
--- a/lib/radio/mix/src/mix_cpx.vhd
+++ /dev/null
@@ -1,171 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: mix_cpx - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity mix_cpx is
-Generic
-(
- nbits_in : integer := 12;
- nbits_in_frac : integer := 12;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 12;
- nbits_scale_z : integer := 0;
- has_in_reg : boolean := false;
- has_pipe_reg : boolean := false;
- has_out_reg : boolean := false;
- rounding : fixed_round_style_type := fixed_round;
- saturating : fixed_overflow_style_type := fixed_saturate
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_re_in : in sfixed;
- x_im_in : in sfixed;
- y_re_in : in sfixed;
- y_im_in : in sfixed;
- out_valid : out std_logic;
- z_re_out : out sfixed;
- z_im_out : out sfixed
-);
-end mix_cpx;
-
-architecture Behavioral of mix_cpx is
-constant nbits_prod : integer := nbits_out + nbits_scale_z;
-constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
-
-signal x_re, x_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal p_re_left, p_re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-signal p_im_left, p_im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-signal valid, p_valid : std_logic;
-------------------------------------------------------------
-begin
-
-
-------------------------------------------------------------
- proc_in_reg: process(srst, clk, in_valid, x_re_in, x_im_in, y_re_in, y_im_in)
- begin
- if has_in_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- x_re <= to_sfixed(0, x_re);
- x_im <= to_sfixed(0, x_im);
- y_re <= to_sfixed(0, y_re);
- y_im <= to_sfixed(0, y_im);
- valid <= '0';
- else
- valid <= in_valid;
- if in_valid = '1' then
- x_re <= x_re_in;
- x_im <= x_im_in;
- y_re <= y_re_in;
- y_im <= y_im_in;
- end if;
- end if;
- end if;
- else
- x_re <= x_re_in;
- x_im <= x_im_in;
- y_re <= y_re_in;
- y_im <= y_im_in;
- valid <= in_valid;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_pipe_reg: process(srst, clk, valid, x_re, x_im, y_re, y_im)
- variable re_left, re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
- variable im_left, im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
-
- begin
- re_left := resize(x_re * y_re, re_left);
- re_right := resize(x_im * y_im, re_right);
- im_left := resize(x_re * y_im, im_left);
- im_right := resize(x_im * y_re, im_right);
- if has_pipe_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- p_re_left <= to_sfixed(0, p_re_left);
- p_re_right <= to_sfixed(0, p_re_right);
- p_im_left <= to_sfixed(0, p_im_left);
- p_im_right <= to_sfixed(0, p_im_right);
- p_valid <= '0';
- else
- p_re_left <= re_left;
- p_re_right <= re_right;
- p_im_left <= im_left;
- p_im_right <= im_right;
- p_valid <= valid;
- end if;
- end if;
- else
- p_re_left <= re_left;
- p_re_right <= re_right;
- p_im_left <= im_left;
- p_im_right <= im_right;
- p_valid <= valid;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_out_reg: process(srst, clk, p_valid, p_re_left, p_re_right, p_im_left, p_im_right)
- variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- begin
- sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, saturating, rounding);
- sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, saturating, rounding);
- if has_out_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- z_re_out <= to_sfixed(0, re);
- z_im_out <= to_sfixed(0, im);
- out_valid <= '0';
- else
- z_re_out <= sum_re;
- z_im_out <= sum_im;
- out_valid <= p_valid;
- end if;
- end if;
- else
- z_re_out <= re;
- z_im_out <= im;
- out_valid <= p_valid;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/mix/src/mix_real.vhd b/lib/radio/mix/src/mix_real.vhd
deleted file mode 100644
index 37e96de..0000000
--- a/lib/radio/mix/src/mix_real.vhd
+++ /dev/null
@@ -1,160 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: mix_cpx - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity mix_real is
-Generic
-(
- nbits_in : integer := 12;
- nbits_in_frac : integer := 12;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 12;
- nbits_scale_z : integer := 0;
- has_in_reg : boolean := false;
- has_pipe_reg : boolean := false;
- has_out_reg : boolean := false;
- rounding : fixed_round_style_type := fixed_round;
- saturating : fixed_overflow_style_type := fixed_saturate
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_re_din : in sfixed;
- y_re_din : in sfixed;
- y_im_din : in sfixed;
- out_valid : out std_logic;
- z_re_dout : out sfixed;
- z_im_dout : out sfixed
-);
-end mix_real;
-
-architecture Behavioral of mix_real is
-
-constant nbits_prod : integer := nbits_out + nbits_scale_z;
-constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
-
-signal x_re : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal p_re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-signal p_im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-signal valid, p_valid : std_logic;
-------------------------------------------------------------
-begin
-
-
-------------------------------------------------------------
- proc_in_reg: process(srst, clk, in_valid, x_re_din, y_re_din, y_im_din)
- begin
- if has_in_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- x_re <= to_sfixed(0, x_re);
- y_re <= to_sfixed(0, y_re);
- y_im <= to_sfixed(0, y_im);
- valid <= '0';
- else
- valid <= in_valid;
- if in_valid = '1' then
- x_re <= x_re_din;
- y_re <= y_re_din;
- y_im <= y_im_din;
- end if;
- end if;
- end if;
- else
- x_re <= x_re_din;
- y_re <= y_re_din;
- y_im <= y_im_din;
- valid <= in_valid;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_pipe_reg: process(srst, clk, valid, x_re, y_re, y_im)
- variable re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
- variable im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-
- begin
- re_left := resize(x_re * y_re, re_left);
- im_left := resize(x_re * y_im, im_left);
- if has_pipe_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- p_re_left <= to_sfixed(0, p_re_left);
- p_im_left <= to_sfixed(0, p_im_left);
- p_valid <= '0';
- else
- p_re_left <= re_left;
- p_im_left <= im_left;
- p_valid <= valid;
- end if;
- end if;
- else
- p_re_left <= re_left;
- p_im_left <= im_left;
- p_valid <= valid;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_out_reg: process(srst, clk, p_valid, p_re_left, p_im_left)
- variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- begin
- sum_re := resize(scalb(p_re_left, nbits_scale_z), re, saturating, rounding);
- sum_im := resize(scalb(p_im_left, nbits_scale_z), im, saturating, rounding);
- if has_out_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- z_re_dout <= to_sfixed(0, re);
- z_im_dout <= to_sfixed(0, im);
- out_valid <= '0';
- else
- z_re_dout <= sum_re;
- z_im_dout <= sum_im;
- out_valid <= p_valid;
- end if;
- end if;
- else
- z_re_dout <= re;
- z_im_dout <= im;
- out_valid <= p_valid;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/mix/src/tb_mix_cpx.vhd b/lib/radio/mix/src/tb_mix_cpx.vhd
deleted file mode 100644
index 5eac130..0000000
--- a/lib/radio/mix/src/tb_mix_cpx.vhd
+++ /dev/null
@@ -1,211 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_mix_cpx
--- Module Name: tb_mix_cpx.vhd
--- Project Name: mix_cpx
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_mix_cpx IS
- Generic (
- nbits_in : integer := 24;
- nbits_in_frac : integer := 24;
- nbits_out : integer := 24;
- nbits_out_frac : integer := 24;
- nbits_scale_z : integer := 0;
- has_in_reg : boolean := true;
- has_pipe_reg : boolean := true;
- has_out_reg : boolean := true;
- rounding : fixed_round_style_type := fixed_round;
- saturating : fixed_overflow_style_type := fixed_saturate
- );
-END tb_mix_cpx;
-
-ARCHITECTURE behavior OF tb_mix_cpx IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT mix_cpx
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- nbits_scale_z : integer;
- has_in_reg : boolean;
- has_pipe_reg : boolean;
- has_out_reg : boolean;
- rounding : fixed_round_style_type;
- saturating : fixed_overflow_style_type
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_re_in : in sfixed;
- x_im_in : in sfixed;
- y_re_in : in sfixed;
- y_im_in : in sfixed;
- out_valid : out std_logic;
- z_re_out : out sfixed;
- z_im_out : out sfixed
- );
- END COMPONENT;
-
- --Constants
- constant PERIOD : time := 10 ns;
-
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL in_valid : std_logic := '0';
- SIGNAL x_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
- SIGNAL x_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
- SIGNAL y_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
- SIGNAL y_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-
- --Outputs
- SIGNAL z_re_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- SIGNAL z_im_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- SIGNAL out_valid : std_logic;
-
- SIGNAL fileout_enable : std_logic := '0';
- SIGNAL x_re : real := 0.0;
- SIGNAL x_im : real := 0.0;
- SIGNAL y_re : real := 0.0;
- SIGNAL y_im : real := 0.0;
- SIGNAL z_re : real := 0.0;
- SIGNAL z_im : real := 0.0;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: mix_cpx
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- nbits_scale_z => nbits_scale_z,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- in_valid => in_valid,
- x_re_in => x_re_in,
- x_im_in => x_im_in,
- y_re_in => y_re_in,
- y_im_in => y_im_in,
- out_valid => out_valid,
- z_re_out => z_re_out,
- z_im_out => z_im_out
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
- wait until rising_edge(clk);
- x_re_in <= to_sfixed(0.5, x_re_in);
- x_im_in <= to_sfixed(0.5, x_im_in);
- y_re_in <= to_sfixed(0.5, y_re_in);
- y_im_in <= to_sfixed(0.5, y_im_in);
- in_valid <= '1';
- wait until rising_edge(clk);
- in_valid <= '0';
- wait for 5*PERIOD;
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_in <= to_sfixed(0.125, x_re_in);
- x_im_in <= to_sfixed(0.25, x_im_in);
- y_re_in <= to_sfixed(0.25, y_re_in);
- y_im_in <= to_sfixed(0.125, y_im_in);
- in_valid <= '1';
- wait until rising_edge(clk);
- in_valid <= '0';
- wait for 5*PERIOD;
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_in <= to_sfixed(0.125, x_re_in);
- x_im_in <= to_sfixed(-0.25, x_im_in);
- y_re_in <= to_sfixed(0.25, y_re_in);
- y_im_in <= to_sfixed(0.125, y_im_in);
- in_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_in <= to_sfixed(0.125, x_re_in);
- x_im_in <= to_sfixed(-0.25, x_im_in);
- y_re_in <= to_sfixed(0.25, y_re_in);
- y_im_in <= to_sfixed(0.125, y_im_in);
- in_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_in <= to_sfixed(0.3, x_re_in);
- x_im_in <= to_sfixed(0.0, x_im_in);
- y_re_in <= to_sfixed(-0.5, y_re_in);
- y_im_in <= to_sfixed(0.5, y_im_in);
- in_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_in <= to_sfixed(0.0, x_re_in);
- x_im_in <= to_sfixed(-0.7071, x_im_in);
- y_re_in <= to_sfixed(0.0, y_re_in);
- y_im_in <= to_sfixed(-0.7071, y_im_in);
- in_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- in_valid <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- x_re <= to_real(x_re_in);
- x_im <= to_real(x_im_in);
- y_re <= to_real(y_re_in);
- y_im <= to_real(y_im_in);
- z_re <= to_real(z_re_out);
- z_im <= to_real(z_im_out);
-
-END;
diff --git a/lib/radio/mix/src/tb_mix_real.vhd b/lib/radio/mix/src/tb_mix_real.vhd
deleted file mode 100644
index 8f0ce40..0000000
--- a/lib/radio/mix/src/tb_mix_real.vhd
+++ /dev/null
@@ -1,200 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_mix_cpx
--- Module Name: tb_mix_cpx.vhd
--- Project Name: mix_cpx
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_mix_real IS
- Generic (
- nbits_in : integer := 24;
- nbits_in_frac : integer := 24;
- nbits_out : integer := 24;
- nbits_out_frac : integer := 24;
- nbits_scale_z : integer := 0;
- has_in_reg : boolean := true;
- has_pipe_reg : boolean := true;
- has_out_reg : boolean := true;
- rounding : fixed_round_style_type := fixed_round;
- saturating : fixed_overflow_style_type := fixed_saturate
- );
-END tb_mix_real;
-
-ARCHITECTURE behavior OF tb_mix_real IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT mix_real
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- nbits_scale_z : integer;
- has_in_reg : boolean;
- has_pipe_reg : boolean;
- has_out_reg : boolean;
- rounding : fixed_round_style_type;
- saturating : fixed_overflow_style_type
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_re_din : in sfixed;
- y_re_din : in sfixed;
- y_im_din : in sfixed;
- out_valid : out std_logic;
- z_re_dout : out sfixed;
- z_im_dout : out sfixed
- );
- END COMPONENT;
-
- --Constants
- constant PERIOD : time := 10 ns;
-
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL in_valid : std_logic := '0';
- SIGNAL x_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
- SIGNAL y_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
- SIGNAL y_im_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-
- --Outputs
- SIGNAL z_re_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- SIGNAL z_im_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
- SIGNAL out_valid : std_logic;
-
- SIGNAL fileout_enable : std_logic := '0';
- SIGNAL x_re : real := 0.0;
- SIGNAL y_re : real := 0.0;
- SIGNAL y_im : real := 0.0;
- SIGNAL z_re : real := 0.0;
- SIGNAL z_im : real := 0.0;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: mix_real
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- nbits_scale_z => nbits_scale_z,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- in_valid => in_valid,
- x_re_din => x_re_din,
- y_re_din => y_re_din,
- y_im_din => y_im_din,
- out_valid => out_valid,
- z_re_dout => z_re_dout,
- z_im_dout => z_im_dout
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
- wait until rising_edge(clk);
- x_re_din <= to_sfixed(0.5, x_re_din);
- y_re_din <= to_sfixed(0.5, y_re_din);
- y_im_din <= to_sfixed(0.5, y_im_din);
- in_valid <= '1';
- wait until rising_edge(clk);
- in_valid <= '0';
- wait for 5*PERIOD;
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_din <= to_sfixed(0.125, x_re_din);
- y_re_din <= to_sfixed(0.25, y_re_din);
- y_im_din <= to_sfixed(0.125, y_im_din);
- in_valid <= '1';
- wait until rising_edge(clk);
- in_valid <= '0';
- wait for 5*PERIOD;
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_din <= to_sfixed(0.125, x_re_din);
- y_re_din <= to_sfixed(0.25, y_re_din);
- y_im_din <= to_sfixed(0.125, y_im_din);
- in_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_din <= to_sfixed(0.125, x_re_din);
- y_re_din <= to_sfixed(0.25, y_re_din);
- y_im_din <= to_sfixed(0.125, y_im_din);
- in_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_din <= to_sfixed(0.3, x_re_din);
- y_re_din <= to_sfixed(-0.5, y_re_din);
- y_im_din <= to_sfixed(0.5, y_im_din);
- in_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- x_re_din <= to_sfixed(0.0, x_re_din);
- y_re_din <= to_sfixed(0.0, y_re_din);
- y_im_din <= to_sfixed(-0.7071, y_im_din);
- in_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- in_valid <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- x_re <= to_real(x_re_din);
- y_re <= to_real(y_re_din);
- y_im <= to_real(y_im_din);
- z_re <= to_real(z_re_dout);
- z_im <= to_real(z_im_dout);
-
-END;
diff --git a/lib/radio/mix/src/tb_undc_real.vhd b/lib/radio/mix/src/tb_undc_real.vhd
deleted file mode 100644
index 3fc872b..0000000
--- a/lib/radio/mix/src/tb_undc_real.vhd
+++ /dev/null
@@ -1,161 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_mix_cpx
--- Module Name: tb_mix_cpx.vhd
--- Project Name: mix_cpx
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_undc_real IS
- Generic (
- nbits_data : integer := 24;
- nbits_data_frac : integer := 24;
- nbits_k : integer := 24;
- nbits_k_frac : integer := 24;
- has_in_reg : boolean := true;
- rounding : fixed_round_style_type := fixed_round;
- saturating : fixed_overflow_style_type := fixed_saturate
- );
-END tb_undc_real;
-
-ARCHITECTURE behavior OF tb_undc_real IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT undc_real
- Generic
- (
- nbits_data : integer;
- nbits_data_frac : integer;
- nbits_k : integer;
- nbits_k_frac : integer;
- has_in_reg : boolean;
- rounding : fixed_round_style_type;
- saturating : fixed_overflow_style_type
- );
- Port
- (
- srst : in std_logic;
- clk : in std_logic;
- din_valid : in std_logic;
- din : in sfixed;
- kin_valid : in std_logic;
- kin : in sfixed;
- dout_valid : out std_logic;
- dout : out sfixed;
- dc_out : out sfixed
- );
- END COMPONENT;
-
- --Constants
- constant PERIOD : time := 10 ns;
-
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL din_valid : std_logic := '0';
- SIGNAL kin_valid : std_logic := '0';
- SIGNAL din : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
- SIGNAL kin : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
-
- --Outputs
- SIGNAL dout : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
- SIGNAL dc_out : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
- SIGNAL dout_valid : std_logic;
-
- SIGNAL k : real := 0.0;
- SIGNAL x : real := 0.0;
- SIGNAL y : real := 0.0;
- SIGNAL dc : real := 0.0;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: undc_real
- GENERIC MAP
- (
- nbits_data => nbits_data,
- nbits_data_frac => nbits_data_frac,
- nbits_k => nbits_k,
- nbits_k_frac => nbits_k_frac,
- has_in_reg => has_in_reg,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- din_valid => din_valid,
- din => din,
- kin_valid => kin_valid,
- kin => kin,
- dout_valid => dout_valid,
- dout => dout,
- dc_out => dc_out
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- -- Load k
- ------------------------------------------
- wait for 2*PERIOD;
- wait until rising_edge(clk);
- kin <= to_sfixed(0.0005, kin);
- kin_valid <= '1';
- wait until rising_edge(clk);
- kin_valid <= '1';
- ------------------------------------------
- -- Process
- ------------------------------------------
- wait for 2*PERIOD;
- wait until rising_edge(clk);
- din <= to_sfixed(0.5, din);
- din_valid <= '1';
- wait until rising_edge(clk);
- din_valid <= '1';
- wait for 5*PERIOD;
-
- wait for 200*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- k <= to_real(kin);
- x <= to_real(din);
- y <= to_real(dout);
- dc <= to_real(dc_out);
-
-END;
diff --git a/lib/radio/mix/src/undc_real.vhd b/lib/radio/mix/src/undc_real.vhd
deleted file mode 100644
index e4a3bba..0000000
--- a/lib/radio/mix/src/undc_real.vhd
+++ /dev/null
@@ -1,143 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: mix_cpx - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity undc_real is
-Generic
-(
- nbits_data : integer := 12;
- nbits_data_frac : integer := 12;
- nbits_k : integer := 12;
- nbits_k_frac : integer := 12;
- has_in_reg : boolean := false;
- rounding : fixed_round_style_type := fixed_round;
- saturating : fixed_overflow_style_type := fixed_saturate
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- din_valid : in std_logic;
- din : in sfixed;
- kin_valid : in std_logic;
- kin : in sfixed;
- dout_valid : out std_logic;
- dout : out sfixed;
- dc_out : out sfixed
-);
-end undc_real;
-
-architecture Behavioral of undc_real is
-
-constant nbits_internal : integer := nbits_data + nbits_data;
-constant nbits_internal_frac : integer := nbits_data_frac + nbits_data_frac;
-
-signal x : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
-signal k : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
-signal dc : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
-signal y : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
-signal y1 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
-signal y2 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
-
-begin
-
-dout <= resize(y, sproto(nbits_data, nbits_data_frac), saturating, rounding);
-dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), fixed_wrap, fixed_truncate);
-
-------------------------------------------------------------
- proc_din_reg: process(clk, din_valid, din)
- begin
- if has_in_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- x <= to_sfixed(0, x);
- else
- if din_valid = '1' then
- x <= din;
- end if;
- end if;
- end if;
- else
- x <= din;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_valid_reg: process(clk, din_valid)
- begin
- if has_in_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- dout_valid <= '0';
- else
- dout_valid <= din_valid;
- end if;
- end if;
- else
- dout_valid <= din_valid;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_kin_reg: process(clk, kin_valid, kin)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- k <= to_sfixed(0, k);
- else
- if kin_valid = '1' then
- k <= kin;
- end if;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_pipe_y: process(clk, x, dc)
- begin
- y <= resize(x - dc, y, fixed_wrap, fixed_truncate);
- if rising_edge(clk) then
- if srst = '1' then
- y1 <= to_sfixed(0, y1);
- y2 <= to_sfixed(0, y2);
- dc <= to_sfixed(0, dc);
- else
- y1 <= y;
- y2 <= resize(y1 * k, y2, fixed_wrap, fixed_truncate);
- dc <= resize(y2 + dc, dc, fixed_wrap, fixed_truncate);
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/sim/tb_mix_cordic.fdo b/lib/radio/nco/sim/tb_mix_cordic.fdo
deleted file mode 100644
index 3bd3ff4..0000000
--- a/lib/radio/nco/sim/tb_mix_cordic.fdo
+++ /dev/null
@@ -1,19 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd"
-vcom -explicit -93 "../src/mix_cordic.vhd"
-vcom -explicit -93 "../src/tb_mix_cordic.vhd"
-vsim -t 1ps -lib work tb_mix
-do {tb_mix_cordic.wdo}
-view wave
-view structure
-view signals
-run 400us
diff --git a/lib/radio/nco/sim/tb_mix_cordic.wdo b/lib/radio/nco/sim/tb_mix_cordic.wdo
deleted file mode 100644
index dc928bd..0000000
--- a/lib/radio/nco/sim/tb_mix_cordic.wdo
+++ /dev/null
@@ -1,42 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_mix/clk
-add wave -noupdate -format Logic /tb_mix/srst
-add wave -noupdate -format Logic /tb_mix/clk
-add wave -noupdate -format Logic /tb_mix/srst
-add wave -noupdate -format Logic /tb_mix/mix_nco_rst
-add wave -noupdate -format Logic /tb_mix/mix_nco_en
-add wave -noupdate -format Literal /tb_mix/mix_freq_in
-add wave -noupdate -format Literal /tb_mix/mix_phase_in
-add wave -noupdate -format Literal /tb_mix/mix_din_i
-add wave -noupdate -format Literal /tb_mix/mix_din_q
-add wave -noupdate -format Literal /tb_mix/mix_dout_i
-add wave -noupdate -format Literal /tb_mix/mix_dout_q
-add wave -noupdate -format Logic /tb_mix/mix_dout_vld
-add wave -noupdate -format Logic /tb_mix/mix_din_vld
-add wave -noupdate -format Logic /tb_mix/rfgen_nco_rst
-add wave -noupdate -format Logic /tb_mix/rfgen_nco_en
-add wave -noupdate -format Literal /tb_mix/rfgen_freq_in
-add wave -noupdate -format Literal /tb_mix/rfgen_phase_in
-add wave -noupdate -format Literal /tb_mix/rfgen_din_i
-add wave -noupdate -format Literal /tb_mix/rfgen_din_q
-add wave -noupdate -format Literal /tb_mix/rfgen_dout_i
-add wave -noupdate -format Literal /tb_mix/rfgen_dout_q
-add wave -noupdate -format Logic /tb_mix/rfgen_dout_vld
-add wave -noupdate -format Logic /tb_mix/fileout_enable
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {249834550 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {146645950 ps} {228944950 ps}
diff --git a/lib/radio/nco/sim/tb_mix_results.m b/lib/radio/nco/sim/tb_mix_results.m
deleted file mode 100644
index 5997fea..0000000
--- a/lib/radio/nco/sim/tb_mix_results.m
+++ /dev/null
@@ -1,90 +0,0 @@
-% Read data
-function tb_mix_results()
-fa = 100.0;
-f = TEXTREAD('freq.txt')*1E-6
-R = 128;
-fa_dec = fa/R
-N_pfir = 63;
-
-I_in = TEXTREAD('i_in.txt')';
-I_out = TEXTREAD('i_out.txt')';
-Q_out = TEXTREAD('q_out.txt')';
-
-N= length(I_out)
-N_fft = N;
-N_fft2 = N_fft/2;
-
-fft_y2 = 2/N_fft*abs(fft(I_out(1:N_fft).*hann(N_fft)'));
-
-[i, v] = get_maxpur(fft_y2, fa, f);
-max_spur_freq = (i*fa/N_fft);
-max_spur_value = 20*log10(v);
-
-fft_y3 = 2/N_fft*abs(fft(I_in(1:N_fft).*hann(N_fft)'));
-
-[i, v] = get_maxpur(fft_y3, fa, f);
-max_ditherd_spur_freq = (i*fa/N_fft);
-max_ditherd_spur_value = 20*log10(v);
-
-I_out_dec = cic_filter(R, 1, 3, I_out);
-Q_out_dec = cic_filter(R, 1, 3, Q_out);
-N_dec = length(I_out_dec)-2*N_pfir;
-N_fft_dec = N_dec
-N_fft2_dec = N_fft_dec/2;
-fft_y2_dec = 2/N_fft_dec*abs(fft(I_out_dec(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)'));
-
-pfir_b = sinc(0.1*(-(N_pfir-1)/2:1:(N_pfir)/2));
-pfir_b = pfir_b/sum(pfir_b).*blackman(N_pfir)';
-I_out_dec_pfir = filter(pfir_b, 1, I_out_dec);
-Q_out_dec_pfir = filter(pfir_b, 1, Q_out_dec);
-fft_y2_dec_pfir = 2/N_fft_dec*abs(fft(I_out_dec_pfir(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)'));
-
-% Output
-close all;
-
-plot(fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec(1:N_fft2_dec+1)), '-', fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec_pfir(1:N_fft2_dec+1)), '-'); grid;
-
-figure;
-plot(1:length(I_out_dec_pfir), I_out_dec_pfir, 1:length(Q_out_dec_pfir), Q_out_dec_pfir); grid;
-
-figure;
-freqz(pfir_b, 1, 1000);
-
-figure;
-plot(pfir_b); grid;
-
-
-figure;
-subplot(2,1,1)
-plot(fa/N_fft*(0:N_fft2),20*log10(fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid;
-spur_legend = sprintf('Max. spur %.1fdB at %.3fMHz', max_spur_value, max_spur_freq);
-legend('With dithering', spur_legend);
-legend('No dithering', spur_legend);
-title('Table');
-ylabel('dB');
-xlabel('f/MHz');
-axis([0 fa/2 -140 0]);
-subplot(2,1,2)
-plot(fa/N_fft*(0:N_fft2),20*log10(fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid;
-spur_legend = sprintf('Max. spur %.1fdB at %.3fMHz', max_ditherd_spur_value, max_ditherd_spur_freq);
-legend('With dithering', spur_legend);
-title('Table');
-ylabel('dB');
-xlabel('f/MHz');
-axis([0 fa/2 -140 0]);
-
-plot(1:N, I_out, 1:N, Q_out); grid;
-
-function [max_i, max_v] = get_maxpur(spec, fa, f)
-max_v = 0;
-max_i = 0;
-for ii=1:fix(length(spec)/2+1),
- fi = ii*fa/length(spec);
- dfi = fi - f;
- if abs(dfi) > 0.005*f
- if spec(ii) > max_v
- max_v = spec(ii);
- max_i = ii-1;
- end
- end;
-end;
diff --git a/lib/radio/nco/sim/tb_nco_cordic.fdo b/lib/radio/nco/sim/tb_nco_cordic.fdo
deleted file mode 100644
index 5c5e619..0000000
--- a/lib/radio/nco/sim/tb_nco_cordic.fdo
+++ /dev/null
@@ -1,19 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd"
-vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd"
-vcom -explicit -93 "../src/mix_cordic.vhd"
-vcom -explicit -93 "../src/tb_nco_cordic.vhd"
-vsim -t 1ps -lib work tb_nco
-do {tb_nco_cordic.wdo}
-view wave
-view structure
-view signals
-run 250us
diff --git a/lib/radio/nco/sim/tb_nco_cordic.wdo b/lib/radio/nco/sim/tb_nco_cordic.wdo
deleted file mode 100644
index d41d308..0000000
--- a/lib/radio/nco/sim/tb_nco_cordic.wdo
+++ /dev/null
@@ -1,32 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_nco/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase
-add wave -noupdate -divider Cordic
-add wave -noupdate -format Literal -radix decimal /tb_nco/uut/xin
-add wave -noupdate -format Literal -radix decimal /tb_nco/uut/yin
-add wave -noupdate -format Literal /tb_nco/mix_din_i
-add wave -noupdate -format Literal /tb_nco/mix_din_q
-add wave -noupdate -format Literal /tb_nco/mix_dout_i
-add wave -noupdate -format Literal /tb_nco/mix_dout_q
-add wave -noupdate -format Logic /tb_nco/mix_dout_vld
-add wave -noupdate -format Logic /tb_nco/mix_din_vld
-add wave -noupdate -format Logic /tb_nco/fileout_enable
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {243331511 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {239972168 ps} {248698737 ps}
diff --git a/lib/radio/nco/sim/tb_nco_lut.fdo b/lib/radio/nco/sim/tb_nco_lut.fdo
deleted file mode 100644
index 12f120e..0000000
--- a/lib/radio/nco/sim/tb_nco_lut.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/nco_pkg.vhd"
-vcom -explicit -93 "../src/waverom_dual.vhd"
-vcom -explicit -93 "../src/wavelut.vhd"
-vcom -explicit -93 "../src/nco_lut_dbg.vhd"
-vcom -explicit -93 "../src/tb_nco_lut.vhd"
-vsim -t 1ps -lib work tb_nco
-do {tb_nco_lut.wdo}
-view wave
-view structure
-view signals
-run 250us
diff --git a/lib/radio/nco/sim/tb_nco_lut.wdo b/lib/radio/nco/sim/tb_nco_lut.wdo
deleted file mode 100644
index 0fd0917..0000000
--- a/lib/radio/nco/sim/tb_nco_lut.wdo
+++ /dev/null
@@ -1,46 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_nco/uut/srst
-add wave -noupdate -format Logic /tb_nco/uut/clk
-add wave -noupdate -format Logic /tb_nco/uut/pacc_clr
-add wave -noupdate -format Logic /tb_nco/uut/pacc_inc
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in
-add wave -noupdate -format Logic /tb_nco/uut/freq_load
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in
-add wave -noupdate -format Logic /tb_nco/uut/phase_load
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out
-add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_i
-add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_q
-add wave -noupdate -format Logic /tb_nco/uut/out_valid
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/debug_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_ud
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_d
-add wave -noupdate -format Literal /tb_nco/uut/wave_i_d
-add wave -noupdate -format Literal /tb_nco/uut/wave_q_d
-add wave -noupdate -format Literal /tb_nco/uut/wave_i_ud
-add wave -noupdate -format Literal /tb_nco/uut/wave_q_ud
-add wave -noupdate -format Literal /tb_nco/uut/lfsr
-add wave -noupdate -format Literal /tb_nco/uut/lfsr_out
-add wave -noupdate -format Logic /tb_nco/uut/lut_addr_valid
-add wave -noupdate -format Logic /tb_nco/uut/lfsr_valid
-add wave -noupdate -format Logic /tb_nco/uut/wave_d_valid
-add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {249141632 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {249024188 ps} {250051359 ps}
diff --git a/lib/radio/nco/sim/tb_nco_results.m b/lib/radio/nco/sim/tb_nco_results.m
deleted file mode 100644
index b3fe27a..0000000
--- a/lib/radio/nco/sim/tb_nco_results.m
+++ /dev/null
@@ -1,61 +0,0 @@
-% Read data
-function tb_nco_results(nbins)
-fa = 100.0;
-f = TEXTREAD('freq.txt')*1E-6
-
-I_ud = TEXTREAD('q_ud.txt')';
-I_d = TEXTREAD('q_d.txt')';
-LFSR = TEXTREAD('lfsr.txt');
-
-N= length(I_ud);
-N_fft = min(16384, N);
-N_fft2 = N_fft/2;
-
-fft_y2 = 2/N_fft*abs(fft(I_ud(1:N_fft).*hann(N_fft)'));
-fft_y3 = 2/N_fft*abs(fft(I_d(1:N_fft).*hann(N_fft)'));
-
-[i, v] = get_maxpur(fft_y2, fa, f);
-max_spur_freq = (i*fa/N_fft);
-max_spur_value = 20*log10(v);
-
-[i, v] = get_maxpur(fft_y3, fa, f);
-max_ditherd_spur_freq = (i*fa/N_fft);
-max_ditherd_spur_value = 20*log10(v);
-
-% Output
-close all;
-
-subplot(2,1,1)
-plot(fa/N_fft*(0:N_fft2),20*log10(fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid;
-spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_spur_value, max_spur_freq);
-legend('With dithering', spur_legend);
-legend('No dithering', spur_legend);
-title('Table');
-ylabel('dB');
-xlabel('f/MHz');
-axis([0 fa/2 -140 0]);
-subplot(2,1,2)
-plot(fa/N_fft*(0:N_fft2),20*log10(fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid;
-spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_ditherd_spur_value, max_ditherd_spur_freq);
-legend('With dithering', spur_legend);
-title('Table');
-ylabel('dB');
-xlabel('f/MHz');
-axis([0 fa/2 -140 0]);
-
-figure;
-hist(LFSR, nbins)
-
-function [max_i, max_v] = get_maxpur(spec, fa, f)
-max_v = 0;
-max_i = 0;
-for ii=1:fix(length(spec)/2+1),
- fi = ii*fa/length(spec);
- dfi = fi - f;
- if abs(dfi) > 0.05*f
- if spec(ii) > max_v
- max_v = spec(ii);
- max_i = ii;
- end
- end;
-end;
diff --git a/lib/radio/nco/src/mix_cordic.vhd b/lib/radio/nco/src/mix_cordic.vhd
deleted file mode 100644
index ad002a0..0000000
--- a/lib/radio/nco/src/mix_cordic.vhd
+++ /dev/null
@@ -1,177 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity mix is
-Generic
-(
- nbits_din : integer := 18;
- nbits_din_frac : integer := 16;
- nbits_dout : integer := 18;
- nbits_dout_frac : integer := 16;
- nbits_phase : integer := 16;
- nbits_freq : integer := 16
-);
-Port
-(
- rst : in std_logic;
- clk : in std_logic;
- nco_rst : in std_logic;
- nco_en : in std_logic;
- freq_in : in unsigned(nbits_freq-1 downto 0);
- phase_in : in unsigned(nbits_phase-1 downto 0);
- din_i : in sfixed;
- din_q : in sfixed;
- dout_i : out sfixed;
- dout_q : out sfixed;
- din_vld : in std_logic;
- dout_vld : out std_logic
-);
-end mix;
-
-architecture Behavioral of mix is
-
- COMPONENT cordic_pipe_top
- GENERIC
- (
- cordic_mode : cordic_mode_t;
- z_range : real;
- gain_corr_mode : gain_corr_mode_t;
- nstages : integer;
- nbits_x_in : integer;
- nbits_y_in : integer;
- nbits_z_in : integer;
- nbits_frac_x_in : integer;
- nbits_frac_y_in : integer;
- nbits_frac_z_in : integer;
- nbits_x_out : integer;
- nbits_y_out : integer;
- nbits_z_out : integer;
- nbits_frac_x_out : integer;
- nbits_frac_y_out : integer;
- nbits_frac_z_out : integer
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- vld_in : in std_logic;
- xin : in sfixed;
- yin : in sfixed;
- zin : in sfixed;
- xout : out sfixed;
- yout : out sfixed;
- zout : out sfixed;
- vld_out : out std_logic
- );
- END COMPONENT;
-
--------------------------------------------------------------------------------
- constant nbits_phase_frac : integer := nbits_phase;
-
--------------------------------------------------------------------------------
- signal phase : signed(nbits_phase-1 downto 0);
- signal xin, yin : sfixed(shi(nbits_din, nbits_din_frac) downto slo(nbits_din, nbits_din_frac));
- signal xout, yout : sfixed(shi(nbits_dout, nbits_dout_frac) downto slo(nbits_dout, nbits_dout_frac));
-
- signal dout_valid : std_logic;
-
- signal zin : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
- signal zout : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
-
--------------------------------------------------------------------------------
-begin
-
- dout_i <= xout;
- dout_q <= yout;
- xin <= din_i;
- yin <= din_q;
-
- dout_vld <= dout_valid;
-
-------------------------------------------------------------
- proc_phase_accu: process(clk)
- variable phase_accu : signed(nbits_phase-1 downto 0);
-
- begin
- if rising_edge(clk) then
- if rst = '1' or nco_rst = '1' then
- phase_accu := (others => '0');
- elsif nco_en = '1' then
- phase <= phase_accu + signed(phase_in);
- phase_accu := phase_accu + signed(freq_in);
- end if;
- end if;
- zin <= sfixed(phase);
- end process;
-
-------------------------------------------------------------
- inst_cordic: cordic_pipe_top
- GENERIC MAP
- (
- cordic_mode => cordic_mode_rotate,
- z_range => 1.0,
- gain_corr_mode => gain_mode_disabled,
- nstages => nbits_phase,
- nbits_x_in => nbits_din,
- nbits_frac_x_in => nbits_din_frac,
- nbits_y_in => nbits_din,
- nbits_frac_y_in => nbits_din_frac,
- nbits_z_in => nbits_phase,
- nbits_frac_z_in => nbits_phase_frac,
- nbits_x_out => nbits_dout,
- nbits_frac_x_out => nbits_dout_frac,
- nbits_y_out => nbits_dout,
- nbits_frac_y_out => nbits_dout_frac,
- nbits_z_out => nbits_phase,
- nbits_frac_z_out => nbits_phase_frac
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- vld_in => din_vld,
- xin => xin,
- yin => yin,
- zin => zin,
- xout => xout,
- yout => yout,
- zout => zout,
- vld_out => dout_valid
- );
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/nco.vhd.bak b/lib/radio/nco/src/nco.vhd.bak
deleted file mode 100644
index 657b97a..0000000
--- a/lib/radio/nco/src/nco.vhd.bak
+++ /dev/null
@@ -1,240 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use work.fixed_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity nco is
-Generic
-(
- nbits_wave : integer := 12;
- nbits_phase : integer := 16;
- nbits_lut_depth : integer := 12;
- nbits_dither : integer := 4;
- nbits_lfsr : integer := 12;
- has_pipe_reg : boolean := false;
- has_out_reg : boolean := false
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- pacc_clr : in std_logic;
- pacc_inc : in std_logic;
- freq_in : in unsigned(nbits_phase-1 downto 0);
- freq_load : in std_logic;
- phase_in : in unsigned(nbits_phase-1 downto 0);
- phase_load : in std_logic;
- phase_out : out unsigned(nbits_phase-1 downto 0);
- wave_out_i : out sfixed;
- wave_out_q : out sfixed;
- out_valid : out std_logic
-);
-end nco;
-
-architecture Behavioral of nco is
-
- COMPONENT wavelut
- Generic
- (
- nbits_wave : integer;
- nbits_wave_frac : integer;
- nbits_lut_depth : integer;
- has_out_reg : boolean
- );
- Port
- (
- clk : in std_logic;
- addr_valid : in std_logic;
- addr : in unsigned(nbits_lut_depth-1 downto 0);
- wave_i_out : out sfixed;
- wave_q_out : out sfixed
- );
- END COMPONENT;
-
--------------------------------------------------------------------------------
- constant nbits_wave_frac : integer := nbits_wave;
-
--------------------------------------------------------------------------------
- constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
-
- signal valid : std_logic_vector(3 downto 0);
- signal phase : unsigned(nbits_phase-1 downto 0);
- signal freq_in_r : unsigned(nbits_phase-1 downto 0);
- signal phase_in_r : unsigned(nbits_phase-1 downto 0);
- signal lsfr_sum : unsigned(nbits_phase-1 downto 0);
- signal lut_addr : unsigned(nbits_lut_depth-1 downto 0);
- signal wave_i, wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
- type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
- signal lfsr : lfsr_t;
- signal lfsr_out : unsigned(nbits_dither-1 downto 0);
- signal lut_addr_valid _ std_logic;
-
--------------------------------------------------------------------------------
-begin
-
- wave_out_i <= wave_i;
- wave_out_q <= wave_q;
-
-------------------------------------------------------------
- proc_ctrl: process(srst, clk, pacc_inc, pacc_clr)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- valid <= (others => '0');
- else
- valid <= valid(valid'left-1 downto valid'right) & (pacc_inc or pacc_clr);
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_lfsr: process(srst, clk, lfsr, pacc_inc)
- variable lo : unsigned(nbits_dither downto 0);
- begin
- if rising_edge(clk) then
- if srst = '1' then
- for i in lfsr'range loop
- lfsr(i) <= to_unsigned(1234+2**i, nbits_lfsr);
- end loop;
- elsif pacc_inc ='1' then
- lo := (others => '0');
- for i in lfsr'range loop
- if lfsr(i)(lfsr(i)'left) = '1' then
- lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
- else
- lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
- end if;
- end loop;
- for i in lfsr'range loop
- lo := lo + lfsr(i)(nbits_dither-1 downto 0);
- end loop;
--- lo := lfsr(0)(nbits_dither downto 0);
- lfsr_out <= lo(nbits_dither-1 downto 0);
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
- variable phase_accu : unsigned(nbits_phase-1 downto 0);
-
- begin
- if rising_edge(clk) then
- if srst = '1' then
- phase_accu := (others => '0');
- else
- phase <= phase_accu + phase_in_r;
- if pacc_clr = '1' then
- phase_accu := (others => '0');
- elsif pacc_inc = '1' then
- phase_accu := phase_accu + freq_in_r;
- end if;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- freq_in_reg: process(srst, clk, freq_load, freq_in)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- freq_in_r <= (others => '0');
- elsif freq_load = '1' then
- freq_in_r <= freq_in;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- phase_in_reg: process(srst, clk, phase_load, phase_in)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- phase_in_r <= (others => '0');
- elsif phase_load = '1' then
- phase_in_r <= phase_in;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_pipe_reg: process(clk)
- begin
- if rising_edge(clk) then
- lsfr_sum <= lfsr_out + phase;
- lut_addr <= lsfr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
- end if;
- end process;
-
-------------------------------------------------------------
- proc_out_reg: process(clk, phase)
- begin
- if has_out_reg = true then
- if rising_edge(clk) then
- phase_out <= phase;
- end if;
- else
- phase_out <= phase;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_valid_reg: process(clk, valid)
- begin
- out_valid <= valid(valid'right+1);
- if has_out_reg = true then
- out_valid <= valid(valid'right+2);
- if has_pipe_reg = true then
- out_valid <= valid(valid'right+3);
- end if;
- elsif has_pipe_reg = true then
- out_valid <= valid(valid'right+2);
- end if;
- end process;
-
-------------------------------------------------------------
- inst_wavelut_d: wavelut
- GENERIC MAP
- (
- nbits_wave => nbits_wave,
- nbits_wave_frac => nbits_wave_frac,
- nbits_lut_depth => nbits_lut_depth,
- has_out_reg => has_out_reg
- )
- PORT MAP
- (
- clk => clk,
- addr => lut_addr,
- addr_valid => lut_addr_valid,
- wave_i_out => wave_i,
- wave_q_out => wave_q
- );
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/nco_lut.vhd b/lib/radio/nco/src/nco_lut.vhd
deleted file mode 100644
index 09e1e87..0000000
--- a/lib/radio/nco/src/nco_lut.vhd
+++ /dev/null
@@ -1,229 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity nco is
-Generic
-(
- nbits_wave : integer := 18;
- nbits_phase : integer := 16;
- nbits_lut_depth : integer := 12;
- nbits_dither : integer := 4;
- nbits_lfsr : integer := 12;
- q_phase : phase_relation_t := phase_90deg;
- has_pipe_reg : boolean := false;
- has_out_reg : boolean := false
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- pacc_clr : in std_logic;
- pacc_inc : in std_logic;
- freq_in : in unsigned(nbits_phase-1 downto 0);
- freq_load : in std_logic;
- phase_in : in unsigned(nbits_phase-1 downto 0);
- phase_load : in std_logic;
- phase_out : out unsigned(nbits_phase-1 downto 0);
- wave_out_i : out sfixed;
- wave_out_q : out sfixed;
- out_valid : out std_logic
-);
-end nco;
-
-architecture Behavioral of nco is
-
- COMPONENT wavelut
- Generic
- (
- nbits_wave : integer;
- nbits_wave_frac : integer;
- nbits_lut_depth : integer;
- q_phase : phase_relation_t;
- has_out_reg : boolean
- );
- Port
- (
- clk : in std_logic;
- rst : in std_logic;
- addr_valid : in std_logic;
- addr : in unsigned(nbits_lut_depth-1 downto 0);
- wave_i_out : out sfixed;
- wave_q_out : out sfixed;
- valid_out : out std_logic
- );
- END COMPONENT;
-
--------------------------------------------------------------------------------
- constant nbits_wave_frac : integer := nbits_wave;
-
--------------------------------------------------------------------------------
- constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
-
- signal phase : unsigned(nbits_phase-1 downto 0);
- signal freq_in_r : unsigned(nbits_phase-1 downto 0);
- signal phase_in_r : unsigned(nbits_phase-1 downto 0);
- signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
- signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-
- type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
- signal lfsr : lfsr_t;
- signal lfsr_out : unsigned(nbits_dither-1 downto 0);
- signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic;
-
--------------------------------------------------------------------------------
-begin
-
- wave_out_i <= wave_i_d;
- wave_out_q <= wave_q_d;
- out_valid <= wave_d_valid;
-
-------------------------------------------------------------
- proc_lfsr: process(srst, clk, lfsr, pacc_inc)
- variable lo : unsigned(nbits_dither-1 downto 0);
- begin
- if rising_edge(clk) then
- if srst = '1' then
- lfsr_valid <= '0';
- lfsr_out <= (others => '0');
- for i in lfsr'range loop
- lfsr(i) <= to_unsigned(2**i, nbits_lfsr);
- end loop;
- else
- lfsr_valid <= '0';
- if pacc_inc ='1' then
- lfsr_valid <= '1';
- lo := (others => '0');
- for i in lfsr'range loop
- if lfsr(i)(lfsr(i)'left) = '1' then
- lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
- else
- lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
- end if;
- end loop;
- for i in lfsr'range loop
- lo := lo + lfsr(i)(nbits_dither-1 downto 0);
- end loop;
- -- lo := lfsr(0)(nbits_dither downto 0);
- lfsr_out <= lo(nbits_dither-1 downto 0);
- end if;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_phase_accu: process(clk, phase)
- variable phase_accu : unsigned(nbits_phase-1 downto 0);
-
- begin
- if rising_edge(clk) then
- if srst = '1' then
- phase_accu := (others => '0');
- else
- phase <= phase_accu + phase_in_r;
- if pacc_clr = '1' then
- phase_accu := (others => '0');
- elsif pacc_inc = '1' then
- phase_accu := phase_accu + freq_in_r;
- end if;
- end if;
- end if;
- phase_out <= phase;
- end process;
-
-------------------------------------------------------------
- freq_in_reg: process(srst, clk, freq_load, freq_in)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- freq_in_r <= (others => '0');
- elsif freq_load = '1' then
- freq_in_r <= freq_in;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- phase_in_reg: process(srst, clk, phase_load, phase_in)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- phase_in_r <= (others => '0');
- elsif phase_load = '1' then
- phase_in_r <= phase_in;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_pipe_reg: process(clk)
- variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
- begin
- if rising_edge(clk) then
- lut_addr_valid <= '0';
- if srst = '1' then
- lfsr_sum := (others => '0');
- elsif lfsr_valid = '1' then
- lut_addr_valid <= '1';
- lfsr_sum := lfsr_out + phase;
- end if;
- end if;
- lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
- end process;
-
-------------------------------------------------------------
- inst_wavelut_d: wavelut
- GENERIC MAP
- (
- nbits_wave => nbits_wave,
- nbits_wave_frac => nbits_wave_frac,
- nbits_lut_depth => nbits_lut_depth,
- q_phase => q_phase,
- has_out_reg => has_out_reg
- )
- PORT MAP
- (
- rst => srst,
- clk => clk,
- addr_valid => lut_addr_valid,
- addr => lut_addr_d,
- wave_i_out => wave_i_d,
- wave_q_out => wave_q_d,
- valid_out => wave_d_valid
- );
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/nco_lut_dbg.vhd b/lib/radio/nco/src/nco_lut_dbg.vhd
deleted file mode 100644
index a766e7d..0000000
--- a/lib/radio/nco/src/nco_lut_dbg.vhd
+++ /dev/null
@@ -1,259 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity nco is
-Generic
-(
- nbits_wave : integer := 18;
- nbits_phase : integer := 16;
- nbits_lut_depth : integer := 12;
- nbits_dither : integer := 4;
- nbits_lfsr : integer := 12;
- q_phase : phase_relation_t := phase_90deg;
- has_pipe_reg : boolean := false;
- has_out_reg : boolean := false
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- pacc_clr : in std_logic;
- pacc_inc : in std_logic;
- freq_in : in unsigned(nbits_phase-1 downto 0);
- freq_load : in std_logic;
- phase_in : in unsigned(nbits_phase-1 downto 0);
- phase_load : in std_logic;
- phase_out : out unsigned(nbits_phase-1 downto 0);
- wave_out_i : out sfixed;
- wave_out_q : out sfixed;
- out_valid : out std_logic;
- debug_out : out debug_out_t
-);
-end nco;
-
-architecture Behavioral of nco is
-
- COMPONENT wavelut
- Generic
- (
- nbits_wave : integer;
- nbits_wave_frac : integer;
- nbits_lut_depth : integer;
- q_phase : phase_relation_t;
- has_out_reg : boolean
- );
- Port
- (
- clk : in std_logic;
- rst : in std_logic;
- addr_valid : in std_logic;
- addr : in unsigned(nbits_lut_depth-1 downto 0);
- wave_i_out : out sfixed;
- wave_q_out : out sfixed;
- valid_out : out std_logic
- );
- END COMPONENT;
-
--------------------------------------------------------------------------------
- constant nbits_wave_frac : integer := nbits_wave;
-
--------------------------------------------------------------------------------
- constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
-
- signal phase : unsigned(nbits_phase-1 downto 0);
- signal freq_in_r : unsigned(nbits_phase-1 downto 0);
- signal phase_in_r : unsigned(nbits_phase-1 downto 0);
- signal lut_addr_ud : unsigned(nbits_lut_depth-1 downto 0);
- signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
- signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
- signal wave_i_ud, wave_q_ud : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-
- type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
- signal lfsr : lfsr_t;
- signal lfsr_out : unsigned(nbits_dither-1 downto 0);
- signal lut_addr_valid, lfsr_valid, wave_d_valid, wave_ud_valid : std_logic;
-
--------------------------------------------------------------------------------
-begin
-
- wave_out_i <= wave_i_d;
- wave_out_q <= wave_q_d;
- out_valid <= wave_d_valid;
-
- debug_out.lfsr <= (debug_out.lfsr'left downto (debug_out.lfsr'right+lfsr_out'left+1) => '0') & lfsr_out;
- debug_out.i_d <= to_real(wave_i_d);
- debug_out.q_d <= to_real(wave_q_d);
- debug_out.i_ud <= to_real(wave_i_ud);
- debug_out.q_ud <= to_real(wave_q_ud);
-
-------------------------------------------------------------
- proc_lfsr: process(srst, clk, lfsr, pacc_inc)
- variable lo : unsigned(nbits_dither-1 downto 0);
- begin
- if rising_edge(clk) then
- if srst = '1' then
- lfsr_valid <= '0';
- lfsr_out <= (others => '0');
- for i in lfsr'range loop
- lfsr(i) <= to_unsigned(2**i, nbits_lfsr);
- end loop;
- else
- lfsr_valid <= '0';
- if pacc_inc ='1' then
- lfsr_valid <= '1';
- lo := (others => '0');
- for i in lfsr'range loop
- if lfsr(i)(lfsr(i)'left) = '1' then
- lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
- else
- lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
- end if;
- end loop;
- for i in lfsr'range loop
- lo := lo + lfsr(i)(nbits_dither-1 downto 0);
- end loop;
- -- lo := lfsr(0)(nbits_dither downto 0);
- lfsr_out <= lo(nbits_dither-1 downto 0);
- end if;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
- variable phase_accu : unsigned(nbits_phase-1 downto 0);
-
- begin
- if rising_edge(clk) then
- if srst = '1' then
- phase_accu := (others => '0');
- else
- phase <= phase_accu + phase_in_r;
- if pacc_clr = '1' then
- phase_accu := (others => '0');
- elsif pacc_inc = '1' then
- phase_accu := phase_accu + freq_in_r;
- end if;
- end if;
- end if;
- phase_out <= phase;
- end process;
-
-------------------------------------------------------------
- freq_in_reg: process(srst, clk, freq_load, freq_in)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- freq_in_r <= (others => '0');
- elsif freq_load = '1' then
- freq_in_r <= freq_in;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- phase_in_reg: process(srst, clk, phase_load, phase_in)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- phase_in_r <= (others => '0');
- elsif phase_load = '1' then
- phase_in_r <= phase_in;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_pipe_reg: process(clk)
- variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
- begin
- if rising_edge(clk) then
- lut_addr_valid <= '0';
- if srst = '1' then
- lfsr_sum := (others => '0');
- elsif lfsr_valid = '1' then
- lut_addr_valid <= '1';
- lfsr_sum := lfsr_out + phase;
- end if;
- end if;
- lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
- lut_addr_ud <= phase(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
- end process;
-
-------------------------------------------------------------
- inst_wavelut_ud: wavelut
- GENERIC MAP
- (
- nbits_wave => nbits_wave,
- nbits_wave_frac => nbits_wave_frac,
- nbits_lut_depth => nbits_lut_depth,
- q_phase => q_phase,
- has_out_reg => has_out_reg
- )
- PORT MAP
- (
- rst => srst,
- clk => clk,
- addr_valid => lut_addr_valid,
- addr => lut_addr_ud,
- wave_i_out => wave_i_ud,
- wave_q_out => wave_q_ud,
- valid_out => wave_ud_valid
- );
-
- inst_wavelut_d: wavelut
- GENERIC MAP
- (
- nbits_wave => nbits_wave,
- nbits_wave_frac => nbits_wave_frac,
- nbits_lut_depth => nbits_lut_depth,
- q_phase => q_phase,
- has_out_reg => has_out_reg
- )
- PORT MAP
- (
- rst => srst,
- clk => clk,
- addr_valid => lut_addr_valid,
- addr => lut_addr_d,
- wave_i_out => wave_i_d,
- wave_q_out => wave_q_d,
- valid_out => wave_d_valid
- );
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/nco_pkg.vhd b/lib/radio/nco/src/nco_pkg.vhd
deleted file mode 100644
index d64b23a..0000000
--- a/lib/radio/nco/src/nco_pkg.vhd
+++ /dev/null
@@ -1,95 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use IEEE.MATH_REAL.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
--------------------------------------------------------------------------------
-package nco_pkg is
-
- constant tpd : time := 0 ns;
-
- type real_array_t is array (natural range <>) of real;
- type natural_array_t is array (natural range <>) of natural;
- type phase_relation_t is (phase_90deg, phase_270deg);
-
- type debug_out_t is record
- lfsr : unsigned(31 downto 0);
- i_ud : real;
- q_ud : real;
- i_d : real;
- q_d : real;
- end record;
-
- constant lfsr_poly : natural_array_t(3 to 24) :=
- (
- 12, -- 3
- 24, -- 4
- 58, -- 5
- 114, -- 6
- 210, -- 7
- 500, -- 8
- 1000, -- 9
- 1824, -- 10
- 3712, -- 11
- 7184, -- 12
- 14592, -- 13
- 28674, -- 14
- 59392, -- 15
- 106512, -- 16
- 245760, -- 17
- 466944, -- 18
- 933888, -- 19
- 1654784, -- 20
- 3735552, -- 21
- 7342080, -- 22
- 14745600, -- 23
- 14811138 -- 24
- );
-
- function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t;
- function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t;
-
-end; -- package nco_pkg;
-
--------------------------------------------------------------------------------
-package body nco_pkg is
-
- function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is
- variable tbl : real_array_t (0 to nsamples-1);
- variable phi : real := phi_in;
- variable dphi : real := 2.0*pi*omega;
-
- begin
- for i in 0 to nsamples-1 loop
- tbl(i) := sin(phi);
- phi := phi + dphi;
- end loop;
-
- return tbl;
- end sin_tbl;
-
- -------------------------------------------------------------
- function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is
- variable tbl : real_array_t (0 to nsamples-1);
- variable phi : real := phi_in;
- variable dphi : real := 2.0*pi*omega;
-
- begin
- for i in 0 to nsamples-1 loop
- tbl(i) := cos(phi);
- phi := phi + dphi;
- end loop;
-
- return tbl;
- end cos_tbl;
-
--------------------------------------------------------------------------------
-end; -- package nco_pkg;
diff --git a/lib/radio/nco/src/tb_mix_cordic.vhd b/lib/radio/nco/src/tb_mix_cordic.vhd
deleted file mode 100644
index 335c619..0000000
--- a/lib/radio/nco/src/tb_mix_cordic.vhd
+++ /dev/null
@@ -1,331 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_nco
--- Module Name: tb_nco.vhd
--- Project Name: nco
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_mix IS
- Generic
- (
- nbits_wave_in : integer := 16;
- nbits_wave_out : integer := 18; -- Gain of 2.6 (mix + rfgen)
- nbits_phase : integer := 20;
- nbits_freq : integer := 20
- );
-END tb_mix;
-
-ARCHITECTURE behavior OF tb_mix IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT mix
- GENERIC
- (
- nbits_din : integer;
- nbits_din_frac : integer;
- nbits_dout : integer;
- nbits_dout_frac : integer;
- nbits_phase : integer;
- nbits_freq : integer
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- nco_rst : in std_logic;
- nco_en : in std_logic;
- freq_in : in unsigned(nbits_freq-1 downto 0);
- phase_in : in unsigned(nbits_phase-1 downto 0);
- din_i : in sfixed;
- din_q : in sfixed;
- dout_i : out sfixed;
- dout_q : out sfixed;
- din_vld : in std_logic;
- dout_vld : out std_logic
- );
- END COMPONENT;
-
- --Constants
- constant fa : REAL := 100.0E6;
- constant frf : REAL := 3.333E5;
- constant flo : REAL := 3.333E5;
- constant df : REAL := 10.0E3;
- constant PERIOD : time := 10 ns;
- constant num_steps : integer := 1000000;
-
- constant nbits_wave_in_frac : integer := nbits_wave_in-2;
- constant nbits_wave_out_frac : integer := nbits_wave_out-2;
-
- SIGNAL rfgen_freq_word : integer := integer(frf/fa*2.0**nbits_freq);
- SIGNAL freq_word : integer := integer(flo/fa*2.0**nbits_freq);
- SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_freq);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL mix_nco_rst : std_logic := '0';
- SIGNAL mix_nco_en : std_logic := '0';
- SIGNAL mix_freq_in : unsigned(nbits_freq-1 downto 0) := (others => '0');
- SIGNAL mix_phase_in : unsigned(nbits_phase-1 downto 0) := (others => '0');
-
- --Outputs
- SIGNAL mix_din_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
- SIGNAL mix_din_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
- SIGNAL mix_dout_i : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
- SIGNAL mix_dout_q : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
- SIGNAL mix_dout_vld : std_logic;
- SIGNAL mix_din_vld : std_logic := '0';
-
- SIGNAL rfgen_nco_rst : std_logic := '0';
- SIGNAL rfgen_nco_en : std_logic := '0';
- SIGNAL rfgen_freq_in : unsigned(nbits_freq-1 downto 0) := (others => '0');
- SIGNAL rfgen_phase_in : unsigned(nbits_phase-1 downto 0) := (others => '0');
-
- --Outputs
- signal rfgen_din_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(0.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
- signal rfgen_din_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(1.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
- SIGNAL rfgen_dout_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
- SIGNAL rfgen_dout_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
- SIGNAL rfgen_dout_vld : std_logic;
- SIGNAL fileout_enable : std_logic := '0';
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: mix
- GENERIC MAP
- (
- nbits_din => nbits_wave_in,
- nbits_din_frac => nbits_wave_in_frac,
- nbits_dout => nbits_wave_out,
- nbits_dout_frac => nbits_wave_out_frac,
- nbits_phase => nbits_phase,
- nbits_freq => nbits_freq
- )
- PORT MAP
- (
- rst => srst,
- clk => clk,
- nco_rst => mix_nco_rst,
- nco_en => mix_nco_en,
- freq_in => mix_freq_in,
- phase_in => mix_phase_in,
- din_i => mix_din_i,
- din_q => mix_din_q,
- dout_i => mix_dout_i,
- dout_q => mix_dout_q,
- din_vld => mix_din_vld,
- dout_vld => mix_dout_vld
- );
-
- rfgen1: mix
- GENERIC MAP
- (
- nbits_din => nbits_wave_in,
- nbits_din_frac => nbits_wave_in_frac,
- nbits_dout => nbits_wave_in,
- nbits_dout_frac => nbits_wave_in_frac,
- nbits_phase => nbits_phase,
- nbits_freq => nbits_freq
- )
- PORT MAP
- (
- rst => srst,
- clk => clk,
- nco_rst => rfgen_nco_rst,
- nco_en => rfgen_nco_en,
- freq_in => rfgen_freq_in,
- phase_in => rfgen_phase_in,
- din_i => rfgen_din_i,
- din_q => rfgen_din_q,
- dout_i => rfgen_dout_i,
- dout_q => rfgen_dout_q,
- din_vld => '1',
- dout_vld => rfgen_dout_vld
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- mix_din_i <= rfgen_dout_i;
- mix_din_q <= to_sfixed(0.0, mix_din_q);
- mix_din_vld <= rfgen_dout_vld;
-
- tb : PROCESS
- file RESULT_FREQ: text open write_mode is "freq.txt";
- variable L: line;
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
-
- fprint(RESULT_FREQ, L,"%s\n", REAL'image(flo));
-
- wait for 2*PERIOD;
- -------------------------------------------
- -- 1
- mix_phase_in <= to_unsigned(0,nbits_phase);
- wait until rising_edge(clk);
-
- mix_freq_in <= to_unsigned(1411,nbits_freq);
- wait until rising_edge(clk);
-
- wait for 2*PERIOD;
- mix_nco_en <= '1';
-
- wait for 2*PERIOD;
- wait until rising_edge(clk);
-
- wait for 40*PERIOD;
- -------------------------------------------
- mix_freq_in <= to_unsigned(643,nbits_freq);
- wait until rising_edge(clk);
-
- wait for 40*PERIOD;
- -------------------------------------------
- mix_phase_in <= to_unsigned(800,nbits_phase);
- wait until rising_edge(clk);
-
- wait for 20*PERIOD;
- -------------------------------------------
- mix_phase_in <= to_unsigned(45072,nbits_phase);
- wait until rising_edge(clk);
-
- wait for 20*PERIOD;
- -------------------------------------------
- mix_phase_in <= to_unsigned(20593,nbits_phase);
- wait until rising_edge(clk);
-
- -------------------------------------------
- mix_freq_in <= to_unsigned(freq_word,nbits_freq);
- wait until rising_edge(clk);
-
- wait for 20*PERIOD;
- fileout_enable <= '1';
-
- wait for 200000*PERIOD;
- fileout_enable <= '0';
-
- -------------------------------------------
- -- Sweep
- freq_word <= 100;
- for i in 1 to 200 loop
- wait for 20*PERIOD;
- freq_word <= freq_word + dfreq_word;
-
- mix_freq_in <= to_unsigned(freq_word,nbits_freq);
- wait until rising_edge(clk);
-
- end loop;
-
- mix_nco_en <= '0';
- wait for 20*PERIOD;
- fileout_enable <= '0';
- wait until rising_edge(clk);
- mix_nco_rst <= '1';
- wait until rising_edge(clk);
- mix_nco_rst <= '0';
- wait for 20*PERIOD;
- mix_nco_en <= '1';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- mix_nco_rst <= '1';
- wait until rising_edge(clk);
- mix_nco_rst <= '0';
- wait for 20*PERIOD;
- mix_nco_en <= '0';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- mix_nco_en <= '1';
- wait until rising_edge(clk);
- mix_nco_en <= '0';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- srst <= '1';
- wait until rising_edge(clk);
- srst <= '0';
- mix_freq_in <= to_unsigned(freq_word,nbits_freq);
- wait until rising_edge(clk);
-
- wait for 20*PERIOD;
- mix_nco_en <= '1';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- srst <= '1';
- wait until rising_edge(clk);
- srst <= '0';
- wait for 20*PERIOD;
- mix_nco_en <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
-
- rfgen_ctrl : PROCESS
-
- BEGIN
- wait for 20*PERIOD;
- wait until rising_edge(clk) and srst = '0';
- rfgen_freq_in <= to_unsigned(rfgen_freq_word,nbits_freq);
- wait until rising_edge(clk);
-
- wait for 20*PERIOD;
- rfgen_nco_en <= '1';
-
- wait for 20*PERIOD;
-
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk)
- file RESULT_Ii: text open write_mode is "i_in.txt";
- file RESULT_Qi: text open write_mode is "q_in.txt";
- file RESULT_Io: text open write_mode is "i_out.txt";
- file RESULT_Qo: text open write_mode is "q_out.txt";
- variable L: line;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' then
- if rfgen_dout_vld = '1' then
- fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i)));
- fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q)));
- end if;
- if mix_dout_vld = '1' then
- fprint(RESULT_Io, L,"%s\n", REAL'image(to_real(mix_dout_i)));
- fprint(RESULT_Qo, L,"%s\n", REAL'image(to_real(mix_dout_q)));
- end if;
- end if;
-
- END PROCESS;
-
-
-END;
diff --git a/lib/radio/nco/src/tb_nco_cordic.vhd b/lib/radio/nco/src/tb_nco_cordic.vhd
deleted file mode 100644
index 0bcfd93..0000000
--- a/lib/radio/nco/src/tb_nco_cordic.vhd
+++ /dev/null
@@ -1,265 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_nco
--- Module Name: tb_nco.vhd
--- Project Name: nco
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_nco IS
- Generic
- (
- nbits_wave_in : integer := 16;
- nbits_wave_out : integer := 16;
- nbits_phase : integer := 20;
- nbits_freq : integer := 20
- );
-END tb_nco;
-
-ARCHITECTURE behavior OF tb_nco IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT mix
- GENERIC
- (
- nbits_din : integer;
- nbits_din_frac : integer;
- nbits_dout : integer;
- nbits_dout_frac : integer;
- nbits_phase : integer;
- nbits_freq : integer
- );
- PORT
- (
- rst : in std_logic;
- clk : in std_logic;
- nco_rst : in std_logic;
- nco_en : in std_logic;
- freq_in : in unsigned(nbits_freq-1 downto 0);
- phase_in : in unsigned(nbits_phase-1 downto 0);
- din_i : in sfixed;
- din_q : in sfixed;
- dout_i : out sfixed;
- dout_q : out sfixed;
- din_vld : in std_logic;
- dout_vld : out std_logic
- );
- END COMPONENT;
-
- --Constants
- constant fa : REAL := 100.0E6;
- constant f : REAL := 5.0*fa/24.0;
- constant df : REAL := 10.0E3;
- constant PERIOD : time := 10 ns;
-
- constant nbits_wave_in_frac : integer := nbits_wave_in-2;
- constant nbits_wave_out_frac : integer := nbits_wave_out-2;
-
- SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
- SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL mix_nco_rst : std_logic := '0';
- SIGNAL mix_nco_en : std_logic := '0';
- SIGNAL mix_freq_in : unsigned(nbits_freq-1 downto 0) := (others => '0');
- SIGNAL mix_phase_in : unsigned(nbits_phase-1 downto 0) := (others => '0');
-
- --Outputs
- SIGNAL mix_din_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(0.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
- SIGNAL mix_din_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(1.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
- SIGNAL mix_dout_i : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
- SIGNAL mix_dout_q : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
- SIGNAL mix_dout_vld : std_logic;
- SIGNAL mix_din_vld : std_logic := '1';
-
- SIGNAL fileout_enable : std_logic := '0';
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: mix
- GENERIC MAP
- (
- nbits_din => nbits_wave_in,
- nbits_din_frac => nbits_wave_in_frac,
- nbits_dout => nbits_wave_out,
- nbits_dout_frac => nbits_wave_out_frac,
- nbits_phase => nbits_phase,
- nbits_freq => nbits_freq
- )
- PORT MAP
- (
- rst => srst,
- clk => clk,
- nco_rst => mix_nco_rst,
- nco_en => mix_nco_en,
- freq_in => mix_freq_in,
- phase_in => mix_phase_in,
- din_i => mix_din_i,
- din_q => mix_din_q,
- dout_i => mix_dout_i,
- dout_q => mix_dout_q,
- din_vld => mix_din_vld,
- dout_vld => mix_dout_vld
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- file RESULT_FREQ: text open write_mode is "freq.txt";
- variable L: line;
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
-
- fprint(RESULT_FREQ, L,"%s\n", REAL'image(f));
-
- wait for 2*PERIOD;
- -------------------------------------------
- -- 1
- mix_phase_in <= to_unsigned(0,nbits_phase);
- wait until rising_edge(clk);
-
- mix_freq_in <= to_unsigned(1411,nbits_phase);
- wait until rising_edge(clk);
-
- wait for 2*PERIOD;
- mix_nco_en <= '1';
-
- wait for 2*PERIOD;
- wait until rising_edge(clk);
-
- wait for 40*PERIOD;
- -------------------------------------------
- mix_freq_in <= to_unsigned(643,nbits_phase);
- wait until rising_edge(clk);
-
- wait for 40*PERIOD;
- -------------------------------------------
- mix_phase_in <= to_unsigned(800,nbits_phase);
- wait until rising_edge(clk);
-
- wait for 20*PERIOD;
- -------------------------------------------
- mix_phase_in <= to_unsigned(45072,nbits_phase);
- wait until rising_edge(clk);
-
- wait for 20*PERIOD;
- -------------------------------------------
- mix_phase_in <= to_unsigned(20593,nbits_phase);
- wait until rising_edge(clk);
-
- -------------------------------------------
- mix_freq_in <= to_unsigned(freq_word,nbits_phase);
- wait until rising_edge(clk);
-
- wait for 20*PERIOD;
- fileout_enable <= '1';
-
- wait for 20000*PERIOD;
- fileout_enable <= '0';
-
- -------------------------------------------
- -- Sweep
- freq_word <= 100;
- for i in 1 to 200 loop
- wait for 20*PERIOD;
- freq_word <= freq_word + dfreq_word;
-
- mix_freq_in <= to_unsigned(freq_word,nbits_phase);
- wait until rising_edge(clk);
-
- end loop;
-
- mix_nco_en <= '0';
- wait for 20*PERIOD;
- fileout_enable <= '0';
- wait until rising_edge(clk);
- mix_nco_rst <= '1';
- wait until rising_edge(clk);
- mix_nco_rst <= '0';
- wait for 20*PERIOD;
- mix_nco_en <= '1';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- mix_nco_rst <= '1';
- wait until rising_edge(clk);
- mix_nco_rst <= '0';
- wait for 20*PERIOD;
- mix_nco_en <= '0';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- mix_nco_en <= '1';
- wait until rising_edge(clk);
- mix_nco_en <= '0';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- srst <= '1';
- wait until rising_edge(clk);
- srst <= '0';
- mix_freq_in <= to_unsigned(freq_word,nbits_phase);
- wait until rising_edge(clk);
-
- wait for 20*PERIOD;
- mix_nco_en <= '1';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- srst <= '1';
- wait until rising_edge(clk);
- srst <= '0';
- wait for 20*PERIOD;
- mix_nco_en <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk)
- file RESULT_I: text open write_mode is "i_ud.txt";
- file RESULT_Q: text open write_mode is "q_ud.txt";
- file RESULT_ID: text open write_mode is "i_d.txt";
- file RESULT_QD: text open write_mode is "q_d.txt";
- variable L: line;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' and mix_dout_vld = '1' then
- fprint(RESULT_I, L,"%s\n", REAL'image(to_real(mix_dout_i)));
- fprint(RESULT_Q, L,"%s\n", REAL'image(to_real(mix_dout_q)));
- fprint(RESULT_ID, L,"%s\n", REAL'image(to_real(mix_dout_i)));
- fprint(RESULT_QD, L,"%s\n", REAL'image(to_real(mix_dout_q)));
- end if;
-
- END PROCESS;
-
-
-END;
diff --git a/lib/radio/nco/src/tb_nco_lut.vhd b/lib/radio/nco/src/tb_nco_lut.vhd
deleted file mode 100644
index 53a480d..0000000
--- a/lib/radio/nco/src/tb_nco_lut.vhd
+++ /dev/null
@@ -1,303 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_nco
--- Module Name: tb_nco.vhd
--- Project Name: nco
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_nco IS
- Generic (
- nbits_wave : integer := 18;
- nbits_phase : integer := 16;
- nbits_lut_depth : integer := 12;
- nbits_dither : integer := 4;
- nbits_lfsr : integer := 12;
- q_phase : phase_relation_t := phase_270deg;
- has_pipe_reg : boolean := true;
- has_out_reg : boolean := true
- );
-END tb_nco;
-
-ARCHITECTURE behavior OF tb_nco IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT nco
- GENERIC (
- nbits_wave : integer;
- nbits_phase : integer;
- nbits_lut_depth : integer;
- nbits_dither : integer;
- nbits_lfsr : integer;
- q_phase : phase_relation_t;
- has_pipe_reg : boolean;
- has_out_reg : boolean
- );
- PORT(
- srst : in std_logic;
- clk : in std_logic;
--- ce : in std_logic;
- pacc_clr : in std_logic;
- pacc_inc : in std_logic;
- freq_in : in unsigned(nbits_phase-1 downto 0);
- freq_load : in std_logic;
- phase_in : in unsigned(nbits_phase-1 downto 0);
- phase_load : in std_logic;
- phase_out : out unsigned(nbits_phase-1 downto 0);
- wave_out_i : out sfixed;
- wave_out_q : out sfixed;
- out_valid : out std_logic;
- debug_out : out debug_out_t
- );
- END COMPONENT;
-
- --Constants
- constant fa : REAL := 100.0E6;
- constant f : REAL := 5.0*fa/24.0;
- constant df : REAL := 10.0E3;
- constant PERIOD : time := 10 ns;
- constant nbits_wave_frac : integer := nbits_wave;
-
- SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
- SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
--- SIGNAL ce : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL pacc_clr : std_logic := '0';
- SIGNAL pacc_inc : std_logic := '0';
- SIGNAL phase_load : std_logic := '0';
- SIGNAL freq_load : std_logic := '0';
- SIGNAL freq_in : unsigned(nbits_phase-1 downto 0);
- SIGNAL phase_in : unsigned(nbits_phase-1 downto 0);
-
- --Outputs
- SIGNAL wave_out_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
- SIGNAL wave_out_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
- SIGNAL out_valid : std_logic;
- SIGNAL phase_out : unsigned(nbits_phase-1 downto 0);
- SIGNAL debug_out : debug_out_t;
-
- SIGNAL fileout_enable : std_logic := '0';
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: nco
- GENERIC MAP (
- nbits_wave => nbits_wave,
- nbits_phase => nbits_phase,
- nbits_lut_depth => nbits_lut_depth,
- nbits_dither => nbits_dither,
- nbits_lfsr => nbits_lfsr,
- q_phase => q_phase,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg
- )
- PORT MAP(
- srst => srst,
- clk => clk,
--- ce => ce,
- pacc_clr => pacc_clr,
- pacc_inc => pacc_inc,
- freq_in => freq_in,
- freq_load => freq_load,
- phase_in => phase_in,
- phase_load => phase_load,
- phase_out => phase_out,
- wave_out_i => wave_out_i,
- wave_out_q => wave_out_q,
- out_valid => out_valid,
- debug_out => debug_out
- );
-
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- file RESULT_FREQ: text open write_mode is "freq.txt";
- variable L: line;
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
-
- fprint(RESULT_FREQ, L,"%s\n", REAL'image(f));
-
- wait for 2*PERIOD;
--- ce <= '1';
- -------------------------------------------
- -- 1
- phase_in <= to_unsigned(0,nbits_phase);
- wait until rising_edge(clk);
- phase_load <= '1';
- wait until rising_edge(clk);
- phase_load <= '0';
-
- freq_in <= to_unsigned(1411,nbits_phase);
- wait until rising_edge(clk);
- freq_load <= '1';
- wait until rising_edge(clk);
- freq_load <= '0';
-
- wait for 2*PERIOD;
- pacc_inc <= '1';
-
- wait for 2*PERIOD;
- wait until rising_edge(clk);
-
- wait for 40*PERIOD;
- -------------------------------------------
- freq_in <= to_unsigned(643,nbits_phase);
- wait until rising_edge(clk);
- freq_load <= '1';
- wait until rising_edge(clk);
- freq_load <= '0';
-
- wait for 40*PERIOD;
- -------------------------------------------
- phase_in <= to_unsigned(800,nbits_phase);
- wait until rising_edge(clk);
- phase_load <= '1';
- wait until rising_edge(clk);
- phase_load <= '0';
-
- wait for 20*PERIOD;
- -------------------------------------------
- phase_in <= to_unsigned(45072,nbits_phase);
- wait until rising_edge(clk);
- phase_load <= '1';
- wait until rising_edge(clk);
- phase_load <= '0';
-
- wait for 20*PERIOD;
- -------------------------------------------
- phase_in <= to_unsigned(20593,nbits_phase);
- wait until rising_edge(clk);
- phase_load <= '1';
- wait until rising_edge(clk);
- phase_load <= '0';
-
- -------------------------------------------
- freq_in <= to_unsigned(freq_word,nbits_phase);
- wait until rising_edge(clk);
- freq_load <= '1';
- wait until rising_edge(clk);
- freq_load <= '0';
-
- wait for 20*PERIOD;
- fileout_enable <= '1';
-
- wait for 20000*PERIOD;
- fileout_enable <= '0';
-
- -------------------------------------------
- -- Sweep
- freq_word <= 100;
- for i in 1 to 200 loop
- wait for 20*PERIOD;
- freq_word <= freq_word + dfreq_word;
-
- freq_in <= to_unsigned(freq_word,nbits_phase);
- wait until rising_edge(clk);
- freq_load <= '1';
- wait until rising_edge(clk);
- freq_load <= '0';
-
- end loop;
-
- pacc_inc <= '0';
- wait for 20*PERIOD;
- fileout_enable <= '0';
- wait until rising_edge(clk);
- pacc_clr <= '1';
- wait until rising_edge(clk);
- pacc_clr <= '0';
- wait for 20*PERIOD;
- pacc_inc <= '1';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- pacc_clr <= '1';
- wait until rising_edge(clk);
- pacc_clr <= '0';
- wait for 20*PERIOD;
- pacc_inc <= '0';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- pacc_inc <= '1';
- wait until rising_edge(clk);
- pacc_inc <= '0';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- srst <= '1';
- wait until rising_edge(clk);
- srst <= '0';
- freq_in <= to_unsigned(freq_word,nbits_phase);
- wait until rising_edge(clk);
- freq_load <= '1';
- wait until rising_edge(clk);
- freq_load <= '0';
-
- wait for 20*PERIOD;
- pacc_inc <= '1';
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- srst <= '1';
- wait until rising_edge(clk);
- srst <= '0';
- wait for 20*PERIOD;
- pacc_inc <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk, fileout_enable, out_valid)
- file RESULT_I: text open write_mode is "i_ud.txt";
- file RESULT_Q: text open write_mode is "q_ud.txt";
- file RESULT_ID: text open write_mode is "i_d.txt";
- file RESULT_QD: text open write_mode is "q_d.txt";
- file RESULT_LFSR: text open write_mode is "lfsr.txt";
- variable L: line;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
- fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud));
- fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud));
- fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d));
- fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d));
- fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr)));
- end if;
-
- END PROCESS;
-
-
-END;
diff --git a/lib/radio/nco/src/wavelut.vhd b/lib/radio/nco/src/wavelut.vhd
deleted file mode 100644
index 6f8eaed..0000000
--- a/lib/radio/nco/src/wavelut.vhd
+++ /dev/null
@@ -1,245 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity wavelut is
-Generic
-(
- nbits_wave : integer := 12;
- nbits_wave_frac : integer := 12;
- nbits_lut_depth : integer := 12;
- q_phase : phase_relation_t := phase_90deg;
- has_out_reg : boolean := false
-);
-Port
-(
- rst : in std_logic;
- clk : in std_logic;
- addr_valid : in std_logic;
- addr : in unsigned(nbits_lut_depth-1 downto 0);
- wave_i_out : out sfixed;
- wave_q_out : out sfixed;
- valid_out : out std_logic
-);
-end wavelut;
-
-architecture Behavioral of wavelut is
-
- COMPONENT waverom_dual
- Generic
- (
- nbits_wave : integer;
- nbits_wave_frac : integer;
- nbits_rom_depth : integer
- );
- Port
- (
- clk : in std_logic;
- addr_i : in unsigned(nbits_rom_depth-1 downto 0);
- addr_q : in unsigned(nbits_rom_depth-1 downto 0);
- wave_i_out : out sfixed;
- wave_q_out : out sfixed
- );
- END COMPONENT;
-
--------------------------------------------------------------------------------
-constant nbits_rom_depth : integer := nbits_lut_depth-2;
-
--------------------------------------------------------------------------------
-signal wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-signal wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-signal inv_i : std_logic;
-signal inv_q : std_logic;
-signal addr_i : unsigned(nbits_rom_depth-1 downto 0);
-signal addr_q : unsigned(nbits_rom_depth-1 downto 0);
-signal zero_i : std_logic;
-signal zero_q : std_logic;
-
--------------------------------------------------------------------------------
-begin
-
- inst_waverom_dual: waverom_dual
- GENERIC MAP
- (
- nbits_wave => nbits_wave,
- nbits_wave_frac => nbits_wave_frac,
- nbits_rom_depth => nbits_rom_depth
- )
- PORT MAP
- (
- clk => clk,
- addr_i => addr_i,
- addr_q => addr_q,
- wave_i_out => wave_i,
- wave_q_out => wave_q
- );
-
-------------------------------------------------------------
-proc_valid: process(clk)
- variable v : unsigned(0 to 1);
- begin
- if rising_edge(clk) then
- if rst = '1' then
- v := (others => '0');
- valid_out <= '0';
- else
- valid_out <= v(1);
- v(1) := v(0);
- v(0) := addr_valid;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-proc_tbl_addr_i: process(clk, addr)
- variable index : unsigned(addr'left downto addr'right);
- variable n2 : integer;
- constant N_2 : integer := 2**(nbits_lut_depth-1);
- constant N_4 : integer := 2**(nbits_lut_depth-2);
- begin
- n2 := to_integer(addr(addr'left-1 downto addr'right));
- if n2 > N_4 then
- index := to_unsigned(N_2 - n2, index'length);
- else
- index := to_unsigned(n2, index'length);
- end if;
-
- if rising_edge(clk) then
- if rst = '1' then
- addr_i <= (others => '0');
- zero_i <= '0';
- inv_i <= '0';
- elsif addr_valid = '1' then
- addr_i <= index(addr'left-2 downto addr'right);
- zero_i <= index(addr'left-1);
- inv_i <= addr(addr'left) xor addr(addr'left-1);
- end if;
- end if;
-
- end process;
-
--------------------------------------------------------------------------------
-proc_tbl_addr_q: process(clk, addr)
- variable index : unsigned(addr'left downto addr'right);
- variable n2 : integer;
- constant N_4 : integer := 2**(nbits_lut_depth-2);
-
- begin
- n2 := to_integer(addr(addr'left-1 downto addr'right));
- if n2 > N_4 then
- index := to_unsigned(n2 - N_4, index'length);
- else
- index := to_unsigned(N_4 - n2, index'length);
- end if;
-
- if rising_edge(clk) then
- if rst = '1' then
- addr_q <= (others => '0');
- zero_q <= '0';
- inv_q <= '0';
- elsif addr_valid = '1' then
- addr_q <= index(addr'left-2 downto addr'right);
- zero_q <= index(addr'left-1);
- if q_phase = phase_90deg then
- inv_q <= addr(addr'left);
- elsif q_phase = phase_270deg then
- inv_q <= not addr(addr'left);
- end if;
- end if;
- end if;
-
- end process;
-
-------------------------------------------------------------
-proc_out_i: process(clk, wave_i, inv_i, zero_i)
- variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
- variable z, inv : std_logic;
- begin
-
- w := to_sfixed(0.0, w);
- if z = '0' then
- w := wave_i;
- if inv = '1' then
- w := resize(-wave_i, w, fixed_wrap, fixed_truncate);
- end if;
- end if;
-
- if has_out_reg = true then
- if rising_edge(clk) then
- wave_i_out <= w;
- end if;
- else
- wave_i_out <= w;
- end if;
-
- if rising_edge(clk) then
- z := zero_i;
- inv := inv_i;
- end if;
-
- end process;
-
-------------------------------------------------------------
-proc_out_q: process(clk, wave_q, inv_q, zero_q)
- variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
- variable z, inv : std_logic;
- begin
-
- w := to_sfixed(0.0, w);
- if z = '0' then
- w := wave_q;
- if inv = '1' then
- w := resize(-wave_q, w, fixed_wrap, fixed_truncate);
- end if;
- end if;
-
- if has_out_reg = true then
- if rising_edge(clk) then
- wave_q_out <= w;
- end if;
- else
- wave_q_out <= w;
- end if;
-
- if rising_edge(clk) then
- z := zero_q;
- inv := inv_q;
- end if;
-
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/waverom_dual.vhd b/lib/radio/nco/src/waverom_dual.vhd
deleted file mode 100644
index b39e2a7..0000000
--- a/lib/radio/nco/src/waverom_dual.vhd
+++ /dev/null
@@ -1,92 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: cordic_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity waverom_dual is
-Generic
-(
- nbits_wave : integer := 12;
- nbits_wave_frac : integer := 12;
- nbits_rom_depth : integer := 12
-);
-Port
-(
- clk : in std_logic;
- addr_i : in unsigned(nbits_rom_depth-1 downto 0);
- addr_q : in unsigned(nbits_rom_depth-1 downto 0);
- wave_i_out : out sfixed;
- wave_q_out : out sfixed
-);
-end waverom_dual;
-
-architecture Behavioral of waverom_dual is
-
--------------------------------------------------------------------------------
-constant rom_depth : integer := 2**nbits_rom_depth;
-type wave_mem_t is array (0 to rom_depth-1) of sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-
-constant sfixed_proto : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low) := (others => '0');
-
--------------------------------------------------------------------------------
-function to_wave_mem(wave_real : real_array_t; len : integer; proto : sfixed) return wave_mem_t is
-variable res : wave_mem_t;
-begin
- for i in 0 to len-1 loop
- res(i) := to_sfixed(wave_real(i), proto, fixed_saturate, fixed_round);
- end loop;
-
- return res;
-end to_wave_mem;
-
--------------------------------------------------------------------------------
--- Create ROM
-constant real_wave_tbl : real_array_t(0 to rom_depth-1) := cos_tbl(rom_depth, 0.25/real(rom_depth), 0.0);
-constant wave_tbl : wave_mem_t := to_wave_mem(real_wave_tbl, rom_depth, sfixed_proto);
-
--------------------------------------------------------------------------------
-begin
-
--------------------------------------------------------------------------------
-proc_wave: process(clk)
- begin
- if rising_edge(clk) then
- wave_i_out <= wave_tbl(to_integer(addr_i));
- wave_q_out <= wave_tbl(to_integer(addr_q));
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd
index 55cad91..f4f9fad 100644
--- a/lib/uart/uart_wb.vhd
+++ b/lib/uart/uart_wb.vhd
@@ -1,13 +1,8 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; -- Imports the standard textio package.
ENTITY uart_wb IS
- Generic
- (
- simulate_tx : boolean := false
- );
Port
(
CLK_I : in STD_LOGIC;
@@ -89,8 +84,6 @@ begin
------------------------------------------------------------------
registers_write:
process(CLK_I)
- file output: text open write_mode is "STD_OUTPUT";
- variable L : line;
begin
if rising_edge(CLK_I) then
reg_we_uart_tx <= '0';
@@ -102,17 +95,8 @@ registers_write:
case ADDR_I(5 downto 2) is
when "0000" =>
- if simulate_tx then
- if DAT_I(7 downto 0) /= X"0D" then
- write(L, character'val(to_integer(DAT_I(7 downto 0))));
- end if;
- if DAT_I(7 downto 0) = X"0A" then
- writeline(output, L);
- end if;
- else
- reg_we_uart_tx <= '1';
- reg_uart_tx <= DAT_I(7 downto 0);
- end if;
+ reg_we_uart_tx <= '1';
+ reg_uart_tx <= DAT_I(7 downto 0);
when "0001" =>
rx_int_en <= DAT_I(6);
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.par b/projects/mips_sys/ise101/mips_sys/mips_sys.par
deleted file mode 100644
index 20658d1..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.par
+++ /dev/null
@@ -1,201 +0,0 @@
-Release 10.1.03 par K.39 (nt)
-Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
-
-JUPITER:: Tue Mar 09 13:07:50 2010
-
-par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
-mips_sys.pcf
-
-
-Constraints file: mips_sys.pcf.
-Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE.
- "mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
-The STEPPING level for this design is ES.
-
-Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
-Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
-
-
-Device speed data version: "PRODUCTION 1.68 2008-07-25".
-
-
-
-Device Utilization Summary:
-
- Number of BSCANs 1 out of 4 25%
- Number of BUFGs 12 out of 32 37%
- Number of DCM_ADVs 4 out of 8 50%
- Number of ILOGICs 99 out of 448 22%
- Number of External IOBs 226 out of 448 50%
- Number of LOCed IOBs 226 out of 226 100%
-
- Number of OLOGICs 182 out of 448 40%
- Number of RAMB16s 51 out of 192 26%
- Number of Slices 5907 out of 15360 38%
- Number of SLICEMs 543 out of 7680 7%
-
-
-
-Overall effort level (-ol): High
-Router effort level (-rl): High
-
-Starting initial Timing Analysis. REAL time: 14 secs
-Finished initial Timing Analysis. REAL time: 15 secs
-
-Starting Router
-
-Phase 1: 47928 unrouted; REAL time: 16 secs
-
-Phase 2: 40960 unrouted; REAL time: 17 secs
-
-Phase 3: 15655 unrouted; REAL time: 24 secs
-
-Phase 4: 15655 unrouted; (245197) REAL time: 24 secs
-
-Phase 5: 16281 unrouted; (4341) REAL time: 27 secs
-
-Phase 6: 16339 unrouted; (710) REAL time: 28 secs
-
-Phase 7: 0 unrouted; (9891) REAL time: 53 secs
-
-Updating file: mips_sys.ncd with current fully routed design.
-
-Phase 8: 0 unrouted; (9891) REAL time: 1 mins 4 secs
-
-Phase 9: 0 unrouted; (5549) REAL time: 1 mins 14 secs
-
-Phase 10: 0 unrouted; (5549) REAL time: 1 mins 21 secs
-
-Updating file: mips_sys.ncd with current fully routed design.
-
-Phase 11: 0 unrouted; (5549) REAL time: 2 mins 23 secs
-
-Phase 12: 0 unrouted; (1304) REAL time: 2 mins 58 secs
-
-Phase 13: 0 unrouted; (1304) REAL time: 3 mins 2 secs
-
-Phase 14: 0 unrouted; (1304) REAL time: 3 mins 7 secs
-
-Total REAL time to Router completion: 3 mins 9 secs
-Total CPU time to Router completion: 3 mins 3 secs
-
-Partition Implementation Status
--------------------------------
-
- No Partitions were found in this design.
-
--------------------------------
-
-Generating "PAR" statistics.
-
-**************************
-Generating Clock Report
-**************************
-
-+---------------------+--------------+------+------+------------+-------------+
-| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
-+---------------------+--------------+------+------+------------+-------------+
-| cpu_clk |BUFGCTRL_X0Y12| No | 1610 | 0.400 | 4.025 |
-+---------------------+--------------+------+------+------------+-------------+
-| CLK_O | BUFGCTRL_X0Y2| No | 2256 | 0.541 | 3.930 |
-+---------------------+--------------+------+------+------------+-------------+
-|inst_rom_wb/inst_rom | | | | | |
-| /bs_clk1 | BUFGCTRL_X0Y0| No | 76 | 0.190 | 3.686 |
-+---------------------+--------------+------+------+------------+-------------+
-| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.408 | 3.881 |
-+---------------------+--------------+------+------+------------+-------------+
-| sdram_clk0 |BUFGCTRL_X0Y31| No | 227 | 0.492 | 3.933 |
-+---------------------+--------------+------+------+------------+-------------+
-|sys_ac97_bit_clk_IBU | | | | | |
-| F | BUFGCTRL_X0Y8| No | 251 | 0.428 | 3.823 |
-+---------------------+--------------+------+------+------------+-------------+
-| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 55 | 0.205 | 3.675 |
-+---------------------+--------------+------+------+------------+-------------+
-| sdram_clk270 |BUFGCTRL_X0Y16| No | 68 | 0.158 | 3.932 |
-+---------------------+--------------+------+------+------------+-------------+
-| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 |
-+---------------------+--------------+------+------+------------+-------------+
-|inst_rom_wb/inst_rom | | | | | |
-| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.044 | 3.631 |
-+---------------------+--------------+------+------+------------+-------------+
-
-* Net Skew is the difference between the minimum and maximum routing
-only delays for the net. Note this is different from Clock Skew which
-is reported in TRCE timing report. Clock Skew is the difference between
-the minimum and maximum path delays which includes logic delays.
-
-Timing Score: 1304
-
-WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
- your design.
-
- Review the timing report using Timing Analyzer (In ISE select "Post-Place &
- Route Static Timing Report"). Go to the failing constraint(s) and select
- the "Timing Improvement Wizard" link for suggestions to correct each problem.
-
- Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
- ensure the best options are set in the tools for timing closure.
-
- Use the Xilinx "SmartXplorer" script to try special combinations of
- options known to produce very good results.
-
-INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
- requested value.
-Asterisk (*) preceding a constraint indicates it was not met.
- This may be due to a setup or hold violation.
-
-------------------------------------------------------------------------------------------------------
- Constraint | Check | Worst Case | Best Case | Timing | Timing
- | | Slack | Achievable | Errors | Score
-------------------------------------------------------------------------------------------------------
-* TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | -0.293ns| 10.193ns| 9| 1107
- HIGH 50% | HOLD | 0.365ns| | 0| 0
-------------------------------------------------------------------------------------------------------
-* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.197ns| 10.294ns| 1| 197
- ns HIGH 50% | HOLD | 0.346ns| | 0| 0
-------------------------------------------------------------------------------------------------------
- TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.170ns| 7.330ns| 0| 0
- 7.5 ns HIGH 50% | HOLD | 0.513ns| | 0| 0
-------------------------------------------------------------------------------------------------------
- TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.386ns| 7.614ns| 0| 0
- s HIGH 50% | HOLD | 0.514ns| | 0| 0
-------------------------------------------------------------------------------------------------------
- NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 36.650ns| 6.700ns| 0| 0
- ns HIGH 50% | HOLD | 0.518ns| | 0| 0
-------------------------------------------------------------------------------------------------------
- TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 74.716ns| 5.284ns| 0| 0
- ns HIGH 50% | HOLD | 0.802ns| | 0| 0
-------------------------------------------------------------------------------------------------------
- PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.594ns| N/A| 0
-------------------------------------------------------------------------------------------------------
- PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.138ns| N/A| 0
-------------------------------------------------------------------------------------------------------
-
-
-2 constraints not met.
-INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
- constraint does not cover any paths or that it has no requested value.
-
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-Total REAL time to PAR completion: 3 mins 18 secs
-Total CPU time to PAR completion: 3 mins 9 secs
-
-Peak Memory Usage: 428 MB
-
-Placer: Placement generated during map.
-Routing: Completed - No errors found.
-Timing: Completed - 10 errors found.
-
-Number of error messages: 0
-Number of warning messages: 1
-Number of info messages: 1
-
-Writing design to file mips_sys.ncd
-
-
-
-PAR done!
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/mips_sys.prj
index b8b35cd..c75d8ad 100644
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.prj
+++ b/projects/mips_sys/ise101/mips_sys/mips_sys.prj
@@ -15,6 +15,7 @@ vhdl work "../../../../lib/uart/kcuart_rx.vhd"
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.syr b/projects/mips_sys/ise101/mips_sys/mips_sys.syr
deleted file mode 100644
index 51fc424..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.syr
+++ /dev/null
@@ -1,5227 +0,0 @@
-Release 10.1.03 - xst K.39 (nt)
-Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
---> Parameter TMPDIR set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst/projnav.tmp
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.13 secs
-
---> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.13 secs
-
---> Reading design: mips_sys.prj
-
-TABLE OF CONTENTS
- 1) Synthesis Options Summary
- 2) HDL Compilation
- 3) Design Hierarchy Analysis
- 4) HDL Analysis
- 5) HDL Synthesis
- 5.1) HDL Synthesis Report
- 6) Advanced HDL Synthesis
- 6.1) Advanced HDL Synthesis Report
- 7) Low Level Synthesis
- 8) Partition Report
- 9) Final Report
- 9.1) Device utilization summary
- 9.2) Partition Resource Summary
- 9.3) TIMING REPORT
-
-
-=========================================================================
-* Synthesis Options Summary *
-=========================================================================
----- Source Parameters
-Input File Name : "mips_sys.prj"
-Input Format : mixed
-Ignore Synthesis Constraint File : NO
-
----- Target Parameters
-Output File Name : "mips_sys"
-Output Format : NGC
-Target Device : xc4vsx35-10-ff668
-
----- Source Options
-Top Module Name : mips_sys
-Automatic FSM Extraction : YES
-FSM Encoding Algorithm : Auto
-Safe Implementation : No
-FSM Style : lut
-RAM Extraction : Yes
-RAM Style : Auto
-ROM Extraction : Yes
-Mux Style : Auto
-Decoder Extraction : YES
-Priority Encoder Extraction : YES
-Shift Register Extraction : YES
-Logical Shifter Extraction : YES
-XOR Collapsing : YES
-ROM Style : Auto
-Mux Extraction : YES
-Resource Sharing : NO
-Asynchronous To Synchronous : NO
-Use DSP Block : auto
-Automatic Register Balancing : Yes
-
----- Target Options
-Add IO Buffers : YES
-Global Maximum Fanout : 500
-Add Generic Clock Buffer(BUFG) : 32
-Number of Regional Clock Buffers : 24
-Register Duplication : YES
-Move First FlipFlop Stage : YES
-Move Last FlipFlop Stage : YES
-Slice Packing : YES
-Optimize Instantiated Primitives : NO
-Use Clock Enable : Auto
-Use Synchronous Set : Auto
-Use Synchronous Reset : Auto
-Pack IO Registers into IOBs : true
-Equivalent register Removal : YES
-
----- General Options
-Optimization Goal : Speed
-Optimization Effort : 1
-Power Reduction : NO
-Library Search Order : mips_sys.lso
-Keep Hierarchy : NO
-Netlist Hierarchy : as_optimized
-RTL Output : Yes
-Global Optimization : AllClockNets
-Read Cores : YES
-Write Timing Constraints : NO
-Cross Clock Analysis : NO
-Hierarchy Separator : /
-Bus Delimiter : <>
-Case Specifier : maintain
-Slice Utilization Ratio : 100
-BRAM Utilization Ratio : 100
-DSP48 Utilization Ratio : 100
-Verilog 2001 : YES
-Auto BRAM Packing : NO
-Slice Utilization Ratio Delta : 5
-
-=========================================================================
-
-
-=========================================================================
-* HDL Compilation *
-=========================================================================
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_ctrl_pkg.vhd" in Library work.
-Architecture fifo_ctrl_pkg of Entity fifo_ctrl_pkg is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_types.vhd" in Library work.
-Architecture vga_types of Entity vga_types is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/sdram_config.vhd" in Library work.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/gray_counter.vhd" in Library work.
-Architecture behavioral of Entity gray_counter is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/singleshot.vhd" in Library work.
-Architecture behavioral of Entity singleshot is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd" in Library work.
-Architecture behavioral of Entity vga_sync is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" in Library work.
-Architecture sdram_types of Entity sdram_types is up to date.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd" in Library work.
-Architecture behavioral of Entity fifo_async_ctrl is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/dpram_1w1r.vhd" in Library work.
-Architecture behavioral of Entity dpram_1w1r is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/utils_pkg.vhd" in Library work.
-WARNING:HDLParsers:3534 - "W:/vhdl/lib/misc/utils_pkg.vhd" Line 155. In the function f_correct, not all control paths contain a return statement.
-Architecture utils_pkg of Entity utils_pkg is up to date.
-Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd" in Library work.
-Architecture behavioral of Entity ac_in is up to date.
-Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" in Library work.
-Architecture behavioral of Entity ac_out is up to date.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd" in Library work.
-Architecture behavioral of Entity fifo_sync_ctrl is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" in Library work.
-Architecture rtl of Entity char_rom is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_timing.vhd" in Library work.
-Architecture behavioral of Entity vga_timing is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" in Library work.
-Architecture behaviour of Entity sdram_ctrl is up to date.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_async.vhd" in Library work.
-Architecture behavioral of Entity fifo_async is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" in Library work.
-Architecture behaviour of Entity sdram_cmd is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" in Library work.
-Architecture tech of Entity ddr_phy is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/kcuart_rx.vhd" in Library work.
-Architecture low_level_definition of Entity kcuart_rx is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/bbfifo_16x8.vhd" in Library work.
-Architecture low_level_definition of Entity bbfifo_16x8 is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/kcuart_tx.vhd" in Library work.
-Architecture low_level_definition of Entity kcuart_tx is up to date.
-Compiling vhdl file "W:/vhdl/lib/ps2_port/src/debounce.vhd" in Library work.
-Architecture behavioral of Entity debounce is up to date.
-Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" in Library work.
-Architecture behavioral of Entity ps2_core is up to date.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync.vhd" in Library work.
-Architecture behavioral of Entity fifo_sync is up to date.
-Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd" in Library work.
-Architecture behavioral of Entity ac_io is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_backend.vhd" in Library work.
-Architecture behavioral of Entity vga_backend is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/char_gen.vhd" in Library work.
-Architecture behavioral of Entity char_gen is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" in Library work.
-Architecture rtl of Entity sdram_ctrl_top is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/uart_tx.vhd" in Library work.
-Architecture macro_level_definition of Entity uart_tx is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/uart_rx.vhd" in Library work.
-Architecture macro_level_definition of Entity uart_rx is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/async_types.vhd" in Library work.
-Architecture async_types of Entity async_types is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd" in Library work.
-Architecture data of Entity rom is up to date.
-Compiling vhdl file "W:/vhdl/lib/CPUs/MIPS/src/core/mips_types.vhd" in Library work.
-Architecture mips_types of Entity mips_types is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/async_defs.vhd" in Library work.
-Compiling vhdl file "W:/vhdl/lib/misc/rom_wb.vhd" in Library work.
-Architecture behavior of Entity rom_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/lcd_port.vhd" in Library work.
-Architecture behavioral of Entity lcd_port is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/gpio_wb.vhd" in Library work.
-Architecture behavior of Entity gpio_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/async_port_wb.vhd" in Library work.
-Architecture behavioral of Entity async_port_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/uart_wb.vhd" in Library work.
-Architecture behavior of Entity uart_wb is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd" in Library work.
-Architecture tech of Entity clockgen is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" in Library work.
-Architecture struct of Entity sdram_ctrl_frontend64_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" in Library work.
-Architecture behavioral of Entity vga_frontend64 is up to date.
-Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac97_wb.vhd" in Library work.
-Architecture behavior of Entity ac97_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_wb.vhd" in Library work.
-Architecture behavior of Entity ps2_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd" in Library work.
-Architecture behavioral of Entity ps2_phy is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" in Library work.
-Architecture behavior of Entity mips_sys is up to date.
-
-=========================================================================
-* Design Hierarchy Analysis *
-=========================================================================
-Analyzing hierarchy for entity in library (architecture ) with generics.
- sdram_phaseshift = 0
- sys_freq = 100.000000
- sys_freq_in = 100.000000
- tsvga = (f_pxl_clk => 40000000
- nfps => 60
- ts_h => (ncyc_scan => 800
- ncyc_porch_front => 40
- ncyc_sync_pulse => 128
- ncyc_porch_back => 88
- sync_polarity => '0')
- ts_v => (ncyc_scan => 600
- ncyc_porch_front => 1
- ncyc_sync_pulse => 4
- ncyc_porch_back => 23
- sync_polarity => '0'))
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- f_sysclk = 100.000000
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 25
- async_timespec = (T_leadin => 0.000000
- T_pulse_rd => 120.000000
- T_pulse_wr => 70.000000
- T_leadout => 0.000000
- T_release => 40.000000
- T_pulse_rst => 80.000000
- T_pulse_page_rd => 30.000000
- can_page_rd => true
- nbits_page_rd => 4
- pol_cs => '1'
- pol_oe => '0'
- pol_we => '0'
- pol_be => '0'
- pol_rst => '0')
- byte_sel_width = 1
- data_width = 32
- f_sysclk = 100.000000
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 4
- async_timespec = (T_leadin => 10.000000
- T_pulse_rd => 60.000000
- T_pulse_wr => 60.000000
- T_leadout => 10.000000
- T_release => 80.000000
- T_pulse_rst => 80.000000
- T_pulse_page_rd => 0.000000
- can_page_rd => false
- nbits_page_rd => 0
- pol_cs => '0'
- pol_oe => '0'
- pol_we => '0'
- pol_be => '0'
- pol_rst => '0')
- byte_sel_width = 1
- data_width = 16
- f_sysclk = 100.000000
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- simulate_tx = false
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- clk_in_freq = 100.000000
- sdr0_clk_out_phaseshift = 0
- sdr1_clk_out_phaseshift = 0
- sys_clk_out_freq = 100.000000
- vga_clk_out_freq = 40.000000
-WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored.
-WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored.
-WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored.
-WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored.
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- BL = 2
- f_sdrclk = 100.000000
- f_sysclk = 100.000000
- fifo_depth = 5
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- fifo_almost_empty_thresh = 256
- fifo_almost_full_thresh = 1920
- fifo_depth = 2048
- tsvga = (f_pxl_clk => 40000000
- nfps => 60
- ts_h => (ncyc_scan => 800
- ncyc_porch_front => 40
- ncyc_sync_pulse => 128
- ncyc_porch_back => 88
- sync_polarity => '0')
- ts_v => (ncyc_scan => 600
- ncyc_porch_front => 1
- ncyc_sync_pulse => 4
- ncyc_porch_back => 23
- sync_polarity => '0'))
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- fifo_depth = 8
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- f_sys_clk = 100.000000
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- allow_empty_reads = false
- allow_full_writes = false
- almost_empty_thresh = 4
- almost_full_thresh = 12
- data_width = 30
- do_last_read_update = true
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- allow_empty_reads = false
- allow_full_writes = false
- almost_empty_thresh = 4
- almost_full_thresh = 12
- data_width = 72
- do_last_read_update = true
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- allow_empty_reads = false
- allow_full_writes = false
- almost_empty_thresh = 4
- almost_full_thresh = 12
- data_width = 64
- do_last_read_update = true
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- BL = 2
- f_sdrclk = 100.000000
- f_sysclk = 100.000000
- fifo_depth = 5
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- tsvga = (f_pxl_clk => 40000000
- nfps => 60
- ts_h => (ncyc_scan => 800
- ncyc_porch_front => 40
- ncyc_sync_pulse => 128
- ncyc_porch_back => 88
- sync_polarity => '0')
- ts_v => (ncyc_scan => 600
- ncyc_porch_front => 1
- ncyc_sync_pulse => 4
- ncyc_porch_back => 23
- sync_polarity => '0'))
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 11
- allow_empty_reads = false
- allow_full_writes = false
- almost_empty_thresh = 256
- almost_full_thresh = 1920
- data_width = 64
- do_last_read_update = true
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 9
- allow_empty_reads = false
- allow_full_writes = false
- almost_empty_thresh = 4
- almost_full_thresh = 12
- data_width = 64
- do_last_read_update = true
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 2
- allow_empty_reads = false
- allow_full_writes = false
- almost_empty_thresh = 4
- almost_full_thresh = 12
- data_width = 105
- do_last_read_update = false
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- CHARACTER_SCALE = 1
- CHAR_ROM_DEPTH = 256
- CHAR_ROM_SIZE_X = 8
- CHAR_ROM_SIZE_Y = 16
- CHAR_SPACING_X = 0
- CHAR_SPACING_Y = 0
- MAX_CHAR_PER_LINE = 80
- MAX_LINE_PER_FRAME = 32
- SCREEN_OFFSET_X = 16
- SCREEN_OFFSET_Y = 16
- tsvga = (f_pxl_clk => 40000000
- nfps => 60
- ts_h => (ncyc_scan => 800
- ncyc_porch_front => 40
- ncyc_sync_pulse => 128
- ncyc_porch_back => 88
- sync_polarity => '0')
- ts_v => (ncyc_scan => 600
- ncyc_porch_front => 1
- ncyc_sync_pulse => 4
- ncyc_porch_back => 23
- sync_polarity => '0'))
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 8
- allow_empty_reads = false
- allow_full_writes = false
- almost_empty_thresh = 25
- almost_full_thresh = 230
- data_width = 18
- do_last_read_update = true
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- f_sys_clk = 100.000000
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- ncyc_latency = 8
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- almost_empty_thresh = 4
- almost_full_thresh = 12
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- data_width = 30
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- almost_empty_thresh = 4
- almost_full_thresh = 12
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- data_width = 72
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- data_width = 64
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- BL = 2
- f_sysclk = 100.000000
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- allow_empty_reads = false
- allow_full_writes = false
- almost_empty_thresh = 4
- almost_full_thresh = 12
- data_width = 32
- do_last_read_update = true
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- BL = 2
- f_sdrclk = 100.000000
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- tsvga = (f_pxl_clk => 40000000
- nfps => 60
- ts_h => (ncyc_scan => 800
- ncyc_porch_front => 40
- ncyc_sync_pulse => 128
- ncyc_porch_back => 88
- sync_polarity => '0')
- ts_v => (ncyc_scan => 600
- ncyc_porch_front => 1
- ncyc_sync_pulse => 4
- ncyc_porch_back => 23
- sync_polarity => '0'))
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 11
- almost_empty_thresh = 256
- almost_full_thresh = 1920
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 11
- data_width = 64
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 9
- almost_empty_thresh = 4
- almost_full_thresh = 12
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 9
- data_width = 64
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 2
- almost_empty_thresh = 4
- almost_full_thresh = 12
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 2
- data_width = 105
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 12
- data_width = 8
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 8
- almost_empty_thresh = 25
- almost_full_thresh = 230
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 8
- data_width = 18
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ).
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- init_value = 0
- width = 6
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- almost_empty_thresh = 4
- almost_full_thresh = 12
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- addr_width = 5
- data_width = 32
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- ts = (ncyc_scan => 800
- ncyc_porch_front => 40
- ncyc_sync_pulse => 128
- ncyc_porch_back => 88
- sync_polarity => '0')
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- ts = (ncyc_scan => 600
- ncyc_porch_front => 1
- ncyc_sync_pulse => 4
- ncyc_porch_back => 23
- sync_polarity => '0')
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- init_value = 0
- width = 12
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- mode = 0
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- mode = 1
-
-Analyzing hierarchy for entity in library (architecture ) with generics.
- init_value = 0
- width = 6
-
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 221: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 270: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 318: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 257: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_rx.vhd" line 254: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 133: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 281: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 300: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 354: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 158: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 215: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 226: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 239: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_rx.vhd" line 236: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 333: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-
-=========================================================================
-* HDL Analysis *
-=========================================================================
-Analyzing generic Entity in library (Architecture ).
- sdram_phaseshift = 0
- sys_freq = 100.000000
- sys_freq_in = 100.000000
- tsvga = (f_pxl_clk => 40000000
- nfps => 60
- ts_h => (ncyc_scan => 800
- ncyc_porch_front => 40
- ncyc_sync_pulse => 128
- ncyc_porch_back => 88
- sync_polarity => '0')
- ts_v => (ncyc_scan => 600
- ncyc_porch_front => 1
- ncyc_sync_pulse => 4
- ncyc_porch_back => 23
- sync_polarity => '0'))
- Set user-defined property "KEEP = TRUE" for signal .
- Set user-defined property "KEEP = TRUE" for signal .
- Set user-defined property "KEEP = TRUE" for signal .
- Set user-defined property "KEEP = TRUE" for signal