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This commit was manufactured by cvs2svn to create tag 'MIPS_R12'.

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git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R12@934 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2011-07-24 08:18:46 +00:00
parent faa81b57e9
commit aef784643a
396 changed files with 4562 additions and 83217 deletions
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lib/misc/async_port_wb.vhd
+22 -23
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@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.13 2009-11-04 19:26:53 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -10,10 +10,9 @@ use work.async_types.all;
entity async_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
Port
@@ -57,8 +56,8 @@ architecture Behavioral of async_port_wb is
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal cycle_cnt : natural range 0 to 15;
signal cycle_reload : natural range 0 to 15;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
@@ -73,9 +72,9 @@ architecture Behavioral of async_port_wb is
------------------------------------------------------------------
begin
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
ASSERT async_timespec.ncyc_pulse_rd > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT async_timespec.ncyc_pulse_wr > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (async_timespec.ncyc_pulse_page_rd > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
@@ -111,7 +110,7 @@ architecture Behavioral of async_port_wb is
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cycle_reload <= async_timespec.ncyc_pulse_rst;
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
@@ -139,17 +138,17 @@ architecture Behavioral of async_port_wb is
if en = '1' then
as.cs <= '1';
cc_rst <= '1';
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
if async_timespec.ncyc_leadin = 0 then
sn <= pulse;
if WE_I = '1' then
cycle_reload <= 0;
sn <= leadin; -- always lead-in for writes
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
cycle_reload <= async_timespec.ncyc_pulse_rd-1;
as.rd <= '1';
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
cycle_reload <= async_timespec.ncyc_leadin-1;
sn <= leadin;
end if;
end if;
@@ -163,9 +162,9 @@ architecture Behavioral of async_port_wb is
cc_rst <= '1';
sn <= pulse;
if WE_I_r = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
cycle_reload <= async_timespec.ncyc_pulse_wr-1;
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
cycle_reload <= async_timespec.ncyc_pulse_rd-1;
end if;
end if;
@@ -180,17 +179,17 @@ architecture Behavioral of async_port_wb is
ack <= not WE_I_r;
rdy <= do_page_read;
if en = '1' and do_page_read = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
cycle_reload <= async_timespec.ncyc_pulse_page_rd-1;
sn <= pulse;
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
elsif async_timespec.ncyc_leadout = 0 then
if async_timespec.ncyc_release = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
cycle_reload <= async_timespec.ncyc_release-1;
sn <= release;
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
cycle_reload <= async_timespec.ncyc_leadout-1;
sn <= leadout;
end if;
end if;
@@ -200,10 +199,10 @@ architecture Behavioral of async_port_wb is
as.drive_d <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
if async_timespec.ncyc_release = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
cycle_reload <= async_timespec.ncyc_release-1;
sn <= release;
end if;
end if;