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This commit was manufactured by cvs2svn to create tag 'MIPS_R12'.

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git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R12@934 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2011-07-24 08:18:46 +00:00
parent faa81b57e9
commit aef784643a
396 changed files with 4562 additions and 83217 deletions
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lib/VGA_ctrl/src/align.vhd
-151
View File
@@ -1,151 +0,0 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use work.utils_pkg.all; -- Imports the standard textio package.
ENTITY align IS
Generic
(
data_width : natural := 32;
aggregate_size : natural := 8
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
eb : in STD_LOGIC;
offset : in unsigned(NextExpBaseTwo(data_width/aggregate_size)-1 downto 0);
din_vld : in STD_LOGIC;
din : in unsigned(data_width-1 downto 0);
dout_vld : out STD_LOGIC;
dout : out unsigned(data_width-1 downto 0);
byte_en : out unsigned (data_width/aggregate_size-1 downto 0)
);
END align;
ARCHITECTURE behavior OF align IS
signal shift_dout : unsigned(data_width-1 downto 0);
signal shift_vld : std_logic;
signal reg0_vld : std_logic;
signal reg0 : unsigned(data_width-1 downto 0);
signal reg : unsigned(data_width-1 downto 0);
signal reg_vld : std_logic;
signal reg_be : unsigned(data_width/aggregate_size-1 downto 0);
signal data_vld : std_logic;
type byte_en_rom_t is array (0 to 2*data_width/aggregate_size-1) of unsigned (data_width/aggregate_size-1 downto 0);
function gen_byte_en_rom(N : natural) return byte_en_rom_t is
variable k : integer;
variable result : byte_en_rom_t;
begin
k:=0;
result(k) := (others => '1');
k := k + 1;
for i in 1 to N-1 loop
result(k) := (N-1 downto i => '1') & (i-1 downto 0 => '0');
k := k + 1;
end loop;
result(k) := (others => '1');
k := k + 1;
for i in 1 to N-1 loop
result(k) := (N-1 downto i => '0') & (i-1 downto 0 => '1');
k := k + 1;
end loop;
return result;
end gen_byte_en_rom;
signal byte_en_rom : byte_en_rom_t := gen_byte_en_rom(data_width/aggregate_size);
signal be : unsigned (data_width/aggregate_size-1 downto 0);
--------------------------------------------------------------------------
begin
be <= byte_en_rom(to_integer(not eb & offset));
byte_en <= be;
dout <= reg;
dout_vld <= data_vld;
inst_shifter : entity work.shifter
GENERIC MAP
(
data_width => data_width,
aggregate_size => aggregate_size,
do_pipelined => true
)
PORT MAP
(
rst => rst,
clk => clk,
ce => ce,
sa => to_integer(offset),
din_vld => din_vld,
din => din,
dout_vld => shift_vld,
dout => shift_dout
);
proc_data_valid:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg0_vld <= '0';
data_vld <= '0';
elsif ce = '1' then
reg0_vld <= shift_vld;
data_vld <= shift_vld;
end if;
end if;
end process;
proc_align:
process(clk)
begin
if rising_edge(clk) then
if ce = '1' then
if shift_vld = '1' then
reg0 <= shift_dout;
end if;
end if;
end if;
end process;
proc_blit_dst_combine:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_vld <= '0';
elsif ce = '1' then
if reg0_vld = '1' or shift_vld = '1' then
reg_vld <= '1';
reg <= reg0;
if shift_vld = '1' then
for i in 0 to data_width/aggregate_size-1 loop
if be(i) = '1' then
reg(aggregate_size*(i+1)-1 downto aggregate_size*i) <= shift_dout(aggregate_size*(i+1)-1 downto aggregate_size*i);
end if;
end loop;
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
end behavior;
lib/VGA_ctrl/src/clkgen_virtex4.vhd
+5 -5
View File
@@ -32,8 +32,8 @@ use UNISIM.vcomponents.all;
entity clkgen is
Generic
(
clk_in_freq : real := 100.0;
clk_out_freq : real := 100.0
clk_in_freq_hz : integer := 100E6;
clk_out_freq_hz : integer := 100E6
);
Port
(
@@ -57,10 +57,10 @@ architecture tech of clkgen is
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, clk_out_freq), -- Can be any integer from 2 to 32
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, clk_out_freq_hz), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, clk_out_freq_hz), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
lib/VGA_ctrl/src/shifter.vhd
-133
View File
@@ -1,133 +0,0 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; -- Imports the standard textio package.
use work.utils_pkg.all; -- Imports the standard textio package.
ENTITY shifter IS
Generic
(
data_width : natural := 32;
aggregate_size : natural := 8;
positive_shift_left : boolean := true;
do_pipelined : boolean := true
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
sa : in integer;
din_vld : in STD_LOGIC;
din : in unsigned(data_width-1 downto 0);
dout_vld : out STD_LOGIC;
dout : out unsigned(data_width-1 downto 0)
);
END shifter;
ARCHITECTURE behavior OF shifter IS
constant num_rounds : natural := NextExpBaseTwo(data_width/aggregate_size);
subtype sa_rnd_t is signed(num_rounds-1 downto 0);
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to num_rounds) of word_t;
signal rot_data : word_array_t;
signal sa_rnd : sa_rnd_t;
type sa_rnd_array_t is array (0 to num_rounds) of sa_rnd_t;
signal sa_rnd_pipe : sa_rnd_array_t;
signal dout_vld_pipe : unsigned(0 to num_rounds);
--------------------------------------------------------------------------
function rol_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
variable result : unsigned(x'range);
constant sa : natural := (2**stage_num) * size;
begin
if en = '1' then
result := x(x'left-sa downto 0) & x(x'left downto x'length-sa);
else
result := x;
end if;
return result;
end rol_stage;
function ror_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
variable result : unsigned(x'range);
constant sa : natural := (2**stage_num) * size;
begin
if en = '1' then
result := x(sa-1 downto 0) & x(x'left downto sa);
else
result := x;
end if;
return result;
end ror_stage;
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
gen_non_pipelined:
if do_pipelined = false generate
begin
rot_data(0) <= din;
gen_rotate:
for stage in 0 to num_rounds-1 generate
begin
rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size) when positive_shift_left else
ror_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size);
end generate;
sa_rnd <= to_signed(sa, num_rounds);
dout <= rot_data(num_rounds);
dout_vld <= din_vld;
end generate;
--------------------------------------------------------------------------
gen_pipelined:
if do_pipelined = true generate
begin
rot_data(0) <= din;
sa_rnd_pipe(0) <= to_signed(sa, num_rounds);
dout_vld_pipe(0) <= din_vld;
gen_rotate:
for stage in 0 to num_rounds-1 generate
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
dout_vld_pipe(stage+1) <= '0';
elsif ce = '1' then
dout_vld_pipe(stage+1) <= dout_vld_pipe(stage);
if dout_vld_pipe(stage) = '1' then
sa_rnd_pipe(stage+1) <= sa_rnd_pipe(stage);
if positive_shift_left then
rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
else
rot_data(stage+1) <= ror_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
end if;
end if;
end if;
end if;
end process;
end generate;
dout <= rot_data(num_rounds);
dout_vld <= dout_vld_pipe(num_rounds);
end generate;
--------------------------------------------------------------------------
end behavior;
lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+91 -251
View File
@@ -66,7 +66,6 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
signal rdy : std_logic := '0';
signal read_reg : unsigned(31 downto 0) := (others => '-');
signal const_color : unsigned(31 downto 0) := X"1111_1111";
-- VGA signals
signal vga_clk : std_logic := '1';
@@ -79,11 +78,6 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
signal vga_vsync : std_logic;
signal vga_en : std_logic;
type blit_size_array_t is array (0 to 6) of natural;
constant blit_size_x : blit_size_array_t := (32, 31, 32, 31, 1, 32, 1);
constant blit_size_y : blit_size_array_t := (32, 32, 31, 31, 32, 1, 1);
BEGIN
inst_vga_frontend64 : entity work.vga_frontend64
@@ -92,7 +86,6 @@ inst_vga_frontend64 : entity work.vga_frontend64
fifo_depth => 2048,
fifo_almost_full_thresh => 2048-128,
fifo_almost_empty_thresh => 512,
BLIT_CHUNK_SIZE => 512,
tsvga => tsvga
)
PORT MAP
@@ -213,39 +206,6 @@ VGA_CLK_GEN: process
-- Master
STIMULUS: process
variable result : unsigned(31 downto 0);
procedure reg_write(reg, val : unsigned) is
begin
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
WE_O <= '1';
ADDR_O <= reg;
SDAT_O <= val;
STB_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
end procedure reg_write;
procedure reg_read(reg : unsigned) is
begin
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
WE_O <= '0';
ADDR_O <= reg;
STB_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
result := SDAT_I;
end procedure reg_read;
begin
wait for 6*CLK_PERIOD;
@@ -391,225 +351,105 @@ STIMULUS: process
wait for 60000*CLK_PERIOD;
for i in 0 to blit_size_array_t'length-1 loop
for i in 0 to 99 loop
-------------------------------------------------
-- BLIT aligned => aligned test
-------------------------------------------------
while(true) loop
reg_read(X"0000_0000");
if result(8) = '0' then
exit;
end if;
end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0000");
-- BLIT test
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set src addr first
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src addr last
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000" + to_unsigned(4*(80*4-1), 32);
ADDR_O <= X"0000_0024";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0000");
-- set constant color
reg_write(X"0000_0054", const_color);
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*80, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst addr first
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst addr last
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000" + to_unsigned(4*(80*4-1), 32);
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*80, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(80-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0003";
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= read_reg or X"0000_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait for 100000*CLK_PERIOD;
-------------------------------------------------
-- BLIT unaligned => aligned test
-------------------------------------------------
while(true) loop
reg_read(X"0000_0000");
if result(8) = '0' then
exit;
end if;
end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0004");
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0000");
-- set constant color
reg_write(X"0000_0054", const_color);
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-------------------------------------------------
-- BLIT aligned => unaligned test
-------------------------------------------------
while(true) loop
reg_read(X"0000_0000");
if result(8) = '0' then
exit;
end if;
end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0000");
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0004");
-- set constant color
reg_write(X"0000_0054", const_color);
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-------------------------------------------------
-- BLIT unaligned => unaligned test
-------------------------------------------------
while(true) loop
reg_read(X"0000_0000");
if result(8) = '0' then
exit;
end if;
end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0004");
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0004");
-- set constant color
reg_write(X"0000_0054", const_color);
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-------------------------------------------------
-- BLIT const => aligned test
-------------------------------------------------
while(true) loop
reg_read(X"0000_0000");
if result(8) = '0' then
exit;
end if;
end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0000");
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0000");
-- set constant color
reg_write(X"0000_0054", const_color);
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", result or X"0001_0100");
-------------------------------------------------
-- BLIT const => unaligned test
-------------------------------------------------
while(true) loop
reg_read(X"0000_0000");
if result(8) = '0' then
exit;
end if;
end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0000");
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0004");
-- set constant color
reg_write(X"0000_0054", const_color);
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", result or X"0001_0100");
wait for 60000*CLK_PERIOD;
const_color <= const_color + X"1111_1111";
end loop;
wait;
lib/VGA_ctrl/src/vga_frontend64.vhd
+120 -348
View File
@@ -30,7 +30,6 @@ entity vga_frontend64 is
fifo_depth : integer := 2048;
fifo_almost_full_thresh : natural := 2000;
fifo_almost_empty_thresh : natural := 48;
BLIT_CHUNK_SIZE : natural := 512;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
Port
@@ -155,11 +154,10 @@ architecture Behavioral of vga_frontend64 is
signal vga_scan_dma_en2 : std_logic;
signal request_cnt_rst : std_logic;
signal request_en : std_logic;
signal bus_read_en : std_logic;
signal read_bus_en : std_logic;
signal request_cnt : unsigned(28 downto 0);
signal read_cnt : unsigned(28 downto 0);
signal bus_read_fin : std_logic;
signal bus_cycle_en : std_logic;
signal CYC_O_scan : std_logic;
signal STB_O_scan : std_logic;
@@ -168,34 +166,18 @@ architecture Behavioral of vga_frontend64 is
signal front : unsigned(31 downto 0);
signal back : unsigned(31 downto 0);
-- Blitter vars
constant BLIT_CHUNK_SIZE : natural := 512;
signal blit_chunk_cnt : natural range 0 to BLIT_CHUNK_SIZE-1;
signal blit_chunk_cnt_rst : std_logic;
signal blit_chunk_cnt_en : std_logic;
-- Source Blitter FIFO signals
signal blitfifo_src_full : std_logic;
signal blitfifo_src_empty : std_logic;
signal blitfifo_src_re : std_logic;
signal blitfifo_src_we : std_logic;
signal blitfifo_src_out : unsigned(63 downto 0);
signal blitfifo_src_in : unsigned(63 downto 0);
-- Blitter FIFO signals
signal blitfifo_full : std_logic;
signal blitfifo_empty : std_logic;
signal blitfifo_color_re : std_logic;
signal blitfifo_color_we : std_logic;
signal blitfifo_color_out : unsigned(63 downto 0);
signal blitfifo_color_in : unsigned(63 downto 0);
-- Source alignment register
signal blit_src_addr : unsigned(2 downto 0);
signal blit_src_reg_vld : std_logic;
signal blit_src_reg : unsigned(63 downto 0);
signal blit_src_rdy : std_logic;
signal blit_src_we : std_logic;
signal blit_src_re : std_logic;
signal blit_src_unaligned : std_logic;
signal blit_src_do_extra : std_logic;
signal blit_src_do_extra2 : std_logic;
signal blit_src_row_cnt : unsigned(31 downto 0);
signal blit_src_first : std_logic;
signal blit_src_last : std_logic;
signal blit_src_cnt_x : unsigned(31 downto 0);
signal blit_src_cnt_y : unsigned(31 downto 0);
signal blit_src_off_y : unsigned(31 downto 0);
@@ -205,72 +187,42 @@ architecture Behavioral of vga_frontend64 is
signal STB_O_blit_src : std_logic;
signal ADDR_O_blit_src : unsigned(31 downto 0);
-- Destination alignment register
signal blit_dst_reg : unsigned(63 downto 0);
signal blit_dst_reg_vld : std_logic;
signal blit_dst_unaligned : std_logic;
signal blit_dst_row_cnt : unsigned(31 downto 0);
signal blit_dst_first : std_logic;
signal blit_dst_last : std_logic;
signal blit_dst_do_extra : std_logic;
signal blit_dst_reg_be : unsigned(7 downto 0);
signal blit_dst_rdy : std_logic;
signal blit_dst_we : std_logic;
signal blit_dst_re : std_logic;
signal blit_dst_be : unsigned(7 downto 0);
signal blit_dst_vld : std_logic;
signal blit_dst_cnt_x : unsigned(31 downto 0);
signal blit_dst_cnt_y : unsigned(31 downto 0);
signal blit_dst_off_y : unsigned(31 downto 0);
signal blit_dst_offset : unsigned(31 downto 0);
signal blit_dst_finish : std_logic;
signal blit_const_color : unsigned(31 downto 0);
signal blit_const_color_en : std_logic;
signal blit_const_color_vld : std_logic;
signal CYC_O_blit_dst : std_logic;
signal STB_O_blit_dst : std_logic;
signal ADDR_O_blit_dst : unsigned(31 downto 0);
signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
-- Bus output FIFO
signal busout_fifo_din : unsigned(104 downto 0);
signal busout_fifo_dout : unsigned(104 downto 0);
signal busout_fifo_re : std_logic;
signal busout_fifo_we : std_logic;
signal busout_fifo_full : std_logic;
signal busout_fifo_empty : std_logic;
signal busout_fifo_rdy : std_logic;
-- Bus FIFO
signal bus_fifo_din : unsigned(104 downto 0);
signal bus_fifo_dout : unsigned(104 downto 0);
signal bus_fifo_re : std_logic;
signal bus_fifo_we : std_logic;
signal bus_fifo_full : std_logic;
signal bus_fifo_empty : std_logic;
signal bus_rdy : std_logic;
alias busout_fifo_addr_in is busout_fifo_din(31 downto 0);
alias busout_fifo_data_in is busout_fifo_din(95 downto 32);
alias busout_fifo_sel_in is busout_fifo_din(103 downto 96);
alias busout_fifo_we_in is busout_fifo_din(104);
alias bus_fifo_addr_in is bus_fifo_din(31 downto 0);
alias bus_fifo_data_in is bus_fifo_din(95 downto 32);
alias bus_fifo_sel_in is bus_fifo_din(103 downto 96);
alias bus_fifo_we_in is bus_fifo_din(104);
alias busout_fifo_addr_out is busout_fifo_dout(31 downto 0);
alias busout_fifo_data_out is busout_fifo_dout(95 downto 32);
alias busout_fifo_sel_out is busout_fifo_dout(103 downto 96);
alias busout_fifo_we_out is busout_fifo_dout(104);
alias bus_fifo_addr_out is bus_fifo_dout(31 downto 0);
alias bus_fifo_data_out is bus_fifo_dout(95 downto 32);
alias bus_fifo_sel_out is bus_fifo_dout(103 downto 96);
alias bus_fifo_we_out is bus_fifo_dout(104);
-- Bus input FIFO
signal busin_fifo_din : unsigned(63 downto 0);
signal busin_fifo_dout : unsigned(63 downto 0);
signal busin_fifo_re : std_logic;
signal busin_fifo_we : std_logic;
signal busin_fifo_full : std_logic;
signal busin_fifo_empty : std_logic;
signal busin_fifo_rdy : std_logic;
signal busin_fifo_dout_vld : std_logic;
type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_prime_pipe, blit_dst_bus_request, bus_fin);
type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_bus_request, blit_dst_bus_fin);
signal s, sn : vm_state_t;
--------------------------------------------------------------------------
begin
proc_synced_vga_scan_en:
process(CLK_I)
begin
@@ -305,7 +257,7 @@ proc_blit_request_flags:
blit_request <= '0';
elsif blit_request_set = '1' then
blit_request <= '1';
elsif blit_dst_finish = '1' then
elsif blit_dst_finish = '1' and blitfifo_empty = '1' then
blit_request <= '0';
end if;
end if;
@@ -317,7 +269,7 @@ proc_blit_complete_flag:
if rising_edge(CLK_I) then
if RST_I = '1' or blit_request_set = '1' or blit_complete_ack = '1' then
blit_complete <= '0';
elsif blit_dst_finish = '1' and blit_request = '1' then
elsif blit_dst_finish = '1' and blitfifo_empty = '1' and blit_request = '1' then
blit_complete <= '1';
end if;
end if;
@@ -367,12 +319,12 @@ inst_vga_backend : entity work.vga_backend
);
SRDY_O <= CYC_I; -- and cg_rdy;
MRDY_O <= busin_fifo_rdy; --not fifo_full;
STB_O <= not busout_fifo_empty;
ADDR_O <= busout_fifo_addr_out;
MDAT_O <= busout_fifo_data_out;
SEL_O <= busout_fifo_sel_out;
WE_O <= busout_fifo_we_out;
MRDY_O <= not fifo_full;
STB_O <= not bus_fifo_empty;
ADDR_O <= bus_fifo_addr_out;
MDAT_O <= bus_fifo_data_out;
SEL_O <= bus_fifo_sel_out;
WE_O <= bus_fifo_we_out;
odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length);
ctrl_scan_en <= '1';
@@ -407,71 +359,67 @@ inst_linefifo: entity work.fifo_async
);
fifo_color_in <= busin_fifo_dout;
fifo_color_in <= MDAT_I;
fifo_color_re <= stat_scan and odd_pixel(0);
fifo_color_we <= busin_fifo_dout_vld and CYC_O_scan; -- TODO:
fifo_color_we <= ACK_I and read_bus_en and CYC_O_scan; -- TODO:
-- Bus input FIFO
inst_busin_fifo: entity work.fifo_sync
inst_blitfifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE),
data_width => 64
)
PORT MAP
(
rst => blit_reset,
clk => CLK_I,
we => blitfifo_color_we,
re => blitfifo_color_re,
data_w => blitfifo_color_in,
data_r => blitfifo_color_out,
fifo_full => blitfifo_full,
fifo_empty => blitfifo_empty,
fifo_afull => open,
fifo_aempty => open
);
blitfifo_color_in <= MDAT_I;
blitfifo_color_re <= STB_O_blit_dst and bus_rdy;
blitfifo_color_we <= ACK_I and read_bus_en and CYC_O_blit_src; -- TODO:
-- Instantiate synchronous FIFO
inst_bus_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 2,
data_width => busin_fifo_din'length,
do_last_read_update => true
addr_width => 2,
data_width => 105
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => busin_fifo_we,
re => busin_fifo_re,
fifo_full => busin_fifo_full,
fifo_empty => busin_fifo_empty,
we => bus_fifo_we,
re => bus_fifo_re,
fifo_full => bus_fifo_full,
fifo_empty => bus_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => busin_fifo_din,
data_r => busin_fifo_dout
data_w => bus_fifo_din,
data_r => bus_fifo_dout
);
busin_fifo_rdy <= not busin_fifo_full;
busin_fifo_din <= MDAT_I;
busin_fifo_we <= ACK_I and bus_cycle_en and bus_read_en;
busin_fifo_dout_vld <= not busin_fifo_empty;
busin_fifo_re <= not fifo_full when CYC_O_scan = '1' else blit_src_we;
-- Bus output FIFO
inst_busout_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 2,
data_width => busout_fifo_din'length,
do_last_read_update => false
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => busout_fifo_we,
re => busout_fifo_re,
fifo_full => busout_fifo_full,
fifo_empty => busout_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => busout_fifo_din,
data_r => busout_fifo_dout
);
busout_fifo_rdy <= not busout_fifo_full;
busout_fifo_re <= not busout_fifo_empty and SRDY_I;
busout_fifo_we <= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst);
busout_fifo_data_in <= blit_dst_reg;
busout_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
bus_rdy <= not bus_fifo_full;
bus_fifo_re <= not bus_fifo_empty and SRDY_I;
bus_fifo_we <= STB_O_scan or STB_O_blit_src or STB_O_blit_dst;
bus_fifo_data_in <= blitfifo_color_out;
bus_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
ADDR_O_scan;
busout_fifo_sel_in <= blit_dst_be when CYC_O_blit_dst = '1' else (others => '1');
busout_fifo_we_in <= CYC_O_blit_dst;
CYC_O <= bus_cycle_en;
bus_fifo_sel_in <= (others => '1');
bus_fifo_we_in <= CYC_O_blit_dst;
------------------------------------------------------------------------------------
-- VGA master FSM
CYC_O <= CYC_O_scan or CYC_O_blit_src or CYC_O_blit_dst;
vga_master_next:
process(CLK_I)
begin
@@ -485,7 +433,7 @@ vga_master_next:
end process;
vga_master:
process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_rdy, busout_fifo_empty, blit_chunk_cnt, blitfifo_src_empty, blit_dst_vld, blit_src_finish, blit_const_color_en)
process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, bus_read_fin, bus_fifo_empty, blit_chunk_cnt, blitfifo_empty, blit_src_finish)
begin
CYC_O_scan <= '0';
@@ -496,13 +444,9 @@ vga_master:
STB_O_blit_dst <= '0';
request_cnt_rst <= '0';
request_en <= '0';
bus_read_en <= '0';
bus_cycle_en <= '0';
blit_chunk_cnt_rst <= '0';
blit_chunk_cnt_en <= '0';
read_bus_en <= '0';
sn <= s;
case s is
when init =>
if stat_vga_rdy = '1' then
@@ -511,75 +455,59 @@ vga_master:
when rdy =>
request_cnt_rst <= '1';
blit_chunk_cnt_rst <= '1';
if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then
sn <= scan_bus_request;
elsif blit_request = '1' then -- ToDo: richtig prüfen anhand eines states wer dran ist. Nicht auf FIFO state prüfen
if blitfifo_src_empty = '0' or blit_dst_vld = '1' then
sn <= blit_dst_prime_pipe;
elsif blit_const_color_en = '0' then
elsif blit_request = '1' then
if blitfifo_empty = '1' then
sn <= blit_src_bus_request;
else
sn <= blit_dst_bus_request;
end if;
end if;
when scan_bus_request =>
bus_cycle_en <= '1';
CYC_O_scan <= '1';
STB_O_scan <= '1';
request_en <= '1';
bus_read_en <= '1';
read_bus_en <= '1';
if fifo_almost_full = '1' then
sn <= scan_bus_read;
end if;
when scan_bus_read =>
bus_cycle_en <= '1';
CYC_O_scan <= '1';
bus_read_en <= '1';
CYC_O_scan <= '1';
read_bus_en <= '1';
if bus_read_fin = '1' then
sn <= rdy;
end if;
when blit_src_bus_request =>
bus_cycle_en <= '1';
CYC_O_blit_src <= '1';
STB_O_blit_src <= '1';
request_en <= '1';
bus_read_en <= '1';
blit_chunk_cnt_en <= '1';
read_bus_en <= '1';
if blit_chunk_cnt = 0 or blit_src_finish = '1' then
sn <= blit_src_bus_read;
end if;
when blit_src_bus_read =>
bus_cycle_en <= '1';
CYC_O_blit_src <= '1';
bus_read_en <= '1';
read_bus_en <= '1';
if bus_read_fin = '1' then
sn <= rdy;
end if;
when blit_dst_prime_pipe =>
bus_cycle_en <= '1';
CYC_O_blit_dst <= '1';
STB_O_blit_dst <= blit_dst_vld;
blit_chunk_cnt_en <= blit_dst_vld;
if blit_dst_vld = '1' then
sn <= blit_dst_bus_request;
end if;
when blit_dst_bus_request =>
bus_cycle_en <= '1';
CYC_O_blit_dst <= '1';
STB_O_blit_dst <= blit_dst_vld;
blit_chunk_cnt_en <= blit_dst_vld;
if blit_chunk_cnt = 0 or blit_dst_vld = '0' then
sn <= bus_fin;
STB_O_blit_dst <= '1';
if blitfifo_empty = '1' then
STB_O_blit_dst <= '0';
sn <= blit_dst_bus_fin;
end if;
when bus_fin =>
bus_cycle_en <= '1';
if busout_fifo_empty = '1' then
when blit_dst_bus_fin =>
CYC_O_blit_dst <= '1';
if bus_fifo_empty = '1' then
sn <= rdy;
end if;
@@ -589,14 +517,13 @@ vga_master:
end case;
end process;
------------------------------------------------------------------------------------
proc_bus_request_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
request_cnt <= (others => '0');
elsif request_en = '1' and busout_fifo_rdy = '1' then
elsif request_en = '1' and bus_rdy = '1' then
request_cnt <= request_cnt + 1;
end if;
end if;
@@ -608,7 +535,7 @@ proc_bus_read_counter:
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
read_cnt <= (others => '0');
elsif busin_fifo_dout_vld = '1' then
elsif read_bus_en = '1' and ACK_I = '1' then
read_cnt <= read_cnt + 1;
end if;
end if;
@@ -629,17 +556,16 @@ proc_blit_chunk_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if blit_chunk_cnt_rst = '1' then
blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
elsif blit_chunk_cnt_en = '1' and busout_fifo_rdy = '1' then
if blit_chunk_cnt /= 0 then
if STB_O_blit_src = '1' then
if blit_chunk_cnt /= 0 and bus_rdy = '1' then
blit_chunk_cnt <= blit_chunk_cnt - 1;
end if;
else
blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
end if;
end if;
end process;
---------------------------------------------------------------------------------
blit_reset <= RST_I or (blit_request_set and not blit_request);
ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
@@ -652,7 +578,7 @@ proc_scan_addr:
if vga_scan_dma_en2 = '0' then
pixel_cnt <= 0;
front <= host_fb_front;
elsif STB_O_scan = '1' and busout_fifo_rdy = '1' then
elsif STB_O_scan = '1' and bus_rdy = '1' then
if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
pixel_cnt <= pixel_cnt + 1;
else
@@ -666,93 +592,7 @@ proc_scan_addr:
end if;
end process;
---------------------------------------------------------------------------------
inst_align_src : entity work.align
GENERIC MAP
(
data_width => 64,
aggregate_size => 8
)
PORT MAP
(
rst => blit_reset,
clk => CLK_I,
ce => blit_src_re,
eb => '1',
offset => blit_src_addr,
din_vld => blit_src_we,
din => busin_fifo_dout,
dout_vld => blit_src_reg_vld,
dout => blit_src_reg,
byte_en => open
);
blit_src_we <= busin_fifo_dout_vld and CYC_O_blit_src; -- TODO:
blit_src_re <= not blitfifo_src_full; -- TODO:
proc_blit_src_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if blit_reset = '1' then
blit_src_row_cnt <= (others => '0');
blit_src_unaligned <= '0';
blit_src_first <= '0';
blit_src_last <= '0';
blit_src_do_extra2 <= '0';
if blit_src_addr (2 downto 0) /= "000" then
blit_src_unaligned <= not blit_const_color_en;
blit_src_first <= not blit_const_color_en;
blit_src_do_extra2 <= not blit_const_color_en;
end if;
elsif blit_src_re = '1' then
if blit_src_reg_vld = '1' then
blit_src_first <= '0';
if blit_src_row_cnt /= blit_nx then
blit_src_row_cnt <= blit_src_row_cnt + 1;
elsif blit_src_do_extra2 = '1' then
blit_src_do_extra2 <= '0';
else
if blit_src_unaligned = '1' then
blit_src_do_extra2 <= '1';
end if;
blit_src_row_cnt <= (others => '0');
blit_src_first <= blit_src_unaligned;
end if;
end if;
end if;
end if;
end process;
inst_blitfifo_src: entity work.fifo_sync
GENERIC MAP
(
addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE),
data_width => blitfifo_src_in'length
)
PORT MAP
(
rst => blit_reset,
clk => CLK_I,
we => blitfifo_src_we,
re => blitfifo_src_re,
data_w => blitfifo_src_in,
data_r => blitfifo_src_out,
fifo_full => blitfifo_src_full,
fifo_empty => blitfifo_src_empty,
fifo_afull => open,
fifo_aempty => open
);
blitfifo_src_we <= (blit_src_reg_vld and not blit_src_first) when blit_const_color_en = '0' else (blit_request and not blit_src_finish);
blitfifo_src_in <= blit_src_reg when blit_const_color_en = '0' else (blit_const_color & blit_const_color);
blitfifo_src_re <= blit_dst_re;
---------------------------------------------------------------------------------
ADDR_O_blit_src <= blit_addr_src_0(31 downto 3) & "000" + blit_src_offset;
blit_src_addr <= blit_addr_src_0(2 downto 0);
ADDR_O_blit_src <= blit_addr_src_0 + blit_src_offset;
proc_blit_addr_src:
process(CLK_I)
@@ -764,100 +604,43 @@ proc_blit_addr_src:
blit_src_offset <= (others => '0');
blit_src_off_y <= blit_dimx_src_0;
blit_src_finish <= '0';
blit_src_do_extra <= '0';
if blit_src_addr (2 downto 0) /= "000" then
blit_src_do_extra <= not blit_const_color_en;
end if;
elsif blit_src_finish = '0' and ((STB_O_blit_src = '1' and busout_fifo_rdy = '1') or (blit_const_color_en = '1' and blitfifo_src_full = '0')) then
blit_src_offset <= blit_src_offset + 8;
elsif STB_O_blit_src = '1' and bus_rdy = '1' then
if blit_src_cnt_x /= blit_nx then
blit_src_cnt_x <= blit_src_cnt_x + 1;
elsif blit_src_do_extra = '1' then
blit_src_do_extra <= '0';
blit_src_offset <= blit_src_offset + 8;
else
if blit_src_unaligned = '1' then
blit_src_do_extra <= '1';
end if;
if blit_src_cnt_y /= blit_ny then
blit_src_cnt_x <= (others => '0');
blit_src_cnt_x <= (others => '0');
blit_src_offset <= blit_src_off_y;
blit_src_cnt_y <= blit_src_cnt_y + 1;
blit_src_off_y <= blit_src_off_y + blit_dimx_src_0;
else
blit_src_finish <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------
inst_align_dst : entity work.align
GENERIC MAP
(
data_width => 64,
aggregate_size => 8
)
PORT MAP
(
rst => blit_reset,
clk => CLK_I,
eb => '1',
ce => blit_dst_re,
offset => blit_addr_dst(2 downto 0),
din_vld => blit_dst_we,
din => blitfifo_src_out,
dout_vld => blit_dst_reg_vld,
dout => blit_dst_reg,
byte_en => blit_dst_reg_be
);
blit_dst_be <= blit_dst_reg_be when blit_dst_first = '1' else
not blit_dst_reg_be when blit_dst_last = '1' else
(others => '1');
blit_dst_we <= not blitfifo_src_empty;
blit_dst_re <= CYC_O_blit_dst and busout_fifo_rdy and not blit_dst_last;
blit_dst_vld <= blit_dst_reg_vld or blit_dst_last;
---------------------------------------------------------------------------------
ADDR_O_blit_dst <= blit_addr_dst(31 downto 3) & "000" + blit_dst_offset;
ADDR_O_blit_dst <= blit_addr_dst + blit_dst_offset;
proc_blit_addr_dst:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if blit_reset = '1' then
blit_dst_cnt_x <= (others => '0');
blit_dst_cnt_y <= (others => '0');
blit_dst_offset <= (others => '0');
blit_dst_off_y <= blit_dimx_dst;
blit_dst_finish <= '0';
blit_dst_cnt_x <= (others => '0');
blit_dst_do_extra <= '0';
blit_dst_first <= '1';
blit_dst_last <= '0';
blit_dst_unaligned <= '0';
if blit_addr_dst (2 downto 0) /= "000" then
blit_dst_unaligned <= '1';
blit_dst_do_extra <= '1';
end if;
elsif blit_dst_finish = '0' and (STB_O_blit_dst = '1' and busout_fifo_rdy = '1') then
blit_dst_first <= blit_dst_last;
blit_dst_last <= '0';
blit_dst_offset <= blit_dst_offset + 8;
elsif STB_O_blit_dst = '1' and bus_rdy = '1' then
if blit_dst_cnt_x /= blit_nx then
blit_dst_cnt_x <= blit_dst_cnt_x + 1;
elsif blit_dst_do_extra = '1' then
blit_dst_do_extra <= '0';
blit_dst_last <= '1';
blit_dst_offset <= blit_dst_offset + 8;
else
if blit_dst_unaligned = '1' then
blit_dst_do_extra <= '1';
end if;
if blit_dst_cnt_y /= blit_ny then
blit_dst_cnt_x <= (others => '0');
blit_dst_cnt_x <= (others => '0');
blit_dst_offset <= blit_dst_off_y;
blit_dst_cnt_y <= blit_dst_cnt_y + 1;
blit_dst_off_y <= blit_dst_off_y + blit_dimx_dst;
@@ -869,7 +652,6 @@ proc_blit_addr_dst:
end if;
end process;
---------------------------------------------------------------------------------
inst_char_gen : entity work.char_gen
GENERIC MAP
(
@@ -1011,8 +793,6 @@ registers_read:
end if;
end process;
blit_const_color_en <= blit_func_sel(0);
registers_write:
process(CLK_I)
begin
@@ -1034,9 +814,6 @@ registers_write:
blit_comb_sel <= (others => '0');
host_fb_front <= X"40000000";
host_fb_back <= X"40010000";
blit_addr_src_0 <= X"40000000";
blit_addr_src_1 <= X"40020000";
blit_addr_dst <= X"40040000";
cg_color <= (X"FF", X"FF", X"FF", X"FF");
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(6 downto 2) is
@@ -1092,7 +869,7 @@ registers_write:
-- sys_blit_descr_src_0
-- 0x20
when "01000" =>
blit_addr_src_0 <= SDAT_I(31 downto 0);
blit_addr_src_0 <= SDAT_I(31 downto 3) & "000";
-- 0x28
when "01010" =>
@@ -1101,7 +878,7 @@ registers_write:
-- sys_blit_descr_src_1
-- 0x30
when "01100" =>
blit_addr_src_1 <= SDAT_I(31 downto 0);
blit_addr_src_1 <= SDAT_I(31 downto 3) & "000";
-- 0x38
when "01110" =>
@@ -1110,12 +887,7 @@ registers_write:
-- sys_blit_descr_dst
-- 0x50
when "10100" =>
blit_addr_dst <= SDAT_I(31 downto 0);
-- sys_blit_const_color
-- 0x54
when "10101" =>
blit_const_color <= SDAT_I(31 downto 0);
blit_addr_dst <= SDAT_I(31 downto 3) & "000";
-- 0x58
when "10110" =>