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This commit was manufactured by cvs2svn to create tag 'MIPS_R12'.

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git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R12@934 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2011-07-24 08:18:46 +00:00
parent faa81b57e9
commit aef784643a
396 changed files with 4562 additions and 83217 deletions
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lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo
+1
View File
@@ -13,6 +13,7 @@ vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd"
vcom -explicit -93 "../src/sdram_config.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
vcom -explicit -93 "../src/reset_virtex4.vhd"
vcom -explicit -93 "../src/sdram_cmd.vhd"
vcom -explicit -93 "../src/sdram_ctrl.vhd"
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo
+2 -3
View File
@@ -14,7 +14,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_fb
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk0_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk270_o
@@ -38,7 +37,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {38990166 ps} 0}
WaveRestoreCursors {{Cursor 1} {76048900 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -52,4 +51,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {38975716 ps} {39081070 ps}
WaveRestoreZoom {0 ps} {210 us}
lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo
+1
View File
@@ -13,6 +13,7 @@ vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd"
vcom -explicit -93 "../src/sdram_config.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
vcom -explicit -93 "../src/reset_virtex4.vhd"
vcom -explicit -93 "../src/sdram_cmd.vhd"
vcom -explicit -93 "../src/sdram_ctrl.vhd"
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo
+2 -6
View File
@@ -21,10 +21,6 @@ add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_we
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_full
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_empty
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270var_o
add wave -noupdate -divider Part
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n
@@ -45,7 +41,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {199582900 ps} 0}
WaveRestoreCursors {{Cursor 1} {52445000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -59,4 +55,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {199427964 ps} {200030108 ps}
WaveRestoreZoom {52319857 ps} {52922001 ps}
lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd
+111
View File
@@ -0,0 +1,111 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Reset generator (Virtex-4 specific)
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity reset is
port
(
clk : in std_logic;
rst_in : in std_logic;
rst_out : out std_logic
);
end;
architecture tech of reset is
signal rst : std_logic;
signal shift_pipe : std_logic_vector(3 downto 0);
attribute KEEP : string;
attribute KEEP of shift_pipe : signal is "TRUE";
begin
rst <= shift_pipe(0);
bufg_reset: bufg
port map
(
o => rst_out,
i => rst
);
fdp0: fdp
generic map
(
init => '1'
)
port map
(
d => rst_in,
c => clk,
pre => '0',
q => shift_pipe(3)
);
fdp1: fdp
generic map
(
init => '1'
)
port map
(
d => shift_pipe(3),
c => clk,
pre => '0',
q => shift_pipe(2)
);
fdp2: fdp
generic map
(
init => '1'
)
port map
(
d => shift_pipe(2),
c => clk,
pre => '0',
q => shift_pipe(1)
);
fdp3: fdp
generic map
(
init => '1'
)
port map
(
d => shift_pipe(1),
c => clk,
pre => '0',
q => shift_pipe(0)
);
end tech;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+4 -26
View File
@@ -29,13 +29,8 @@ use work.sdram_config.all;
use work.sdram_types.all;
entity sdram_cmd is
Generic
(
f_sdrclk : real := 100.0;
BL : natural := 2
);
Port
(
Generic (BL : natural := 2);
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
@@ -57,7 +52,7 @@ architecture behaviour of sdram_cmd is
signal st_sdr, st_sdr_next : sdr_state_t;
signal cc_preset : natural range 0 to 15;
signal cc_preset : natural range 0 to 10;
signal cc_load_en : std_logic;
signal cycle_finished : std_logic;
@@ -65,23 +60,6 @@ architecture behaviour of sdram_cmd is
signal burst_load_en : std_logic;
signal burst_finished : std_logic;
subtype cycle_cnt_t is natural range 0 to 15;
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
constant TIMING : part_timing_array_t :=
-- command cycle_cnt
( SD_DESELECT => (0 ),
SD_NOP => (0 ),
SD_LMR => (TMRD-1 ),
SD_ACT => (to_cycles(TRCD, f_sdrclk)-1),
SD_READ => (TCAS-1 ),
SD_WRITE => (to_cycles(TWR, f_sdrclk)-1),
SD_PRE => (to_cycles(TRP, f_sdrclk)-1),
SD_BST => (0 ),
SD_AR => (to_cycles(TRFC, f_sdrclk)-1),
SD_SR => (to_cycles(TRFC, f_sdrclk)-1)
);
begin
u_tag_out <= u_tag_in;
@@ -249,7 +227,7 @@ fsm_sdr_state_next:
------------------------------------------------------------------------------------------
cycle_counter:
process (rst, clk)
variable cycle_cnt : natural range 0 to 15;
variable cycle_cnt : natural range 0 to 10;
begin
if rst = '1' then
cycle_cnt := 0;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
+9 -9
View File
@@ -54,18 +54,18 @@ package sdram_config is
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
constant REFRESH_INTERVAL : real := 7.8125; -- us
-- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : real := 20.0; -- precharge command period [ns]
constant TRAS : real := 45.0; -- active to precharge delay [ns]
constant TRFC : real := 75.0; -- auto refresh command period [ns]
constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
constant TRCD : real := 20.0; -- active to read or write delay [ns]
constant TWR : real := 15.0; -- write recovery time [ns]
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : positive := 2; -- precharge command period
constant TRAS : positive := 4; -- active to precharge delay
constant TRFC : positive := 8; -- auto refresh command period
constant TMRD : positive := 2; -- load mode register command cylce time
constant TRCD : positive := 2; -- active to read or write delay !
constant TWR : positive := 2; -- write recovery time
constant PWR_UP_WAIT : real := 1.0E3; -- [ns]
constant PWR_UP_WAIT : natural := 1; -- µs
subtype user_tag_t is unsigned(3 downto 0);
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+4 -4
View File
@@ -32,8 +32,8 @@ use work.utils_pkg.all;
entity sdram_ctrl is
Generic
(
f_sysclk : real := 100.0;
BL : natural := 2
f_sysclk : natural := 100E6;
BL : natural := 2
);
Port (
rst : in STD_LOGIC;
@@ -60,7 +60,7 @@ architecture behaviour of sdram_ctrl is
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t;
constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk);
constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
signal pwr_up_cnt_rst : std_logic;
signal pwr_up_finished : std_logic;
@@ -74,7 +74,7 @@ architecture behaviour of sdram_ctrl is
signal seq_rst_en : std_logic;
signal seq_cnt_en : std_logic;
constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk);
constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
signal refresh_request : std_logic;
signal refresh_cnt_rst : std_logic;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+3 -5
View File
@@ -32,10 +32,9 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend64_wb is
Generic
(
BL : natural := 2;
f_sysclk : real := 100.0;
f_sdrclk : real := 100.0;
fifo_depth : integer := 4
BL : natural := 2;
f_sysclk : natural := 100E6;
fifo_depth : integer := 4
);
Port
(
@@ -206,7 +205,6 @@ begin
(
BL => BL,
f_sysclk => f_sysclk,
f_sdrclk => f_sdrclk,
fifo_depth => fifo_depth
)
Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+2 -4
View File
@@ -32,9 +32,8 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend_wb is
Generic
(
BL : natural := 2;
f_sysclk : real := 100.0;
f_sdrclk : real := 100.0;
BL : natural := 2;
f_sysclk : natural := 100E6;
fifo_depth : integer := 4
);
Port
@@ -206,7 +205,6 @@ begin
(
BL => BL,
f_sysclk => f_sysclk,
f_sdrclk => f_sdrclk,
fifo_depth => fifo_depth
)
Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+17 -11
View File
@@ -31,9 +31,8 @@ use work.sdram_types.all;
entity sdram_ctrl_top is
Generic
(
BL : natural := 2;
f_sysclk : real := 100.0;
f_sdrclk : real := 100.0;
BL : natural := 2;
f_sysclk : natural := 100E6;
fifo_depth : natural := 3
);
Port
@@ -92,6 +91,7 @@ architecture rtl of sdram_ctrl_top is
-- Clock generator
signal ctrl_rst : std_logic;
signal part_ctrl : part_ctrl_t;
-- SD command FIFO
@@ -128,17 +128,24 @@ begin
sd_cmd <= sdr_cmd_t(to_integer(sd_cmd_fifo_out));
---------------------------------
inst_reset: entity work.reset
port map
(
clk => sys_clk_in,
rst_in => sys_rst_in,
rst_out => ctrl_rst
);
-- Main controller
inst_sdram_ctrl : entity work.sdram_ctrl
Generic map
(
f_sysclk => f_sysclk,
BL => BL
f_sysclk => 100E6,
BL => BL
)
Port map
(
rst => sys_rst_in,
rst => ctrl_rst,
clk => sys_clk_in,
u_busy => u_busy,
u_tag_in => u_tag_in,
@@ -163,7 +170,7 @@ begin
)
PORT MAP
(
rst => sys_rst_in,
rst => ctrl_rst,
clk_w => sys_clk_in,
clk_r => sdram_clk0_in,
we => cmd_fifo_we,
@@ -180,12 +187,11 @@ begin
inst_sdram_cmd : entity work.sdram_cmd
Generic map
(
f_sdrclk => f_sdrclk,
BL => BL
)
Port map
(
rst => sys_rst_in,
rst => ctrl_rst,
clk => sdram_clk0_in,
u_tag_in => sd_tag_fifo_out,
u_tag_out => u_tag,
@@ -205,7 +211,7 @@ begin
inst_ddr_phy : entity work.ddr_phy
Port map
(
sys_rst => sys_rst_in,
sys_rst => ctrl_rst,
sys_clk0 => sdram_clk0_in,
sys_clk270 => sdram_clk270_in,
u_tag_in => u_tag,
lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+17 -14
View File
@@ -24,7 +24,6 @@
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;
use work.sdram_config.all;
@@ -68,6 +67,8 @@ package sdram_types is
subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
subtype col_addr_t is unsigned(8 downto 0);
subtype cycle_cnt_t is natural range 0 to 10;
type phy_ctrl_t is
record
drive_en : std_logic;
@@ -107,6 +108,21 @@ package sdram_types is
SD_SR => ( '0', '0', '0', '1')
);
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
constant TIMING : part_timing_array_t :=
-- command cycle_cnt
( SD_DESELECT => ( 0 ),
SD_NOP => ( 0 ),
SD_LMR => ( TMRD-1 ),
SD_ACT => ( TRCD-1 ),
SD_READ => ( TCAS-1 ),
SD_WRITE => ( TWR-1 ),
SD_PRE => ( TRP-1 ),
SD_BST => ( 0 ),
SD_AR => ( TRFC-1 ),
SD_SR => ( TRFC-1 )
);
type init_seq_t is
record
cmd : sdr_cmd_t;
@@ -114,17 +130,4 @@ package sdram_types is
wait_cycle : natural;
end record init_seq_t;
function to_cycles(T_ns : real; f_Mhz : real) return natural;
end sdram_types;
package body sdram_types is
function to_cycles(T_ns : real; f_Mhz : real) return natural is
begin
return natural(ceil(1.0E-3*T_ns*f_Mhz));
end to_cycles;
end sdram_types;
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+3 -4
View File
@@ -36,7 +36,7 @@ architecture struct of tb_sdram_ctrl_frontend64_wb is
-- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns;
constant SDCLK_PERIOD : time := 7.5 ns;
constant SDCLK_PERIOD : time := 8 ns;
constant BURST_LEN : natural := 2;
signal rst : std_logic := '1';
@@ -122,7 +122,7 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq => 100.0,
clk_in_freq_hz => 100E6,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
@@ -151,8 +151,7 @@ inst_clockgen : entity work.clockgen
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => 100.000,
f_sdrclk => 133.333,
f_sysclk => 100E6,
fifo_depth => 4
)
PORT MAP
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+2 -3
View File
@@ -119,7 +119,7 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq => 100.0,
clk_in_freq_hz => 100E6,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
@@ -146,8 +146,7 @@ inst_clockgen : entity work.clockgen
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => 100.0,
f_sdrclk => 100.0,
f_sysclk => 100E6,
fifo_depth => 4
)
PORT MAP