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This commit was manufactured by cvs2svn to create tag 'MIPS_R12'.

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git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R12@934 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2011-07-24 08:18:46 +00:00
parent faa81b57e9
commit aef784643a
396 changed files with 4562 additions and 83217 deletions
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lib/FIFO/src/sync_fifo_ctrl.vhd
+19 -15
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@@ -37,8 +37,8 @@ entity fifo_sync_ctrl is
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
winc : in STD_LOGIC;
rinc : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
ptr_w : out unsigned (addr_width-1 downto 0);
ptr_r : out unsigned (addr_width-1 downto 0);
fifo_pre_full : out STD_LOGIC;
@@ -57,10 +57,14 @@ architecture Behavioral of fifo_sync_ctrl is
signal empty, full : std_logic;
signal pre_empty, pre_full : std_logic;
signal was_write : std_logic;
signal write, read : std_logic;
signal diff : unsigned (addr_width downto 0);
begin
read <= re and not empty;
write <= we and not full;
fifo_full <= full;
fifo_empty <= empty;
fifo_pre_full <= pre_full;
@@ -73,9 +77,9 @@ proc_diff_gen:
if rst = '1' then
diff <= (others => '0');
elsif rising_edge(clk) then
if winc = '1' and rinc = '0' then
if write = '1' and read = '0' then
diff <= diff + 1;
elsif winc = '0' and rinc = '1' then
elsif write = '0' and read = '1' then
diff <= diff - 1;
end if;
end if;
@@ -130,14 +134,14 @@ proc_empty_reg:
end process;
proc_status_w:
process(was_write, pW_next, pR_next, pW, pR, winc, rinc)
process(was_write, pW_next, pR_next, pW, pR, write, read)
begin
if (pW_next = pR) and (winc = '1' or was_write = '1') then
if (pW_next = pR) and (write = '1' or was_write = '1') then
pre_full <= '1';
else
pre_full <= '0';
end if;
if (pR_next = pW) and (rinc = '1' or was_write = '0') then
if (pR_next = pW) and (read = '1' or was_write = '0') then
pre_empty <= '1';
else
pre_empty <= '0';
@@ -150,45 +154,45 @@ proc_flag_write:
if rst = '1' then
was_write <= '0';
elsif rising_edge(clk) then
if winc = '1' then
if write = '1' then
was_write <= '1';
elsif rinc = '1' then
elsif read = '1' then
was_write <= '0';
end if;
end if;
end process;
proc_ptr_w:
process(rst, clk, pW, winc)
process(rst, clk, pW, write, full)
begin
if rst = '1' then
pW <= to_unsigned(0, addr_width);
pW_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if winc = '1' then
if write = '1' then
pW <= pW_next;
end if;
end if;
pW_next <= pW;
if winc = '1' then
if write = '1' then
pW_next <= pW + 1;
end if;
ptr_w <= pW;
end process;
proc_ptr_r:
process(rst, clk, pR_next, pR, rinc)
process(rst, clk, pR_next, pR, read, empty)
begin
if rst = '1' then
pR <= to_unsigned(0, addr_width);
pR_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if rinc = '1' then
if read = '1' then
pR <= pR_next;
end if;
end if;
pR_next <= pR;
if rinc = '1' then
if read = '1' then
pR_next <= pR + 1;
end if;
ptr_r <= pR_next;