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git-svn-id: http://moon:8086/svn/vhdl/trunk@8 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-08-23 08:34:09 +00:00
parent d3bd08bb52
commit a87b40a4be
27 changed files with 10441 additions and 0 deletions
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projects/mips_sys/tools/insrom.rb
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#!/usr/bin/env ruby
# ----------------------------------------------------------------------
# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
# This file: Insertion of code fragments into templates
#
# Copyright (C) 2008 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
arg = $*
rom_filename = arg[0].to_s
tpl_filename = arg[1].to_s
subst_pattern = "ROM_INSERT_HERE"
# --------------------------------------------------------
# Open file
# --------------------------------------------------------
romfile = File.open(rom_filename, "r")
tplfile = File.open(tpl_filename, "r")
re = Regexp.new(subst_pattern)
while (line = tplfile.gets)
puts line
line.scan(re).each do |word|
romfile.each do |raw_line|
puts raw_line
end
end
end
projects/mips_sys/tools/irom.vhd.tpl
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-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
-- ROM_INSERT_HERE
projects/mips_sys/tools/irom_ld.vhd.tpl
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-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: loadable ROM
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
ENTITY irom IS
Port (
clk : in STD_LOGIC;
addr : in inst_addr_t;
dout : out inst_t
);
END irom;
ARCHITECTURE loadable OF irom IS
-- JASM_ROM_INSERT_HERE
signal jtag_ld_clk : STD_LOGIC;
signal jtag_ld_we : STD_LOGIC;
signal jtag_ld_addr : unsigned (15 downto 0);
signal jtag_ld_dout : unsigned (31 downto 0);
signal jtag_ld_din : unsigned (31 downto 0);
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
signal user_regi, user_rego : unsigned (47 downto 0);
constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
begin
--------------------------------------------------------------------------
-- Virtex-4: JTAG Loader
--------------------------------------------------------------------------
i00_BUFG : BUFG
port map
(
O => bs_clk1,
I => bs_clk0
);
i01_BUFG : BUFG
port map
(
O => bs_update1,
I => bs_update0
);
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
generic map
(
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
)
port map
(
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
DRCK => bs_clk0, -- Data register output for USER functions
RESET => bs_rst, -- Reset output from TAP controller
SEL => bs_sel, -- USER active output
SHIFT => bs_shift, -- SHIFT output from TAP controller
TDI => bs_tdi, -- TDI output from TAP controller
UPDATE => bs_update0, -- UPDATE output from TAP controller
TDO => bs_tdo -- Data input for USER function
);
jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
jtag_ld_clk <= bs_update1;
jtag_ld_we <= bs_sel;
sipo:
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
begin
if bs_rst = '1' then
user_regi <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
end if;
end if;
end process;
piso:
process (bs_rst, bs_clk1, bs_shift, user_rego)
begin
bs_tdo <= user_rego(0);
if bs_rst = '1' then
user_rego <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
else
user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;
-- user_rego <= id;
end if;
end if;
end process;
PROM_WRITE:
process(jtag_ld_clk, jtag_ld_we)
begin
if rising_edge(jtag_ld_clk) then
if jtag_ld_we = '1' then
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
else
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
end if;
end if;
end process;
--------------------------------------------------------------------------
-- ROM Read/Write
--------------------------------------------------------------------------
PROM_READ:
process(clk)
begin
if rising_edge(clk) then
dout <= imem_rom(to_integer(addr));
end if;
end process;
--------------------------------------------------------------------------
end loadable;
projects/mips_sys/tools/make
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#!/bin/sh
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: rom-file generation for cpu_core
#
# Copyright (C) 2007 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
TARGET=$2
DSTDIR=$1
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
$JASM_HOME/jasm.rb $TARGET.jsm
irom_tcl_snippet="$TARGET.irom.tcl.snip"
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
rm -f *.snip
projects/mips_sys/tools/rom.tcl.tpl
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# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: The ROM file for upload to target over JTAG
#
# Copyright (C) 2007 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
# ---------------------------------------------------------------------
# For Chipscope 9.1
# ---------------------------------------------------------------------
# Source JTAG/TCL frame work
cd $env(CHIPSCOPE)\\bin\\nt
source csejtag.tcl
namespace import ::chipscope::*
# Platform USB Cable
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
# Create session
set handle [::chipscope::csejtag_session create 0]
# Open JTAG and lock
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
set lock_result [::chipscope::csejtag_target lock $handle 1000]
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
# Get Device ID
set devtype "Virtex-4SX"
set devid 2
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
set CSE_OP $CSEJTAG_SHIFT_READWRITE
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
# Write Program
# JASM_ROM_INSERT_HERE
::chipscope::csejtag_target unlock $handle
::chipscope::csejtag_target close $handle
::chipscope::csejtag_session destroy $handle
exit
projects/mips_sys/tools/src/ramgen.c
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define ARCH_NAME "data"
#define ENT_NAME "ram"
#define JTAG_ADDR_WIDTH 16
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1);
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "library UNISIM;\n");
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "\n");
fputs(tpl, pFileOut);
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\telse\n");
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, word_addr, filesize, romsize;
char binstr_addr[33];
char binstr_data[33];
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fputs(tpl, pFileOut);
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
fprintf(pFileOut, "# User 2\n");
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
word_addr = 0;
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
word_addr++;
}
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
fprintf(pFileOut, "exit\n");
return 0;
}
int main(int argc, char *argv[])
{
char *pFilenameIn;
char name_prj[1024];
char name_rom_tcl[1024];
char name_rom[1024];
char name_rom_v4ld[1024];
FILE *pFileIn;
int filesize, romsize, nbits_addr, nbits_data;
long start, end;
int word, i;
if (argc < 2)
{
fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
return 1;
}
pFilenameIn = argv[1];
if (argc == 3)
nbits_addr = atoi(argv[2]);
basename(pFilenameIn, name_prj);
sprintf(name_rom, "%s.vhd", name_prj);
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
sprintf(name_rom_tcl, "%s.tcl", name_prj);
SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
return 0;
}
projects/mips_sys/tools/src/romgen.c
+368
View File
@@ -0,0 +1,368 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define ARCH_NAME "data"
#define ENT_NAME "rom"
#define JTAG_ADDR_WIDTH 16
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "library UNISIM;\n");
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "\n");
fputs(tpl, pFileOut);
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\telse\n");
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, word_addr, filesize, romsize;
char binstr_addr[33];
char binstr_data[33];
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fputs(tpl, pFileOut);
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
fprintf(pFileOut, "# User 1\n");
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
word_addr = 0;
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
word_addr++;
}
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
fprintf(pFileOut, "exit\n");
return 0;
}
int main(int argc, char *argv[])
{
char *pFilenameIn;
char name_prj[1024];
char name_rom[1024];
char name_rom_v4ld[1024];
char name_rom_tcl[1024];
FILE *pFileIn;
int filesize, romsize, nbits_addr, nbits_data;
long start, end;
int word, i;
if (argc < 2)
{
fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
return 1;
}
pFilenameIn = argv[1];
if (argc == 3)
nbits_addr = atoi(argv[2]);
basename(pFilenameIn, name_prj);
sprintf(name_rom, "%s.vhd", name_prj);
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
sprintf(name_rom_tcl, "%s.tcl", name_prj);
SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
return 0;
}