From a87b40a4be2d3c65bdde9f762ab571e9797dc2c8 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 23 Aug 2008 08:34:09 +0000 Subject: [PATCH] Initial import git-svn-id: http://moon:8086/svn/vhdl/trunk@8 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/ise91/mips_sys/mips_sys.prj | 35 + .../mips_sys/ise91/mips_sys/mips_sys_vhdl.prj | 35 + .../mips_sys/ise91/mips_sys/ucf/systest.ucf | 245 ++ projects/mips_sys/ise92/mips_sys/mips_sys.prj | 39 + .../mips_sys/ise92/mips_sys/mips_sys_vhdl.prj | 39 + .../mips_sys/ise92/mips_sys/ucf/systest.ucf | 245 ++ projects/mips_sys/sim/tb_mips_sys.fdo | 70 + projects/mips_sys/sim/tb_mips_sys.wdo | 243 ++ projects/mips_sys/src/bootloader.ROM.vhd | 2082 ++++++++++++++++ projects/mips_sys/src/bootloader.ROM_ld.vhd | 2174 +++++++++++++++++ projects/mips_sys/src/bootloader.dis | 1229 ++++++++++ projects/mips_sys/src/mips_pipeline.vhd | 886 +++++++ projects/mips_sys/src/mips_sys.vhd | 681 ++++++ projects/mips_sys/src/mips_sys_cfg.vhd | 19 + projects/mips_sys/src/mips_sys_sim.vhd | 716 ++++++ projects/mips_sys/src/ram_ld.vhd | 173 ++ projects/mips_sys/src/ram_sim.vhd | 88 + projects/mips_sys/src/sdram_config.vhd | 74 + projects/mips_sys/src/sdram_config_sim.vhd | 74 + projects/mips_sys/src/tb_mips_sys.vhd | 208 ++ projects/mips_sys/tools/insrom.rb | 46 + projects/mips_sys/tools/irom.vhd.tpl | 29 + projects/mips_sys/tools/irom_ld.vhd.tpl | 147 ++ projects/mips_sys/tools/make | 50 + projects/mips_sys/tools/rom.tcl.tpl | 61 + projects/mips_sys/tools/src/ramgen.c | 385 +++ projects/mips_sys/tools/src/romgen.c | 368 +++ 27 files changed, 10441 insertions(+) create mode 100644 projects/mips_sys/ise91/mips_sys/mips_sys.prj create mode 100644 projects/mips_sys/ise91/mips_sys/mips_sys_vhdl.prj create mode 100644 projects/mips_sys/ise91/mips_sys/ucf/systest.ucf create mode 100644 projects/mips_sys/ise92/mips_sys/mips_sys.prj create mode 100644 projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj create mode 100644 projects/mips_sys/ise92/mips_sys/ucf/systest.ucf create mode 100644 projects/mips_sys/sim/tb_mips_sys.fdo create mode 100644 projects/mips_sys/sim/tb_mips_sys.wdo create mode 100644 projects/mips_sys/src/bootloader.ROM.vhd create mode 100644 projects/mips_sys/src/bootloader.ROM_ld.vhd create mode 100644 projects/mips_sys/src/bootloader.dis create mode 100644 projects/mips_sys/src/mips_pipeline.vhd create mode 100644 projects/mips_sys/src/mips_sys.vhd create mode 100644 projects/mips_sys/src/mips_sys_cfg.vhd create mode 100644 projects/mips_sys/src/mips_sys_sim.vhd create mode 100644 projects/mips_sys/src/ram_ld.vhd create mode 100644 projects/mips_sys/src/ram_sim.vhd create mode 100644 projects/mips_sys/src/sdram_config.vhd create mode 100644 projects/mips_sys/src/sdram_config_sim.vhd create mode 100644 projects/mips_sys/src/tb_mips_sys.vhd create mode 100644 projects/mips_sys/tools/insrom.rb create mode 100644 projects/mips_sys/tools/irom.vhd.tpl create mode 100644 projects/mips_sys/tools/irom_ld.vhd.tpl create mode 100644 projects/mips_sys/tools/make create mode 100644 projects/mips_sys/tools/rom.tcl.tpl create mode 100644 projects/mips_sys/tools/src/ramgen.c create mode 100644 projects/mips_sys/tools/src/romgen.c diff --git a/projects/mips_sys/ise91/mips_sys/mips_sys.prj b/projects/mips_sys/ise91/mips_sys/mips_sys.prj new file mode 100644 index 0000000..4b296ce --- /dev/null +++ b/projects/mips_sys/ise91/mips_sys/mips_sys.prj @@ -0,0 +1,35 @@ +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd" +vhdl work "../../src/sdram_config.vhd" +vhdl work "../../../../lib/misc/utils_pkg.vhd" +vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" +vhdl work "../../../../lib/misc/dpram_1w2r.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd" +vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd" +vhdl work "../../../../lib/uart/kcuart_tx.vhd" +vhdl work "../../../../lib/uart/kcuart_rx.vhd" +vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" +vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd" +vhdl work "../../src/ram_ld.vhd" +vhdl work "../../asm/bootloader/bootloader.ROM_ld.vhd" +vhdl work "../../../../lib/uart/uart_tx.vhd" +vhdl work "../../../../lib/uart/uart_rx.vhd" +vhdl work "../../../../lib/misc/lcd_port.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd" +vhdl work "../../src/mips_sys.vhd" diff --git a/projects/mips_sys/ise91/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise91/mips_sys/mips_sys_vhdl.prj new file mode 100644 index 0000000..ae12a00 --- /dev/null +++ b/projects/mips_sys/ise91/mips_sys/mips_sys_vhdl.prj @@ -0,0 +1,35 @@ +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd" +vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd" +vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" +vhdl work "W:\vhdl\lib\misc\dpram_1w2r.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd" +vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd" +vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd" +vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd" +vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd" +vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd" +vhdl work "W:\vhdl\projects\mips_sys\asm\bootloader\bootloader.ROM_ld.vhd" +vhdl work "W:\vhdl\lib\uart\uart_tx.vhd" +vhdl work "W:\vhdl\lib\uart\uart_rx.vhd" +vhdl work "W:\vhdl\lib\misc\lcd_port.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd" diff --git a/projects/mips_sys/ise91/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise91/mips_sys/ucf/systest.ucf new file mode 100644 index 0000000..002dee1 --- /dev/null +++ b/projects/mips_sys/ise91/mips_sys/ucf/systest.ucf @@ -0,0 +1,245 @@ +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR +# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION +# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION +# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS +# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE. +# +# (c) Copyright 2005 Xilinx, Inc. +# All rights reserved. +# + +CONFIG STEPPING = "ES"; + +# Bus clock nets +NET "clk" TNM_NET = "clk"; +TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %; + +NET "sys_clk_in" LOC = "AE14"; +#NET sys_clk_in IOSTANDARD = LVCMOS33; +NET "sys_rst_n_in" LOC = "D6"; +NET sys_rst_n_in PULLUP; +NET "sys_rst_n_in" TIG; +NET "rst" TIG; + +# Locate DCM/BUFG - Tools can probably figure them out automatically +# but just LOC them down to be safe +#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2; +#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1; + +//////////////////////////////////////////////////////////////////////////// +// Misc Board Signals +//////////////////////////////////////////////////////////////////////////// + +NET sys_error<0> LOC = V6; +NET sys_error<1> LOC = L24; +#NET sys_error<*> IOSTANDARD = LVCMOS33; +NET sys_error<*> DRIVE = 2; +NET sys_error<*> TIG; + +//////////////////////////////////////////////////////////////////////////// +// RS-232 +//////////////////////////////////////////////////////////////////////////// +NET sys_rx LOC = W2; +#NET sys_rx IOSTANDARD = LVCMOS33; +NET sys_rx TIG; +NET "sys_tx" LOC = "W1"; +#NET sys_tx IOSTANDARD = LVCMOS33; +NET "sys_tx" TIG; + +//////////////////////////////////////////////////////////////////////////// +// Buttons, LEDs, and DIP Switches +//////////////////////////////////////////////////////////////////////////// +# GPLED 0-3 +NET "sys_led<0>" LOC = "G5"; #GPLED0 +NET "sys_led<1>" LOC = "G6"; #GPLED1 +NET "sys_led<2>" LOC = "A11"; #GPLED2 +NET "sys_led<3>" LOC = "A12"; #GPLED3 +# North-East-South-West-Center LEDs +NET "sys_led<4>" LOC = "F9"; # W LED +NET "sys_led<5>" LOC = "E2"; # N LED +NET "sys_led<6>" LOC = "E10"; # E LED +NET "sys_led<7>" LOC = "A5"; # S LED +NET "sys_led<8>" LOC = "C6"; # C LED +NET "sys_led<*>" TIG; +NET "sys_led<*>" SLEW = SLOW; +NET "sys_led<*>" DRIVE = 2; +#NET "sys_led<*>" IOSTANDARD = LVCMOS33; +# North-East-South-West-Center Buttons +NET "sys_btn<0>" LOC = "E9"; # W Button +NET "sys_btn<1>" LOC = "E7"; # N Button +NET "sys_btn<2>" LOC = "F10"; # E Button +NET "sys_btn<3>" LOC = "A6"; # S Button +NET "sys_btn<4>" LOC = "B6"; # C Button +NET "sys_btn<*>" TIG; +NET "sys_btn<*>" PULLDOWN; +#NET "sys_btn<*>" IOSTANDARD = LVCMOS33; +# Dip Switches 1-8 +NET "sys_dip<7>" LOC = "U24"; # DIP SW 8 +NET "sys_dip<6>" LOC = "U25"; # DIP SW 7 +NET "sys_dip<5>" LOC = "V23"; # DIP SW 6 +NET "sys_dip<4>" LOC = "U23"; # DIP SW 5 +NET "sys_dip<3>" LOC = "U26"; # DIP SW 4 +NET "sys_dip<2>" LOC = "T26"; # DIP SW 3 +NET "sys_dip<1>" LOC = "R19"; # DIP SW 2 +NET "sys_dip<0>" LOC = "R20"; # DIP SW 1 +NET "sys_dip<*>" PULLDOWN; +#NET "sys_dip<*>" IOSTANDARD = LVCMOS33; +NET "sys_dip<*>" TIG; +//////////////////////////////////////////////////////////////////////////// +// LCD +//////////////////////////////////////////////////////////////////////////// +NET sys_lcd_e LOC = AE13; # LCD_E +#NET sys_lcd_e IOSTANDARD = LVCMOS33; +NET sys_lcd_e SLEW = SLOW; +NET sys_lcd_e DRIVE = 2; +NET sys_lcd_e TIG; +NET sys_lcd_rs LOC = AC17; # LCD_RS +#NET sys_lcd_rs IOSTANDARD = LVCMOS33; +NET sys_lcd_rs SLEW = SLOW; +NET sys_lcd_rs DRIVE = 2; +NET sys_lcd_rs TIG; +NET sys_lcd_rw LOC = AB17; # LCD_RW +#NET sys_lcd_rw IOSTANDARD = LVCMOS33; +NET sys_lcd_rw SLEW = SLOW; +NET sys_lcd_rw DRIVE = 2; +NET sys_lcd_rw TIG; +NET sys_lcd_d<3> LOC = AF12; # LCD_DB7 +NET sys_lcd_d<2> LOC = AE12; # LCD_DB6 +NET sys_lcd_d<1> LOC = AC10; # LCD_DB5 +NET sys_lcd_d<0> LOC = AB10; # LCD_DB4 +#NET sys_lcd_d<*> IOSTANDARD = LVCMOS33; +NET sys_lcd_d<*> SLEW = SLOW; +NET sys_lcd_d<*> DRIVE = 2; +NET sys_lcd_d<*> PULLDOWN; +NET sys_lcd_d<*> TIG; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for DDR Controllers +#------------------------------------------------------------------------------ + +NET sys_sdr_a_q<0> LOC = C26; # DDR_A0 +NET sys_sdr_a_q<1> LOC = E17; # DDR_A1 +NET sys_sdr_a_q<2> LOC = D18; # DDR_A2 +NET sys_sdr_a_q<3> LOC = C19; # DDR_A3 +NET sys_sdr_a_q<4> LOC = F17; # DDR_A4 +NET sys_sdr_a_q<5> LOC = B18; # DDR_A5 +NET sys_sdr_a_q<6> LOC = B20; # DDR_A6 +NET sys_sdr_a_q<7> LOC = C20; # DDR_A7 +NET sys_sdr_a_q<8> LOC = D20; # DDR_A8 +NET sys_sdr_a_q<9> LOC = C21; # DDR_A9 +NET sys_sdr_a_q<10> LOC = A18; # DDR_A10 +NET sys_sdr_a_q<11> LOC = B21; # DDR_A11 +NET sys_sdr_a_q<12> LOC = A24; # DDR_A12 +NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0 +NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1 +NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N +NET sys_sdr_cke_q LOC = G22; # DDR_CKE +NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N +NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N +NET sys_sdr_we_qn LOC = A23; # DDR_WE_N + +NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P +NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) +NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N + +NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0 +NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1 +NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2 +NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3 + +NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0 +NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1 +NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2 +NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3 + +NET sys_sdr_data<0> LOC = H20; # DDR_D0 +NET sys_sdr_data<1> LOC = E23; # DDR_D1 +NET sys_sdr_data<2> LOC = H26; # DDR_D2 +NET sys_sdr_data<3> LOC = H22; # DDR_D3 +NET sys_sdr_data<4> LOC = E25; # DDR_D4 +NET sys_sdr_data<5> LOC = E26; # DDR_D5 +NET sys_sdr_data<6> LOC = F26; # DDR_D6 +NET sys_sdr_data<7> LOC = E24; # DDR_D7 +NET sys_sdr_data<8> LOC = E20; # DDR_D8 +NET sys_sdr_data<9> LOC = A22; # DDR_D9 +NET sys_sdr_data<10> LOC = C23; # DDR_D10 +NET sys_sdr_data<11> LOC = C24; # DDR_D11 +NET sys_sdr_data<12> LOC = A20; # DDR_D12 +NET sys_sdr_data<13> LOC = A21; # DDR_D13 +NET sys_sdr_data<14> LOC = D24; # DDR_D14 +NET sys_sdr_data<15> LOC = E18; # DDR_D15 +NET sys_sdr_data<16> LOC = F18; # DDR_D16 +NET sys_sdr_data<17> LOC = A19; # DDR_D17 +NET sys_sdr_data<18> LOC = F19; # DDR_D18 +NET sys_sdr_data<19> LOC = B23; # DDR_D19 +NET sys_sdr_data<20> LOC = E21; # DDR_D20 +NET sys_sdr_data<21> LOC = D22; # DDR_D21 +NET sys_sdr_data<22> LOC = D23; # DDR_D22 +NET sys_sdr_data<23> LOC = B24; # DDR_D23 +NET sys_sdr_data<24> LOC = E22; # DDR_D24 +NET sys_sdr_data<25> LOC = F20; # DDR_D25 +NET sys_sdr_data<26> LOC = H23; # DDR_D26 +NET sys_sdr_data<27> LOC = G25; # DDR_D27 +NET sys_sdr_data<28> LOC = G26; # DDR_D28 +NET sys_sdr_data<29> LOC = H25; # DDR_D29 +NET sys_sdr_data<30> LOC = H24; # DDR_D30 +NET sys_sdr_data<31> LOC = H21; # DDR_D31 + +NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I; +NET sys_sdr_a_q<*> FAST; + +NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I; +NET sys_sdr_ba_q<*> FAST; + +NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_cas_qn FAST; + +NET sys_sdr_cke_q IOSTANDARD = SSTL2_I; +NET sys_sdr_cke_q FAST; + +NET sys_sdr_clk_p IOSTANDARD = SSTL2_I; +NET sys_sdr_clk_p FAST; +NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25; +NET sys_sdr_clk_fb IOBDELAY = NONE; +NET sys_sdr_clk_n IOSTANDARD = SSTL2_I; +NET sys_sdr_clk_n FAST; + +NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_cas_qn FAST; + +NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_cs_qn FAST; + +NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_ras_qn FAST; + +NET sys_sdr_we_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_we_qn FAST; + +NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II; +NET sys_sdr_dqs_q<*> IOBDELAY = NONE; +NET sys_sdr_dqs_q<*> FAST; + +NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II; +NET sys_sdr_dm_q<*> IOBDELAY = NONE; +NET sys_sdr_dm_q<*> FAST; + +NET sys_sdr_data<*> IOSTANDARD = SSTL2_II; +NET sys_sdr_data<*> IOBDELAY = NONE; +NET sys_sdr_data<*> FAST; + +#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n"; + + +# Timing Constraint for DDR Feedback Clock +NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p; + diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys.prj b/projects/mips_sys/ise92/mips_sys/mips_sys.prj new file mode 100644 index 0000000..16bb313 --- /dev/null +++ b/projects/mips_sys/ise92/mips_sys/mips_sys.prj @@ -0,0 +1,39 @@ +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd" +vhdl work "../../src/sdram_config.vhd" +vhdl work "../../../../lib/misc/utils_pkg.vhd" +vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd" +vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd" +vhdl work "../../../../lib/misc/dpram_1w1r_dist.vhd" +vhdl work "../../../../lib/misc/dpram_1w1r.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd" +vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/icache.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/dcache.vhd" +vhdl work "../../../../lib/uart/kcuart_tx.vhd" +vhdl work "../../../../lib/uart/kcuart_rx.vhd" +vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd" +vhdl work "../../src/ram_ld.vhd" +vhdl work "../../src/bootloader.ROM_ld.vhd" +vhdl work "../../../../lib/uart/uart_tx.vhd" +vhdl work "../../../../lib/uart/uart_rx.vhd" +vhdl work "../../../../lib/misc/lcd_port.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd" +vhdl work "../../src/mips_sys.vhd" diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj new file mode 100644 index 0000000..01957df --- /dev/null +++ b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj @@ -0,0 +1,39 @@ +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd" +vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd" +vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd" +vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd" +vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd" +vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd" +vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd" +vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd" +vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd" +vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd" +vhdl work "W:\vhdl\lib\uart\uart_tx.vhd" +vhdl work "W:\vhdl\lib\uart\uart_rx.vhd" +vhdl work "W:\vhdl\lib\misc\lcd_port.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_frontend.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd" diff --git a/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf new file mode 100644 index 0000000..002dee1 --- /dev/null +++ b/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf @@ -0,0 +1,245 @@ +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR +# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION +# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION +# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS +# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE. +# +# (c) Copyright 2005 Xilinx, Inc. +# All rights reserved. +# + +CONFIG STEPPING = "ES"; + +# Bus clock nets +NET "clk" TNM_NET = "clk"; +TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %; + +NET "sys_clk_in" LOC = "AE14"; +#NET sys_clk_in IOSTANDARD = LVCMOS33; +NET "sys_rst_n_in" LOC = "D6"; +NET sys_rst_n_in PULLUP; +NET "sys_rst_n_in" TIG; +NET "rst" TIG; + +# Locate DCM/BUFG - Tools can probably figure them out automatically +# but just LOC them down to be safe +#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2; +#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1; + +//////////////////////////////////////////////////////////////////////////// +// Misc Board Signals +//////////////////////////////////////////////////////////////////////////// + +NET sys_error<0> LOC = V6; +NET sys_error<1> LOC = L24; +#NET sys_error<*> IOSTANDARD = LVCMOS33; +NET sys_error<*> DRIVE = 2; +NET sys_error<*> TIG; + +//////////////////////////////////////////////////////////////////////////// +// RS-232 +//////////////////////////////////////////////////////////////////////////// +NET sys_rx LOC = W2; +#NET sys_rx IOSTANDARD = LVCMOS33; +NET sys_rx TIG; +NET "sys_tx" LOC = "W1"; +#NET sys_tx IOSTANDARD = LVCMOS33; +NET "sys_tx" TIG; + +//////////////////////////////////////////////////////////////////////////// +// Buttons, LEDs, and DIP Switches +//////////////////////////////////////////////////////////////////////////// +# GPLED 0-3 +NET "sys_led<0>" LOC = "G5"; #GPLED0 +NET "sys_led<1>" LOC = "G6"; #GPLED1 +NET "sys_led<2>" LOC = "A11"; #GPLED2 +NET "sys_led<3>" LOC = "A12"; #GPLED3 +# North-East-South-West-Center LEDs +NET "sys_led<4>" LOC = "F9"; # W LED +NET "sys_led<5>" LOC = "E2"; # N LED +NET "sys_led<6>" LOC = "E10"; # E LED +NET "sys_led<7>" LOC = "A5"; # S LED +NET "sys_led<8>" LOC = "C6"; # C LED +NET "sys_led<*>" TIG; +NET "sys_led<*>" SLEW = SLOW; +NET "sys_led<*>" DRIVE = 2; +#NET "sys_led<*>" IOSTANDARD = LVCMOS33; +# North-East-South-West-Center Buttons +NET "sys_btn<0>" LOC = "E9"; # W Button +NET "sys_btn<1>" LOC = "E7"; # N Button +NET "sys_btn<2>" LOC = "F10"; # E Button +NET "sys_btn<3>" LOC = "A6"; # S Button +NET "sys_btn<4>" LOC = "B6"; # C Button +NET "sys_btn<*>" TIG; +NET "sys_btn<*>" PULLDOWN; +#NET "sys_btn<*>" IOSTANDARD = LVCMOS33; +# Dip Switches 1-8 +NET "sys_dip<7>" LOC = "U24"; # DIP SW 8 +NET "sys_dip<6>" LOC = "U25"; # DIP SW 7 +NET "sys_dip<5>" LOC = "V23"; # DIP SW 6 +NET "sys_dip<4>" LOC = "U23"; # DIP SW 5 +NET "sys_dip<3>" LOC = "U26"; # DIP SW 4 +NET "sys_dip<2>" LOC = "T26"; # DIP SW 3 +NET "sys_dip<1>" LOC = "R19"; # DIP SW 2 +NET "sys_dip<0>" LOC = "R20"; # DIP SW 1 +NET "sys_dip<*>" PULLDOWN; +#NET "sys_dip<*>" IOSTANDARD = LVCMOS33; +NET "sys_dip<*>" TIG; +//////////////////////////////////////////////////////////////////////////// +// LCD +//////////////////////////////////////////////////////////////////////////// +NET sys_lcd_e LOC = AE13; # LCD_E +#NET sys_lcd_e IOSTANDARD = LVCMOS33; +NET sys_lcd_e SLEW = SLOW; +NET sys_lcd_e DRIVE = 2; +NET sys_lcd_e TIG; +NET sys_lcd_rs LOC = AC17; # LCD_RS +#NET sys_lcd_rs IOSTANDARD = LVCMOS33; +NET sys_lcd_rs SLEW = SLOW; +NET sys_lcd_rs DRIVE = 2; +NET sys_lcd_rs TIG; +NET sys_lcd_rw LOC = AB17; # LCD_RW +#NET sys_lcd_rw IOSTANDARD = LVCMOS33; +NET sys_lcd_rw SLEW = SLOW; +NET sys_lcd_rw DRIVE = 2; +NET sys_lcd_rw TIG; +NET sys_lcd_d<3> LOC = AF12; # LCD_DB7 +NET sys_lcd_d<2> LOC = AE12; # LCD_DB6 +NET sys_lcd_d<1> LOC = AC10; # LCD_DB5 +NET sys_lcd_d<0> LOC = AB10; # LCD_DB4 +#NET sys_lcd_d<*> IOSTANDARD = LVCMOS33; +NET sys_lcd_d<*> SLEW = SLOW; +NET sys_lcd_d<*> DRIVE = 2; +NET sys_lcd_d<*> PULLDOWN; +NET sys_lcd_d<*> TIG; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for DDR Controllers +#------------------------------------------------------------------------------ + +NET sys_sdr_a_q<0> LOC = C26; # DDR_A0 +NET sys_sdr_a_q<1> LOC = E17; # DDR_A1 +NET sys_sdr_a_q<2> LOC = D18; # DDR_A2 +NET sys_sdr_a_q<3> LOC = C19; # DDR_A3 +NET sys_sdr_a_q<4> LOC = F17; # DDR_A4 +NET sys_sdr_a_q<5> LOC = B18; # DDR_A5 +NET sys_sdr_a_q<6> LOC = B20; # DDR_A6 +NET sys_sdr_a_q<7> LOC = C20; # DDR_A7 +NET sys_sdr_a_q<8> LOC = D20; # DDR_A8 +NET sys_sdr_a_q<9> LOC = C21; # DDR_A9 +NET sys_sdr_a_q<10> LOC = A18; # DDR_A10 +NET sys_sdr_a_q<11> LOC = B21; # DDR_A11 +NET sys_sdr_a_q<12> LOC = A24; # DDR_A12 +NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0 +NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1 +NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N +NET sys_sdr_cke_q LOC = G22; # DDR_CKE +NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N +NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N +NET sys_sdr_we_qn LOC = A23; # DDR_WE_N + +NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P +NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) +NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N + +NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0 +NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1 +NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2 +NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3 + +NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0 +NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1 +NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2 +NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3 + +NET sys_sdr_data<0> LOC = H20; # DDR_D0 +NET sys_sdr_data<1> LOC = E23; # DDR_D1 +NET sys_sdr_data<2> LOC = H26; # DDR_D2 +NET sys_sdr_data<3> LOC = H22; # DDR_D3 +NET sys_sdr_data<4> LOC = E25; # DDR_D4 +NET sys_sdr_data<5> LOC = E26; # DDR_D5 +NET sys_sdr_data<6> LOC = F26; # DDR_D6 +NET sys_sdr_data<7> LOC = E24; # DDR_D7 +NET sys_sdr_data<8> LOC = E20; # DDR_D8 +NET sys_sdr_data<9> LOC = A22; # DDR_D9 +NET sys_sdr_data<10> LOC = C23; # DDR_D10 +NET sys_sdr_data<11> LOC = C24; # DDR_D11 +NET sys_sdr_data<12> LOC = A20; # DDR_D12 +NET sys_sdr_data<13> LOC = A21; # DDR_D13 +NET sys_sdr_data<14> LOC = D24; # DDR_D14 +NET sys_sdr_data<15> LOC = E18; # DDR_D15 +NET sys_sdr_data<16> LOC = F18; # DDR_D16 +NET sys_sdr_data<17> LOC = A19; # DDR_D17 +NET sys_sdr_data<18> LOC = F19; # DDR_D18 +NET sys_sdr_data<19> LOC = B23; # DDR_D19 +NET sys_sdr_data<20> LOC = E21; # DDR_D20 +NET sys_sdr_data<21> LOC = D22; # DDR_D21 +NET sys_sdr_data<22> LOC = D23; # DDR_D22 +NET sys_sdr_data<23> LOC = B24; # DDR_D23 +NET sys_sdr_data<24> LOC = E22; # DDR_D24 +NET sys_sdr_data<25> LOC = F20; # DDR_D25 +NET sys_sdr_data<26> LOC = H23; # DDR_D26 +NET sys_sdr_data<27> LOC = G25; # DDR_D27 +NET sys_sdr_data<28> LOC = G26; # DDR_D28 +NET sys_sdr_data<29> LOC = H25; # DDR_D29 +NET sys_sdr_data<30> LOC = H24; # DDR_D30 +NET sys_sdr_data<31> LOC = H21; # DDR_D31 + +NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I; +NET sys_sdr_a_q<*> FAST; + +NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I; +NET sys_sdr_ba_q<*> FAST; + +NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_cas_qn FAST; + +NET sys_sdr_cke_q IOSTANDARD = SSTL2_I; +NET sys_sdr_cke_q FAST; + +NET sys_sdr_clk_p IOSTANDARD = SSTL2_I; +NET sys_sdr_clk_p FAST; +NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25; +NET sys_sdr_clk_fb IOBDELAY = NONE; +NET sys_sdr_clk_n IOSTANDARD = SSTL2_I; +NET sys_sdr_clk_n FAST; + +NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_cas_qn FAST; + +NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_cs_qn FAST; + +NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_ras_qn FAST; + +NET sys_sdr_we_qn IOSTANDARD = SSTL2_I; +NET sys_sdr_we_qn FAST; + +NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II; +NET sys_sdr_dqs_q<*> IOBDELAY = NONE; +NET sys_sdr_dqs_q<*> FAST; + +NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II; +NET sys_sdr_dm_q<*> IOBDELAY = NONE; +NET sys_sdr_dm_q<*> FAST; + +NET sys_sdr_data<*> IOSTANDARD = SSTL2_II; +NET sys_sdr_data<*> IOBDELAY = NONE; +NET sys_sdr_data<*> FAST; + +#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n"; + + +# Timing Constraint for DDR Feedback Clock +NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p; + diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo new file mode 100644 index 0000000..0aab37b --- /dev/null +++ b/projects/mips_sys/sim/tb_mips_sys.fdo @@ -0,0 +1,70 @@ +## NOTE: Do not edit this file. +## +vlib work +# Configs +vcom -explicit -93 "../src/sdram_config_sim.vhd" + +# Packages +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd" +vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd" +vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd" + +# RAMs +vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd" +vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd" +vcom -explicit -93 "../../../lib/misc/dpram_1w1r_dist.vhd" + +# CPU +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/dcache.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/icache.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bui.vhd" +vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd" +vcom -explicit -93 "../src/ram_sim.vhd" +vcom -explicit -93 "../src/bootloader.ROM.vhd" + +# UART +vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd" +vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd" +vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd" +vcom -explicit -93 "../../../lib/uart/uart_rx.vhd" +vcom -explicit -93 "../../../lib/uart/uart_tx.vhd" + +# LCD +vcom -explicit -93 "../../../lib/misc/lcd_port.vhd" + +# FIFOS +vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd" +vcom -explicit -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd" + +# SDRAM +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd" + +# Top and TB +vcom -explicit -93 "../src/mips_sys_sim.vhd" +vcom -explicit -93 "../src/tb_mips_sys.vhd" + +vsim -t 1ps -lib work tb_mips_sys +do {tb_mips_sys.wdo} +view wave +view structure +view signals +run 5ms + \ No newline at end of file diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo new file mode 100644 index 0000000..bd8db46 --- /dev/null +++ b/projects/mips_sys/sim/tb_mips_sys.wdo @@ -0,0 +1,243 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider UUT +add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in +add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in +add wave -noupdate -format Literal /tb_mips_sys/dip +add wave -noupdate -format Literal /tb_mips_sys/btn +add wave -noupdate -format Literal /tb_mips_sys/led +add wave -noupdate -format Logic /tb_mips_sys/sys_rx +add wave -noupdate -format Logic /tb_mips_sys/sys_tx +add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d +add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e +add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs +add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw +add wave -noupdate -format Logic /tb_mips_sys/refresh +add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p +add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n +add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q +add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn +add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn +add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn +add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn +add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q +add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q +add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q +add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_a_q +add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_data +add wave -noupdate -format Literal /tb_mips_sys/sys_error +add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb +add wave -noupdate -divider {MIPS TOP} +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/events +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_wait +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/badvaddr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_code +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_save +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_rest +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir_valid +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/din +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we +add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in +add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags_reg_we +add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic -label .exc_commit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_commit +add wave -noupdate -format Logic -label .exc_pending /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_pending +add wave -noupdate -format Logic -label .exc_exit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_exit +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy1 +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy2 +add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/rst +add wave -noupdate -divider BUI +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_req +add wave -noupdate -format Logic /tb_mips_sys/uut/mem_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_addr +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_req +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dmem_ack +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dmem_valid +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_rdy +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s +add wave -noupdate -divider {Memory Bus} +add wave -noupdate -format Logic /tb_mips_sys/uut/mem_en +add wave -noupdate -format Logic /tb_mips_sys/uut/mem_re +add wave -noupdate -format Logic /tb_mips_sys/uut/mem_re_r +add wave -noupdate -format Literal /tb_mips_sys/uut/mem_we_r +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_re +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_we +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_ce +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_dout +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_valid +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_rdy +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/busy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/en +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/r_wn +add wave -noupdate -divider {CPU DMEM} +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/contention +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_dout +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr +add wave -noupdate -divider {CPU IMEM} +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_rdy +add wave -noupdate -divider {User ROM} +add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_clk +add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_addr +add wave -noupdate -divider UUT +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc +add wave -noupdate -format Logic /tb_mips_sys/uut/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_buf_in +add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_busy_q +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_udata_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_udata_out_q +add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_udata_req_wr +add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_udata_vld_q +add wave -noupdate -format Literal /tb_mips_sys/uut/st +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q +add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q +add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn +add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q +add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb +add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n +add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p +add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data +add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q +add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q +add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn +add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn +add wave -noupdate -format Literal /tb_mips_sys/uut/tick_usec +add wave -noupdate -divider I-Cache +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_wait +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc +add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_dout +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_busy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss +add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram +add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_req +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_gnt +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_din +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_valid +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_rdy +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/ram_index_count +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write +add wave -noupdate -divider D-Cache +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_r_wn +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_req +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_gnt +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_din +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_valid +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_rdy +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_read_miss +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_write_miss +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_busy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_reg_en +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/was_miss +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/data_write +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_dout +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_data_reg +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we_reg +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_force_we +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_was_write +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_din +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/duncached_access +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {1165623518 ps} 0} +configure wave -namecolwidth 218 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 100 +configure wave -griddelta 40 +configure wave -timeline 1 +update +WaveRestoreZoom {1165509887 ps} {1165713125 ps} diff --git a/projects/mips_sys/src/bootloader.ROM.vhd b/projects/mips_sys/src/bootloader.ROM.vhd new file mode 100644 index 0000000..649d39c --- /dev/null +++ b/projects/mips_sys/src/bootloader.ROM.vhd @@ -0,0 +1,2082 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +ENTITY rom IS + Port + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + addr : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); +END rom; + +ARCHITECTURE data OF rom IS + + subtype word_t is unsigned(31 downto 0); + type word_array_t is array (0 to 2047) of word_t; + constant word_array : word_array_t := + ( + + X"3C1A1040", -- 00000000 + X"375A000C", -- 00000004 + X"409A6000", -- 00000008 + X"241A0000", -- 0000000C + X"409A6800", -- 00000010 + X"401A7800", -- 00000014 + X"00000000", -- 00000018 + X"409AF800", -- 0000001C + X"3C1ABFC0", -- 00000020 + X"275A01C4", -- 00000024 + X"03400008", -- 00000028 + X"00000000", -- 0000002C + X"00000000", -- 00000030 + X"00000000", -- 00000034 + X"00000000", -- 00000038 + X"00000000", -- 0000003C + X"00000000", -- 00000040 + X"00000000", -- 00000044 + X"00000000", -- 00000048 + X"00000000", -- 0000004C + X"00000000", -- 00000050 + X"00000000", -- 00000054 + X"00000000", -- 00000058 + X"00000000", -- 0000005C + X"00000000", -- 00000060 + X"00000000", -- 00000064 + X"00000000", -- 00000068 + X"00000000", -- 0000006C + X"00000000", -- 00000070 + X"00000000", -- 00000074 + X"00000000", -- 00000078 + X"00000000", -- 0000007C + X"00000000", -- 00000080 + X"00000000", -- 00000084 + X"00000000", -- 00000088 + X"00000000", -- 0000008C + X"00000000", -- 00000090 + X"00000000", -- 00000094 + X"00000000", -- 00000098 + X"00000000", -- 0000009C + X"00000000", -- 000000A0 + X"00000000", -- 000000A4 + X"00000000", -- 000000A8 + X"00000000", -- 000000AC + X"00000000", -- 000000B0 + X"00000000", -- 000000B4 + X"00000000", -- 000000B8 + X"00000000", -- 000000BC + X"00000000", -- 000000C0 + X"00000000", -- 000000C4 + X"00000000", -- 000000C8 + X"00000000", -- 000000CC + X"00000000", -- 000000D0 + X"00000000", -- 000000D4 + X"00000000", -- 000000D8 + X"00000000", -- 000000DC + X"00000000", -- 000000E0 + X"00000000", -- 000000E4 + X"00000000", -- 000000E8 + X"00000000", -- 000000EC + X"00000000", -- 000000F0 + X"00000000", -- 000000F4 + X"00000000", -- 000000F8 + X"00000000", -- 000000FC + X"00000000", -- 00000100 + X"00000000", -- 00000104 + X"00000000", -- 00000108 + X"00000000", -- 0000010C + X"00000000", -- 00000110 + X"00000000", -- 00000114 + X"00000000", -- 00000118 + X"00000000", -- 0000011C + X"00000000", -- 00000120 + X"00000000", -- 00000124 + X"00000000", -- 00000128 + X"00000000", -- 0000012C + X"00000000", -- 00000130 + X"00000000", -- 00000134 + X"00000000", -- 00000138 + X"00000000", -- 0000013C + X"00000000", -- 00000140 + X"00000000", -- 00000144 + X"00000000", -- 00000148 + X"00000000", -- 0000014C + X"00000000", -- 00000150 + X"00000000", -- 00000154 + X"00000000", -- 00000158 + X"00000000", -- 0000015C + X"00000000", -- 00000160 + X"00000000", -- 00000164 + X"00000000", -- 00000168 + X"00000000", -- 0000016C + X"00000000", -- 00000170 + X"00000000", -- 00000174 + X"00000000", -- 00000178 + X"00000000", -- 0000017C + X"401A6800", -- 00000180 + X"3C1BA000", -- 00000184 + X"277B0000", -- 00000188 + X"001AD082", -- 0000018C + X"335A000F", -- 00000190 + X"035BD025", -- 00000194 + X"AF7A0000", -- 00000198 + X"401A6800", -- 0000019C + X"00000000", -- 000001A0 + X"001AD202", -- 000001A4 + X"335A00FF", -- 000001A8 + X"1740FFFB", -- 000001AC + X"00000000", -- 000001B0 + X"401A7000", -- 000001B4 + X"00000000", -- 000001B8 + X"03400008", -- 000001BC + X"42000010", -- 000001C0 + X"3C1AA000", -- 000001C4 + X"275A0009", -- 000001C8 + X"241B000D", -- 000001CC + X"A35B0000", -- 000001D0 + X"3C1DBFD0", -- 000001D4 + X"27BDFFF0", -- 000001D8 + X"241A0005", -- 000001DC + X"1340009F", -- 000001E0 + X"241AFFFB", -- 000001E4 + X"1340009D", -- 000001E8 + X"241A0000", -- 000001EC + X"13400003", -- 000001F0 + X"00000000", -- 000001F4 + X"0BF00118", -- 000001F8 + X"00000000", -- 000001FC + X"241A0005", -- 00000200 + X"241B0006", -- 00000204 + X"135B0095", -- 00000208 + X"241AFFFB", -- 0000020C + X"135B0093", -- 00000210 + X"241A0000", -- 00000214 + X"135B0091", -- 00000218 + X"241A0006", -- 0000021C + X"135B0003", -- 00000220 + X"00000000", -- 00000224 + X"0BF00118", -- 00000228 + X"00000000", -- 0000022C + X"241AFFFB", -- 00000230 + X"0741008A", -- 00000234 + X"241A0005", -- 00000238 + X"07410002", -- 0000023C + X"00000000", -- 00000240 + X"0BF00118", -- 00000244 + X"241A0000", -- 00000248 + X"07410002", -- 0000024C + X"00000000", -- 00000250 + X"0BF00118", -- 00000254 + X"241AFFFB", -- 00000258 + X"1F400080", -- 0000025C + X"241A0000", -- 00000260 + X"1F40007E", -- 00000264 + X"241A0005", -- 00000268 + X"1F400002", -- 0000026C + X"00000000", -- 00000270 + X"0BF00118", -- 00000274 + X"241A0005", -- 00000278 + X"1B400078", -- 0000027C + X"241A0000", -- 00000280 + X"1B400002", -- 00000284 + X"00000000", -- 00000288 + X"0BF00118", -- 0000028C + X"241AFFFB", -- 00000290 + X"1B400002", -- 00000294 + X"00000000", -- 00000298 + X"0BF00118", -- 0000029C + X"241A0005", -- 000002A0 + X"0740006E", -- 000002A4 + X"241A0000", -- 000002A8 + X"0740006C", -- 000002AC + X"241AFFFB", -- 000002B0 + X"07400002", -- 000002B4 + X"00000000", -- 000002B8 + X"0BF00118", -- 000002BC + X"241A0005", -- 000002C0 + X"241B0006", -- 000002C4 + X"175B0002", -- 000002C8 + X"00000000", -- 000002CC + X"0BF00118", -- 000002D0 + X"241AFFFB", -- 000002D4 + X"175B0002", -- 000002D8 + X"00000000", -- 000002DC + X"0BF00118", -- 000002E0 + X"241AFFFA", -- 000002E4 + X"175B0002", -- 000002E8 + X"00000000", -- 000002EC + X"0BF00118", -- 000002F0 + X"241A0000", -- 000002F4 + X"175B0002", -- 000002F8 + X"00000000", -- 000002FC + X"0BF00118", -- 00000300 + X"241A0006", -- 00000304 + X"175B0055", -- 00000308 + X"241A0005", -- 0000030C + X"17400002", -- 00000310 + X"00000000", -- 00000314 + X"0BF00118", -- 00000318 + X"241AFFFB", -- 0000031C + X"17400002", -- 00000320 + X"00000000", -- 00000324 + X"0BF00118", -- 00000328 + X"241A0000", -- 0000032C + X"1740004B", -- 00000330 + X"241B0005", -- 00000334 + X"2F7A0006", -- 00000338 + X"2F7AFFFA", -- 0000033C + X"241BFFFB", -- 00000340 + X"2F7A0006", -- 00000344 + X"2F7AFFFA", -- 00000348 + X"241B0006", -- 0000034C + X"2F7A0005", -- 00000350 + X"2F7AFFFB", -- 00000354 + X"241BFFFA", -- 00000358 + X"2F7A0005", -- 0000035C + X"2F7AFFFB", -- 00000360 + X"241B0005", -- 00000364 + X"2B7A0006", -- 00000368 + X"2B7AFFFA", -- 0000036C + X"241BFFFB", -- 00000370 + X"2B7A0006", -- 00000374 + X"2B7AFFFA", -- 00000378 + X"241B0006", -- 0000037C + X"2B7A0005", -- 00000380 + X"2B7AFFFB", -- 00000384 + X"241BFFFA", -- 00000388 + X"2B7A0005", -- 0000038C + X"2B7AFFFB", -- 00000390 + X"241A0005", -- 00000394 + X"241B0006", -- 00000398 + X"035BD02B", -- 0000039C + X"241A0005", -- 000003A0 + X"241BFFFA", -- 000003A4 + X"035BD02B", -- 000003A8 + X"241AFFFB", -- 000003AC + X"241B0006", -- 000003B0 + X"035BD02B", -- 000003B4 + X"241AFFFB", -- 000003B8 + X"241BFFFA", -- 000003BC + X"035BD02B", -- 000003C0 + X"241A0006", -- 000003C4 + X"241B0005", -- 000003C8 + X"035BD02B", -- 000003CC + X"241A0006", -- 000003D0 + X"241BFFFB", -- 000003D4 + X"035BD02B", -- 000003D8 + X"241AFFFA", -- 000003DC + X"241B0005", -- 000003E0 + X"035BD02B", -- 000003E4 + X"241AFFFA", -- 000003E8 + X"241BFFFB", -- 000003EC + X"035BD02B", -- 000003F0 + X"241A0005", -- 000003F4 + X"241B0006", -- 000003F8 + X"035BD02A", -- 000003FC + X"241A0005", -- 00000400 + X"241BFFFA", -- 00000404 + X"035BD02A", -- 00000408 + X"241AFFFB", -- 0000040C + X"241B0006", -- 00000410 + X"035BD02A", -- 00000414 + X"241AFFFB", -- 00000418 + X"241BFFFA", -- 0000041C + X"035BD02A", -- 00000420 + X"241A0006", -- 00000424 + X"241B0005", -- 00000428 + X"035BD02A", -- 0000042C + X"241A0006", -- 00000430 + X"241BFFFB", -- 00000434 + X"035BD02A", -- 00000438 + X"241AFFFA", -- 0000043C + X"241B0005", -- 00000440 + X"035BD02A", -- 00000444 + X"241AFFFA", -- 00000448 + X"241BFFFB", -- 0000044C + X"035BD02A", -- 00000450 + X"3C1ABFC0", -- 00000454 + X"275A0F4C", -- 00000458 + X"0340F809", -- 0000045C + X"00000000", -- 00000460 + X"0BF00118", -- 00000464 + X"00000000", -- 00000468 + X"27BDFFF0", -- 0000046C + X"AFBE000C", -- 00000470 + X"03A0F021", -- 00000474 + X"40026000", -- 00000478 + X"03C0E821", -- 0000047C + X"8FBE000C", -- 00000480 + X"03E00008", -- 00000484 + X"27BD0010", -- 00000488 + X"27BDFFF0", -- 0000048C + X"AFBE000C", -- 00000490 + X"03A0F021", -- 00000494 + X"40027800", -- 00000498 + X"03C0E821", -- 0000049C + X"8FBE000C", -- 000004A0 + X"03E00008", -- 000004A4 + X"27BD0010", -- 000004A8 + X"27BDFFF0", -- 000004AC + X"AFBE000C", -- 000004B0 + X"03A0F021", -- 000004B4 + X"3C02A000", -- 000004B8 + X"34420008", -- 000004BC + X"AFC20004", -- 000004C0 + X"3C02A000", -- 000004C4 + X"34420004", -- 000004C8 + X"AFC20000", -- 000004CC + X"8FC20004", -- 000004D0 + X"00000000", -- 000004D4 + X"90420000", -- 000004D8 + X"00000000", -- 000004DC + X"00021600", -- 000004E0 + X"00021603", -- 000004E4 + X"304200FF", -- 000004E8 + X"30420010", -- 000004EC + X"1040FFF7", -- 000004F0 + X"00000000", -- 000004F4 + X"8FC20000", -- 000004F8 + X"00000000", -- 000004FC + X"90420000", -- 00000500 + X"00000000", -- 00000504 + X"00021600", -- 00000508 + X"00021603", -- 0000050C + X"03C0E821", -- 00000510 + X"8FBE000C", -- 00000514 + X"27BD0010", -- 00000518 + X"03E00008", -- 0000051C + X"00000000", -- 00000520 + X"27BDFFE8", -- 00000524 + X"AFBE0014", -- 00000528 + X"03A0F021", -- 0000052C + X"00801021", -- 00000530 + X"A3C20008", -- 00000534 + X"3C02A000", -- 00000538 + X"34420008", -- 0000053C + X"AFC20004", -- 00000540 + X"3C02A000", -- 00000544 + X"34420004", -- 00000548 + X"AFC20000", -- 0000054C + X"8FC20004", -- 00000550 + X"00000000", -- 00000554 + X"90420000", -- 00000558 + X"00000000", -- 0000055C + X"00021600", -- 00000560 + X"00021603", -- 00000564 + X"304200FF", -- 00000568 + X"30420002", -- 0000056C + X"1440FFF7", -- 00000570 + X"00000000", -- 00000574 + X"8FC30000", -- 00000578 + X"93C20008", -- 0000057C + X"00000000", -- 00000580 + X"A0620000", -- 00000584 + X"03C0E821", -- 00000588 + X"8FBE0014", -- 0000058C + X"27BD0018", -- 00000590 + X"03E00008", -- 00000594 + X"00000000", -- 00000598 + X"27BDFFF0", -- 0000059C + X"AFBF000C", -- 000005A0 + X"AFBE0008", -- 000005A4 + X"03A0F021", -- 000005A8 + X"00801021", -- 000005AC + X"A3C20000", -- 000005B0 + X"83C30000", -- 000005B4 + X"2402000A", -- 000005B8 + X"1462000B", -- 000005BC + X"00000000", -- 000005C0 + X"2404000D", -- 000005C4 + X"0FF00149", -- 000005C8 + X"00000000", -- 000005CC + X"83C20000", -- 000005D0 + X"00000000", -- 000005D4 + X"00402021", -- 000005D8 + X"0FF00149", -- 000005DC + X"00000000", -- 000005E0 + X"0BF00180", -- 000005E4 + X"00000000", -- 000005E8 + X"83C20000", -- 000005EC + X"00000000", -- 000005F0 + X"00402021", -- 000005F4 + X"0FF00149", -- 000005F8 + X"00000000", -- 000005FC + X"03C0E821", -- 00000600 + X"8FBF000C", -- 00000604 + X"8FBE0008", -- 00000608 + X"27BD0010", -- 0000060C + X"03E00008", -- 00000610 + X"00000000", -- 00000614 + X"27BDFFE8", -- 00000618 + X"AFBF0014", -- 0000061C + X"AFBE0010", -- 00000620 + X"03A0F021", -- 00000624 + X"AFC40008", -- 00000628 + X"8FC20008", -- 0000062C + X"00000000", -- 00000630 + X"AFC20000", -- 00000634 + X"0BF0019C", -- 00000638 + X"00000000", -- 0000063C + X"8FC20008", -- 00000640 + X"00000000", -- 00000644 + X"80420000", -- 00000648 + X"00000000", -- 0000064C + X"00401821", -- 00000650 + X"8FC20008", -- 00000654 + X"00000000", -- 00000658 + X"24420001", -- 0000065C + X"AFC20008", -- 00000660 + X"00602021", -- 00000664 + X"0FF00167", -- 00000668 + X"00000000", -- 0000066C + X"8FC20008", -- 00000670 + X"00000000", -- 00000674 + X"80420000", -- 00000678 + X"00000000", -- 0000067C + X"1440FFEF", -- 00000680 + X"00000000", -- 00000684 + X"8FC30008", -- 00000688 + X"8FC20000", -- 0000068C + X"00000000", -- 00000690 + X"00621023", -- 00000694 + X"03C0E821", -- 00000698 + X"8FBF0014", -- 0000069C + X"8FBE0010", -- 000006A0 + X"27BD0018", -- 000006A4 + X"03E00008", -- 000006A8 + X"00000000", -- 000006AC + X"27BDFFE8", -- 000006B0 + X"AFBF0014", -- 000006B4 + X"AFBE0010", -- 000006B8 + X"03A0F021", -- 000006BC + X"00801021", -- 000006C0 + X"A3C20008", -- 000006C4 + X"AFC00004", -- 000006C8 + X"0BF001D5", -- 000006CC + X"00000000", -- 000006D0 + X"93C20008", -- 000006D4 + X"00000000", -- 000006D8 + X"00021102", -- 000006DC + X"A3C20000", -- 000006E0 + X"83C20008", -- 000006E4 + X"00000000", -- 000006E8 + X"00021100", -- 000006EC + X"A3C20008", -- 000006F0 + X"93C20000", -- 000006F4 + X"00000000", -- 000006F8 + X"2C42000A", -- 000006FC + X"10400007", -- 00000700 + X"00000000", -- 00000704 + X"93C20000", -- 00000708 + X"00000000", -- 0000070C + X"24420030", -- 00000710 + X"A3C20001", -- 00000714 + X"0BF001CC", -- 00000718 + X"00000000", -- 0000071C + X"93C20000", -- 00000720 + X"00000000", -- 00000724 + X"24420037", -- 00000728 + X"A3C20001", -- 0000072C + X"83C20001", -- 00000730 + X"00000000", -- 00000734 + X"00402021", -- 00000738 + X"0FF00149", -- 0000073C + X"00000000", -- 00000740 + X"8FC20004", -- 00000744 + X"00000000", -- 00000748 + X"24420001", -- 0000074C + X"AFC20004", -- 00000750 + X"8FC20004", -- 00000754 + X"00000000", -- 00000758 + X"28420002", -- 0000075C + X"1440FFDC", -- 00000760 + X"00000000", -- 00000764 + X"03C0E821", -- 00000768 + X"8FBF0014", -- 0000076C + X"8FBE0010", -- 00000770 + X"27BD0018", -- 00000774 + X"03E00008", -- 00000778 + X"00000000", -- 0000077C + X"27BDFFE8", -- 00000780 + X"AFBF0014", -- 00000784 + X"AFBE0010", -- 00000788 + X"03A0F021", -- 0000078C + X"AFC40008", -- 00000790 + X"AFC00004", -- 00000794 + X"0BF001F9", -- 00000798 + X"00000000", -- 0000079C + X"8FC20008", -- 000007A0 + X"00000000", -- 000007A4 + X"00021603", -- 000007A8 + X"A3C20001", -- 000007AC + X"83C20001", -- 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00001B58 + X"00000000", -- 00001B5C + X"00000000", -- 00001B60 + X"00000000", -- 00001B64 + X"00000000", -- 00001B68 + X"00000000", -- 00001B6C + X"00000000", -- 00001B70 + X"00000000", -- 00001B74 + X"00000000", -- 00001B78 + X"00000000", -- 00001B7C + X"00000000", -- 00001B80 + X"00000000", -- 00001B84 + X"00000000", -- 00001B88 + X"00000000", -- 00001B8C + X"00000000", -- 00001B90 + X"00000000", -- 00001B94 + X"00000000", -- 00001B98 + X"00000000", -- 00001B9C + X"00000000", -- 00001BA0 + X"00000000", -- 00001BA4 + X"00000000", -- 00001BA8 + X"00000000", -- 00001BAC + X"00000000", -- 00001BB0 + X"00000000", -- 00001BB4 + X"00000000", -- 00001BB8 + X"00000000", -- 00001BBC + X"00000000", -- 00001BC0 + X"00000000", -- 00001BC4 + X"00000000", -- 00001BC8 + X"00000000", -- 00001BCC + X"00000000", -- 00001BD0 + X"00000000", -- 00001BD4 + X"00000000", -- 00001BD8 + X"00000000", -- 00001BDC + X"00000000", -- 00001BE0 + X"00000000", -- 00001BE4 + X"00000000", -- 00001BE8 + X"00000000", -- 00001BEC + X"00000000", -- 00001BF0 + X"00000000", -- 00001BF4 + X"00000000", -- 00001BF8 + X"00000000", -- 00001BFC + X"00000000", -- 00001C00 + X"00000000", -- 00001C04 + X"00000000", -- 00001C08 + X"00000000", -- 00001C0C + X"00000000", -- 00001C10 + X"00000000", -- 00001C14 + X"00000000", -- 00001C18 + X"00000000", -- 00001C1C + X"00000000", -- 00001C20 + X"00000000", -- 00001C24 + X"00000000", -- 00001C28 + X"00000000", -- 00001C2C + X"00000000", -- 00001C30 + X"00000000", -- 00001C34 + X"00000000", -- 00001C38 + X"00000000", -- 00001C3C + X"00000000", -- 00001C40 + X"00000000", -- 00001C44 + X"00000000", -- 00001C48 + X"00000000", -- 00001C4C + X"00000000", -- 00001C50 + X"00000000", -- 00001C54 + X"00000000", -- 00001C58 + X"00000000", -- 00001C5C + X"00000000", -- 00001C60 + X"00000000", -- 00001C64 + X"00000000", -- 00001C68 + X"00000000", -- 00001C6C + X"00000000", -- 00001C70 + X"00000000", -- 00001C74 + X"00000000", -- 00001C78 + X"00000000", -- 00001C7C + X"00000000", -- 00001C80 + X"00000000", -- 00001C84 + X"00000000", -- 00001C88 + X"00000000", -- 00001C8C + X"00000000", -- 00001C90 + X"00000000", -- 00001C94 + X"00000000", -- 00001C98 + X"00000000", -- 00001C9C + X"00000000", -- 00001CA0 + X"00000000", -- 00001CA4 + X"00000000", -- 00001CA8 + X"00000000", -- 00001CAC + X"00000000", -- 00001CB0 + X"00000000", -- 00001CB4 + X"00000000", -- 00001CB8 + X"00000000", -- 00001CBC + X"00000000", -- 00001CC0 + X"00000000", -- 00001CC4 + X"00000000", -- 00001CC8 + X"00000000", -- 00001CCC + X"00000000", -- 00001CD0 + X"00000000", -- 00001CD4 + X"00000000", -- 00001CD8 + X"00000000", -- 00001CDC + X"00000000", -- 00001CE0 + X"00000000", -- 00001CE4 + X"00000000", -- 00001CE8 + X"00000000", -- 00001CEC + X"00000000", -- 00001CF0 + X"00000000", -- 00001CF4 + X"00000000", -- 00001CF8 + X"00000000", -- 00001CFC + X"00000000", -- 00001D00 + X"00000000", -- 00001D04 + X"00000000", -- 00001D08 + X"00000000", -- 00001D0C + X"00000000", -- 00001D10 + X"00000000", -- 00001D14 + X"00000000", -- 00001D18 + X"00000000", -- 00001D1C + X"00000000", -- 00001D20 + X"00000000", -- 00001D24 + X"00000000", -- 00001D28 + X"00000000", -- 00001D2C + X"00000000", -- 00001D30 + X"00000000", -- 00001D34 + X"00000000", -- 00001D38 + X"00000000", -- 00001D3C + X"00000000", -- 00001D40 + X"00000000", -- 00001D44 + X"00000000", -- 00001D48 + X"00000000", -- 00001D4C + X"00000000", -- 00001D50 + X"00000000", -- 00001D54 + X"00000000", -- 00001D58 + X"00000000", -- 00001D5C + X"00000000", -- 00001D60 + X"00000000", -- 00001D64 + X"00000000", -- 00001D68 + X"00000000", -- 00001D6C + X"00000000", -- 00001D70 + X"00000000", -- 00001D74 + X"00000000", -- 00001D78 + X"00000000", -- 00001D7C + X"00000000", -- 00001D80 + X"00000000", -- 00001D84 + X"00000000", -- 00001D88 + X"00000000", -- 00001D8C + X"00000000", -- 00001D90 + X"00000000", -- 00001D94 + X"00000000", -- 00001D98 + X"00000000", -- 00001D9C + X"00000000", -- 00001DA0 + X"00000000", -- 00001DA4 + X"00000000", -- 00001DA8 + X"00000000", -- 00001DAC + X"00000000", -- 00001DB0 + X"00000000", -- 00001DB4 + X"00000000", -- 00001DB8 + X"00000000", -- 00001DBC + X"00000000", -- 00001DC0 + X"00000000", -- 00001DC4 + X"00000000", -- 00001DC8 + X"00000000", -- 00001DCC + X"00000000", -- 00001DD0 + X"00000000", -- 00001DD4 + X"00000000", -- 00001DD8 + X"00000000", -- 00001DDC + X"00000000", -- 00001DE0 + X"00000000", -- 00001DE4 + X"00000000", -- 00001DE8 + X"00000000", -- 00001DEC + X"00000000", -- 00001DF0 + X"00000000", -- 00001DF4 + X"00000000", -- 00001DF8 + X"00000000", -- 00001DFC + X"00000000", -- 00001E00 + X"00000000", -- 00001E04 + X"00000000", -- 00001E08 + X"00000000", -- 00001E0C + X"00000000", -- 00001E10 + X"00000000", -- 00001E14 + X"00000000", -- 00001E18 + X"00000000", -- 00001E1C + X"00000000", -- 00001E20 + X"00000000", -- 00001E24 + X"00000000", -- 00001E28 + X"00000000", -- 00001E2C + X"00000000", -- 00001E30 + X"00000000", -- 00001E34 + X"00000000", -- 00001E38 + X"00000000", -- 00001E3C + X"00000000", -- 00001E40 + X"00000000", -- 00001E44 + X"00000000", -- 00001E48 + X"00000000", -- 00001E4C + X"00000000", -- 00001E50 + X"00000000", -- 00001E54 + X"00000000", -- 00001E58 + X"00000000", -- 00001E5C + X"00000000", -- 00001E60 + X"00000000", -- 00001E64 + X"00000000", -- 00001E68 + X"00000000", -- 00001E6C + X"00000000", -- 00001E70 + X"00000000", -- 00001E74 + X"00000000", -- 00001E78 + X"00000000", -- 00001E7C + X"00000000", -- 00001E80 + X"00000000", -- 00001E84 + X"00000000", -- 00001E88 + X"00000000", -- 00001E8C + X"00000000", -- 00001E90 + X"00000000", -- 00001E94 + X"00000000", -- 00001E98 + X"00000000", -- 00001E9C + X"00000000", -- 00001EA0 + X"00000000", -- 00001EA4 + X"00000000", -- 00001EA8 + X"00000000", -- 00001EAC + X"00000000", -- 00001EB0 + X"00000000", -- 00001EB4 + X"00000000", -- 00001EB8 + X"00000000", -- 00001EBC + X"00000000", -- 00001EC0 + X"00000000", -- 00001EC4 + X"00000000", -- 00001EC8 + X"00000000", -- 00001ECC + X"00000000", -- 00001ED0 + X"00000000", -- 00001ED4 + X"00000000", -- 00001ED8 + X"00000000", -- 00001EDC + X"00000000", -- 00001EE0 + X"00000000", -- 00001EE4 + X"00000000", -- 00001EE8 + X"00000000", -- 00001EEC + X"00000000", -- 00001EF0 + X"00000000", -- 00001EF4 + X"00000000", -- 00001EF8 + X"00000000", -- 00001EFC + X"00000000", -- 00001F00 + X"00000000", -- 00001F04 + X"00000000", -- 00001F08 + X"00000000", -- 00001F0C + X"00000000", -- 00001F10 + X"00000000", -- 00001F14 + X"00000000", -- 00001F18 + X"00000000", -- 00001F1C + X"00000000", -- 00001F20 + X"00000000", -- 00001F24 + X"00000000", -- 00001F28 + X"00000000", -- 00001F2C + X"00000000", -- 00001F30 + X"00000000", -- 00001F34 + X"00000000", -- 00001F38 + X"00000000", -- 00001F3C + X"00000000", -- 00001F40 + X"00000000", -- 00001F44 + X"00000000", -- 00001F48 + X"00000000", -- 00001F4C + X"00000000", -- 00001F50 + X"00000000", -- 00001F54 + X"00000000", -- 00001F58 + X"00000000", -- 00001F5C + X"00000000", -- 00001F60 + X"00000000", -- 00001F64 + X"00000000", -- 00001F68 + X"00000000", -- 00001F6C + X"00000000", -- 00001F70 + X"00000000", -- 00001F74 + X"00000000", -- 00001F78 + X"00000000", -- 00001F7C + X"00000000", -- 00001F80 + X"00000000", -- 00001F84 + X"00000000", -- 00001F88 + X"00000000", -- 00001F8C + X"00000000", -- 00001F90 + X"00000000", -- 00001F94 + X"00000000", -- 00001F98 + X"00000000", -- 00001F9C + X"00000000", -- 00001FA0 + X"00000000", -- 00001FA4 + X"00000000", -- 00001FA8 + X"00000000", -- 00001FAC + X"00000000", -- 00001FB0 + X"00000000", -- 00001FB4 + X"00000000", -- 00001FB8 + X"00000000", -- 00001FBC + X"00000000", -- 00001FC0 + X"00000000", -- 00001FC4 + X"00000000", -- 00001FC8 + X"00000000", -- 00001FCC + X"00000000", -- 00001FD0 + X"00000000", -- 00001FD4 + X"00000000", -- 00001FD8 + X"00000000", -- 00001FDC + X"00000000", -- 00001FE0 + X"00000000", -- 00001FE4 + X"00000000", -- 00001FE8 + X"00000000", -- 00001FEC + X"00000000", -- 00001FF0 + X"00000000", -- 00001FF4 + X"00000000", -- 00001FF8 + X"00000000" -- 00001FFC + ); + +begin + +PROM_READ: + process(clk) + begin + if rising_edge(clk) and ce = '1' then + dout <= word_array(to_integer(addr(12 downto 2))); + end if; + end process; + +end data; diff --git a/projects/mips_sys/src/bootloader.ROM_ld.vhd b/projects/mips_sys/src/bootloader.ROM_ld.vhd new file mode 100644 index 0000000..1703855 --- /dev/null +++ b/projects/mips_sys/src/bootloader.ROM_ld.vhd @@ -0,0 +1,2174 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +ENTITY rom IS + Port + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + addr : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); +END rom; + +ARCHITECTURE data OF rom IS + + subtype word_t is unsigned(31 downto 0); + type word_array_t is array (0 to 2047) of word_t; + signal jtag_ld_clk : STD_LOGIC; + signal jtag_ld_we : STD_LOGIC; + signal jtag_ld_addr : unsigned (15 downto 0); + signal jtag_ld_dout : unsigned (31 downto 0); + signal jtag_ld_din : unsigned (31 downto 0); + signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; + signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; + signal user_regi, user_rego : unsigned (47 downto 0); + + signal word_array : word_array_t := + ( + + X"3C1A1040", -- 00000000 + X"375A000C", -- 00000004 + X"409A6000", -- 00000008 + X"241A0000", -- 0000000C + X"409A6800", -- 00000010 + X"401A7800", -- 00000014 + X"00000000", -- 00000018 + X"409AF800", -- 0000001C + X"3C1ABFC0", -- 00000020 + X"275A01C4", -- 00000024 + X"03400008", -- 00000028 + X"00000000", -- 0000002C + X"00000000", -- 00000030 + X"00000000", -- 00000034 + X"00000000", -- 00000038 + X"00000000", -- 0000003C + X"00000000", -- 00000040 + X"00000000", -- 00000044 + X"00000000", -- 00000048 + X"00000000", -- 0000004C + X"00000000", -- 00000050 + X"00000000", -- 00000054 + X"00000000", -- 00000058 + X"00000000", -- 0000005C + X"00000000", -- 00000060 + X"00000000", -- 00000064 + X"00000000", -- 00000068 + X"00000000", -- 0000006C + X"00000000", -- 00000070 + X"00000000", -- 00000074 + X"00000000", -- 00000078 + X"00000000", -- 0000007C + X"00000000", -- 00000080 + X"00000000", -- 00000084 + X"00000000", -- 00000088 + X"00000000", -- 0000008C + X"00000000", -- 00000090 + X"00000000", -- 00000094 + X"00000000", -- 00000098 + X"00000000", -- 0000009C + X"00000000", -- 000000A0 + X"00000000", -- 000000A4 + X"00000000", -- 000000A8 + X"00000000", -- 000000AC + X"00000000", -- 000000B0 + X"00000000", -- 000000B4 + X"00000000", -- 000000B8 + X"00000000", -- 000000BC + X"00000000", -- 000000C0 + X"00000000", -- 000000C4 + X"00000000", -- 000000C8 + X"00000000", -- 000000CC + X"00000000", -- 000000D0 + X"00000000", -- 000000D4 + X"00000000", -- 000000D8 + X"00000000", -- 000000DC + X"00000000", -- 000000E0 + X"00000000", -- 000000E4 + X"00000000", -- 000000E8 + X"00000000", -- 000000EC + X"00000000", -- 000000F0 + X"00000000", -- 000000F4 + X"00000000", -- 000000F8 + X"00000000", -- 000000FC + X"00000000", -- 00000100 + X"00000000", -- 00000104 + X"00000000", -- 00000108 + X"00000000", -- 0000010C + X"00000000", -- 00000110 + X"00000000", -- 00000114 + X"00000000", -- 00000118 + X"00000000", -- 0000011C + X"00000000", -- 00000120 + X"00000000", -- 00000124 + X"00000000", -- 00000128 + X"00000000", -- 0000012C + X"00000000", -- 00000130 + X"00000000", -- 00000134 + X"00000000", -- 00000138 + X"00000000", -- 0000013C + X"00000000", -- 00000140 + X"00000000", -- 00000144 + X"00000000", -- 00000148 + X"00000000", -- 0000014C + X"00000000", -- 00000150 + X"00000000", -- 00000154 + X"00000000", -- 00000158 + X"00000000", -- 0000015C + X"00000000", -- 00000160 + X"00000000", -- 00000164 + X"00000000", -- 00000168 + X"00000000", -- 0000016C + X"00000000", -- 00000170 + X"00000000", -- 00000174 + X"00000000", -- 00000178 + X"00000000", -- 0000017C + X"401A6800", -- 00000180 + X"3C1BA000", -- 00000184 + X"277B0000", -- 00000188 + X"001AD082", -- 0000018C + X"335A000F", -- 00000190 + X"035BD025", -- 00000194 + X"AF7A0000", -- 00000198 + X"401A6800", -- 0000019C + X"00000000", -- 000001A0 + X"001AD202", -- 000001A4 + X"335A00FF", -- 000001A8 + X"1740FFFB", -- 000001AC + X"00000000", -- 000001B0 + X"401A7000", -- 000001B4 + X"00000000", -- 000001B8 + X"03400008", -- 000001BC + X"42000010", -- 000001C0 + X"3C1AA000", -- 000001C4 + X"275A0009", -- 000001C8 + X"241B000D", -- 000001CC + X"A35B0000", -- 000001D0 + X"3C1DBFD0", -- 000001D4 + X"27BDFFF0", -- 000001D8 + X"241A0005", -- 000001DC + X"1340009F", -- 000001E0 + X"241AFFFB", -- 000001E4 + X"1340009D", -- 000001E8 + X"241A0000", -- 000001EC + X"13400003", -- 000001F0 + X"00000000", -- 000001F4 + X"0BF00118", -- 000001F8 + X"00000000", -- 000001FC + X"241A0005", -- 00000200 + X"241B0006", -- 00000204 + X"135B0095", -- 00000208 + X"241AFFFB", -- 0000020C + X"135B0093", -- 00000210 + X"241A0000", -- 00000214 + X"135B0091", -- 00000218 + X"241A0006", -- 0000021C + X"135B0003", -- 00000220 + X"00000000", -- 00000224 + X"0BF00118", -- 00000228 + X"00000000", -- 0000022C + X"241AFFFB", -- 00000230 + X"0741008A", -- 00000234 + X"241A0005", -- 00000238 + X"07410002", -- 0000023C + X"00000000", -- 00000240 + X"0BF00118", -- 00000244 + X"241A0000", -- 00000248 + X"07410002", -- 0000024C + X"00000000", -- 00000250 + X"0BF00118", -- 00000254 + X"241AFFFB", -- 00000258 + X"1F400080", -- 0000025C + X"241A0000", -- 00000260 + X"1F40007E", -- 00000264 + X"241A0005", -- 00000268 + X"1F400002", -- 0000026C + X"00000000", -- 00000270 + X"0BF00118", -- 00000274 + X"241A0005", -- 00000278 + X"1B400078", -- 0000027C + X"241A0000", -- 00000280 + X"1B400002", -- 00000284 + X"00000000", -- 00000288 + X"0BF00118", -- 0000028C + X"241AFFFB", -- 00000290 + X"1B400002", -- 00000294 + X"00000000", -- 00000298 + X"0BF00118", -- 0000029C + X"241A0005", -- 000002A0 + X"0740006E", -- 000002A4 + X"241A0000", -- 000002A8 + X"0740006C", -- 000002AC + X"241AFFFB", -- 000002B0 + X"07400002", -- 000002B4 + X"00000000", -- 000002B8 + X"0BF00118", -- 000002BC + X"241A0005", -- 000002C0 + X"241B0006", -- 000002C4 + X"175B0002", -- 000002C8 + X"00000000", -- 000002CC + X"0BF00118", -- 000002D0 + X"241AFFFB", -- 000002D4 + X"175B0002", -- 000002D8 + X"00000000", -- 000002DC + X"0BF00118", -- 000002E0 + X"241AFFFA", -- 000002E4 + X"175B0002", -- 000002E8 + X"00000000", -- 000002EC + X"0BF00118", -- 000002F0 + X"241A0000", -- 000002F4 + X"175B0002", -- 000002F8 + X"00000000", -- 000002FC + X"0BF00118", -- 00000300 + X"241A0006", -- 00000304 + X"175B0055", -- 00000308 + X"241A0005", -- 0000030C + X"17400002", -- 00000310 + X"00000000", -- 00000314 + X"0BF00118", -- 00000318 + X"241AFFFB", -- 0000031C + X"17400002", -- 00000320 + X"00000000", -- 00000324 + X"0BF00118", -- 00000328 + X"241A0000", -- 0000032C + X"1740004B", -- 00000330 + X"241B0005", -- 00000334 + X"2F7A0006", -- 00000338 + X"2F7AFFFA", -- 0000033C + X"241BFFFB", -- 00000340 + X"2F7A0006", -- 00000344 + X"2F7AFFFA", -- 00000348 + X"241B0006", -- 0000034C + X"2F7A0005", -- 00000350 + X"2F7AFFFB", -- 00000354 + X"241BFFFA", -- 00000358 + X"2F7A0005", -- 0000035C + X"2F7AFFFB", -- 00000360 + X"241B0005", -- 00000364 + X"2B7A0006", -- 00000368 + X"2B7AFFFA", -- 0000036C + X"241BFFFB", -- 00000370 + X"2B7A0006", -- 00000374 + X"2B7AFFFA", -- 00000378 + X"241B0006", -- 0000037C + X"2B7A0005", -- 00000380 + X"2B7AFFFB", -- 00000384 + X"241BFFFA", -- 00000388 + X"2B7A0005", -- 0000038C + X"2B7AFFFB", -- 00000390 + X"241A0005", -- 00000394 + X"241B0006", -- 00000398 + X"035BD02B", -- 0000039C + X"241A0005", -- 000003A0 + X"241BFFFA", -- 000003A4 + X"035BD02B", -- 000003A8 + X"241AFFFB", -- 000003AC + X"241B0006", -- 000003B0 + X"035BD02B", -- 000003B4 + X"241AFFFB", -- 000003B8 + X"241BFFFA", -- 000003BC + X"035BD02B", -- 000003C0 + X"241A0006", -- 000003C4 + X"241B0005", -- 000003C8 + X"035BD02B", -- 000003CC + X"241A0006", -- 000003D0 + X"241BFFFB", -- 000003D4 + X"035BD02B", -- 000003D8 + X"241AFFFA", -- 000003DC + X"241B0005", -- 000003E0 + X"035BD02B", -- 000003E4 + X"241AFFFA", -- 000003E8 + X"241BFFFB", -- 000003EC + X"035BD02B", -- 000003F0 + X"241A0005", -- 000003F4 + X"241B0006", -- 000003F8 + X"035BD02A", -- 000003FC + X"241A0005", -- 00000400 + X"241BFFFA", -- 00000404 + X"035BD02A", -- 00000408 + X"241AFFFB", -- 0000040C + X"241B0006", -- 00000410 + X"035BD02A", -- 00000414 + X"241AFFFB", -- 00000418 + X"241BFFFA", -- 0000041C + X"035BD02A", -- 00000420 + X"241A0006", -- 00000424 + X"241B0005", -- 00000428 + X"035BD02A", -- 0000042C + X"241A0006", -- 00000430 + X"241BFFFB", -- 00000434 + X"035BD02A", -- 00000438 + X"241AFFFA", -- 0000043C + X"241B0005", -- 00000440 + X"035BD02A", -- 00000444 + X"241AFFFA", -- 00000448 + X"241BFFFB", -- 0000044C + X"035BD02A", -- 00000450 + X"3C1ABFC0", -- 00000454 + X"275A0F4C", -- 00000458 + X"0340F809", -- 0000045C + X"00000000", -- 00000460 + X"0BF00118", -- 00000464 + X"00000000", -- 00000468 + X"27BDFFF0", -- 0000046C + X"AFBE000C", -- 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00001818 + X"00000000", -- 0000181C + X"00000000", -- 00001820 + X"00000000", -- 00001824 + X"00000000", -- 00001828 + X"00000000", -- 0000182C + X"00000000", -- 00001830 + X"00000000", -- 00001834 + X"00000000", -- 00001838 + X"00000000", -- 0000183C + X"00000000", -- 00001840 + X"00000000", -- 00001844 + X"00000000", -- 00001848 + X"00000000", -- 0000184C + X"00000000", -- 00001850 + X"00000000", -- 00001854 + X"00000000", -- 00001858 + X"00000000", -- 0000185C + X"00000000", -- 00001860 + X"00000000", -- 00001864 + X"00000000", -- 00001868 + X"00000000", -- 0000186C + X"00000000", -- 00001870 + X"00000000", -- 00001874 + X"00000000", -- 00001878 + X"00000000", -- 0000187C + X"00000000", -- 00001880 + X"00000000", -- 00001884 + X"00000000", -- 00001888 + X"00000000", -- 0000188C + X"00000000", -- 00001890 + X"00000000", -- 00001894 + X"00000000", -- 00001898 + X"00000000", -- 0000189C + X"00000000", -- 000018A0 + X"00000000", -- 000018A4 + X"00000000", -- 000018A8 + X"00000000", -- 000018AC + X"00000000", -- 000018B0 + X"00000000", -- 000018B4 + X"00000000", -- 000018B8 + X"00000000", -- 000018BC + X"00000000", -- 000018C0 + X"00000000", -- 000018C4 + X"00000000", -- 000018C8 + X"00000000", -- 000018CC + X"00000000", -- 000018D0 + X"00000000", -- 000018D4 + X"00000000", -- 000018D8 + X"00000000", -- 000018DC + X"00000000", -- 000018E0 + X"00000000", -- 000018E4 + X"00000000", -- 000018E8 + X"00000000", -- 000018EC + X"00000000", -- 000018F0 + X"00000000", -- 000018F4 + X"00000000", -- 000018F8 + X"00000000", -- 000018FC + X"00000000", -- 00001900 + X"00000000", -- 00001904 + X"00000000", -- 00001908 + X"00000000", -- 0000190C + X"00000000", -- 00001910 + X"00000000", -- 00001914 + X"00000000", -- 00001918 + X"00000000", -- 0000191C + X"00000000", -- 00001920 + X"00000000", -- 00001924 + X"00000000", -- 00001928 + X"00000000", -- 0000192C + X"00000000", -- 00001930 + X"00000000", -- 00001934 + X"00000000", -- 00001938 + X"00000000", -- 0000193C + X"00000000", -- 00001940 + X"00000000", -- 00001944 + X"00000000", -- 00001948 + X"00000000", -- 0000194C + X"00000000", -- 00001950 + X"00000000", -- 00001954 + X"00000000", -- 00001958 + X"00000000", -- 0000195C + X"00000000", -- 00001960 + X"00000000", -- 00001964 + X"00000000", -- 00001968 + X"00000000", -- 0000196C + X"00000000", -- 00001970 + X"00000000", -- 00001974 + X"00000000", -- 00001978 + X"00000000", -- 0000197C + X"00000000", -- 00001980 + X"00000000", -- 00001984 + X"00000000", -- 00001988 + X"00000000", -- 0000198C + X"00000000", -- 00001990 + X"00000000", -- 00001994 + X"00000000", -- 00001998 + X"00000000", -- 0000199C + X"00000000", -- 000019A0 + X"00000000", -- 000019A4 + X"00000000", -- 000019A8 + X"00000000", -- 000019AC + X"00000000", -- 000019B0 + X"00000000", -- 000019B4 + X"00000000", -- 000019B8 + X"00000000", -- 000019BC + X"00000000", -- 000019C0 + X"00000000", -- 000019C4 + X"00000000", -- 000019C8 + X"00000000", -- 000019CC + X"00000000", -- 000019D0 + X"00000000", -- 000019D4 + X"00000000", -- 000019D8 + X"00000000", -- 000019DC + X"00000000", -- 000019E0 + X"00000000", -- 000019E4 + X"00000000", -- 000019E8 + X"00000000", -- 000019EC + X"00000000", -- 000019F0 + X"00000000", -- 000019F4 + X"00000000", -- 000019F8 + X"00000000", -- 000019FC + X"00000000", -- 00001A00 + X"00000000", -- 00001A04 + X"00000000", -- 00001A08 + X"00000000", -- 00001A0C + X"00000000", -- 00001A10 + X"00000000", -- 00001A14 + X"00000000", -- 00001A18 + X"00000000", -- 00001A1C + X"00000000", -- 00001A20 + X"00000000", -- 00001A24 + X"00000000", -- 00001A28 + X"00000000", -- 00001A2C + X"00000000", -- 00001A30 + X"00000000", -- 00001A34 + X"00000000", -- 00001A38 + X"00000000", -- 00001A3C + X"00000000", -- 00001A40 + X"00000000", -- 00001A44 + X"00000000", -- 00001A48 + X"00000000", -- 00001A4C + X"00000000", -- 00001A50 + X"00000000", -- 00001A54 + X"00000000", -- 00001A58 + X"00000000", -- 00001A5C + X"00000000", -- 00001A60 + X"00000000", -- 00001A64 + X"00000000", -- 00001A68 + X"00000000", -- 00001A6C + X"00000000", -- 00001A70 + X"00000000", -- 00001A74 + X"00000000", -- 00001A78 + X"00000000", -- 00001A7C + X"00000000", -- 00001A80 + X"00000000", -- 00001A84 + X"00000000", -- 00001A88 + X"00000000", -- 00001A8C + X"00000000", -- 00001A90 + X"00000000", -- 00001A94 + X"00000000", -- 00001A98 + X"00000000", -- 00001A9C + X"00000000", -- 00001AA0 + X"00000000", -- 00001AA4 + X"00000000", -- 00001AA8 + X"00000000", -- 00001AAC + X"00000000", -- 00001AB0 + X"00000000", -- 00001AB4 + X"00000000", -- 00001AB8 + X"00000000", -- 00001ABC + X"00000000", -- 00001AC0 + X"00000000", -- 00001AC4 + X"00000000", -- 00001AC8 + X"00000000", -- 00001ACC + X"00000000", -- 00001AD0 + X"00000000", -- 00001AD4 + X"00000000", -- 00001AD8 + X"00000000", -- 00001ADC + X"00000000", -- 00001AE0 + X"00000000", -- 00001AE4 + X"00000000", -- 00001AE8 + X"00000000", -- 00001AEC + X"00000000", -- 00001AF0 + X"00000000", -- 00001AF4 + X"00000000", -- 00001AF8 + X"00000000", -- 00001AFC + X"00000000", -- 00001B00 + X"00000000", -- 00001B04 + X"00000000", -- 00001B08 + X"00000000", -- 00001B0C + X"00000000", -- 00001B10 + X"00000000", -- 00001B14 + X"00000000", -- 00001B18 + X"00000000", -- 00001B1C + X"00000000", -- 00001B20 + X"00000000", -- 00001B24 + X"00000000", -- 00001B28 + X"00000000", -- 00001B2C + X"00000000", -- 00001B30 + X"00000000", -- 00001B34 + X"00000000", -- 00001B38 + X"00000000", -- 00001B3C + X"00000000", -- 00001B40 + X"00000000", -- 00001B44 + X"00000000", -- 00001B48 + X"00000000", -- 00001B4C + X"00000000", -- 00001B50 + X"00000000", -- 00001B54 + X"00000000", -- 00001B58 + X"00000000", -- 00001B5C + X"00000000", -- 00001B60 + X"00000000", -- 00001B64 + X"00000000", -- 00001B68 + X"00000000", -- 00001B6C + X"00000000", -- 00001B70 + X"00000000", -- 00001B74 + X"00000000", -- 00001B78 + X"00000000", -- 00001B7C + X"00000000", -- 00001B80 + X"00000000", -- 00001B84 + X"00000000", -- 00001B88 + X"00000000", -- 00001B8C + X"00000000", -- 00001B90 + X"00000000", -- 00001B94 + X"00000000", -- 00001B98 + X"00000000", -- 00001B9C + X"00000000", -- 00001BA0 + X"00000000", -- 00001BA4 + X"00000000", -- 00001BA8 + X"00000000", -- 00001BAC + X"00000000", -- 00001BB0 + X"00000000", -- 00001BB4 + X"00000000", -- 00001BB8 + X"00000000", -- 00001BBC + X"00000000", -- 00001BC0 + X"00000000", -- 00001BC4 + X"00000000", -- 00001BC8 + X"00000000", -- 00001BCC + X"00000000", -- 00001BD0 + X"00000000", -- 00001BD4 + X"00000000", -- 00001BD8 + X"00000000", -- 00001BDC + X"00000000", -- 00001BE0 + X"00000000", -- 00001BE4 + X"00000000", -- 00001BE8 + X"00000000", -- 00001BEC + X"00000000", -- 00001BF0 + X"00000000", -- 00001BF4 + X"00000000", -- 00001BF8 + X"00000000", -- 00001BFC + X"00000000", -- 00001C00 + X"00000000", -- 00001C04 + X"00000000", -- 00001C08 + X"00000000", -- 00001C0C + X"00000000", -- 00001C10 + X"00000000", -- 00001C14 + X"00000000", -- 00001C18 + X"00000000", -- 00001C1C + X"00000000", -- 00001C20 + X"00000000", -- 00001C24 + X"00000000", -- 00001C28 + X"00000000", -- 00001C2C + X"00000000", -- 00001C30 + X"00000000", -- 00001C34 + X"00000000", -- 00001C38 + X"00000000", -- 00001C3C + X"00000000", -- 00001C40 + X"00000000", -- 00001C44 + X"00000000", -- 00001C48 + X"00000000", -- 00001C4C + X"00000000", -- 00001C50 + X"00000000", -- 00001C54 + X"00000000", -- 00001C58 + X"00000000", -- 00001C5C + X"00000000", -- 00001C60 + X"00000000", -- 00001C64 + X"00000000", -- 00001C68 + X"00000000", -- 00001C6C + X"00000000", -- 00001C70 + X"00000000", -- 00001C74 + X"00000000", -- 00001C78 + X"00000000", -- 00001C7C + X"00000000", -- 00001C80 + X"00000000", -- 00001C84 + X"00000000", -- 00001C88 + X"00000000", -- 00001C8C + X"00000000", -- 00001C90 + X"00000000", -- 00001C94 + X"00000000", -- 00001C98 + X"00000000", -- 00001C9C + X"00000000", -- 00001CA0 + X"00000000", -- 00001CA4 + X"00000000", -- 00001CA8 + X"00000000", -- 00001CAC + X"00000000", -- 00001CB0 + X"00000000", -- 00001CB4 + X"00000000", -- 00001CB8 + X"00000000", -- 00001CBC + X"00000000", -- 00001CC0 + X"00000000", -- 00001CC4 + X"00000000", -- 00001CC8 + X"00000000", -- 00001CCC + X"00000000", -- 00001CD0 + X"00000000", -- 00001CD4 + X"00000000", -- 00001CD8 + X"00000000", -- 00001CDC + X"00000000", -- 00001CE0 + X"00000000", -- 00001CE4 + X"00000000", -- 00001CE8 + X"00000000", -- 00001CEC + X"00000000", -- 00001CF0 + X"00000000", -- 00001CF4 + X"00000000", -- 00001CF8 + X"00000000", -- 00001CFC + X"00000000", -- 00001D00 + X"00000000", -- 00001D04 + X"00000000", -- 00001D08 + X"00000000", -- 00001D0C + X"00000000", -- 00001D10 + X"00000000", -- 00001D14 + X"00000000", -- 00001D18 + X"00000000", -- 00001D1C + X"00000000", -- 00001D20 + X"00000000", -- 00001D24 + X"00000000", -- 00001D28 + X"00000000", -- 00001D2C + X"00000000", -- 00001D30 + X"00000000", -- 00001D34 + X"00000000", -- 00001D38 + X"00000000", -- 00001D3C + X"00000000", -- 00001D40 + X"00000000", -- 00001D44 + X"00000000", -- 00001D48 + X"00000000", -- 00001D4C + X"00000000", -- 00001D50 + X"00000000", -- 00001D54 + X"00000000", -- 00001D58 + X"00000000", -- 00001D5C + X"00000000", -- 00001D60 + X"00000000", -- 00001D64 + X"00000000", -- 00001D68 + X"00000000", -- 00001D6C + X"00000000", -- 00001D70 + X"00000000", -- 00001D74 + X"00000000", -- 00001D78 + X"00000000", -- 00001D7C + X"00000000", -- 00001D80 + X"00000000", -- 00001D84 + X"00000000", -- 00001D88 + X"00000000", -- 00001D8C + X"00000000", -- 00001D90 + X"00000000", -- 00001D94 + X"00000000", -- 00001D98 + X"00000000", -- 00001D9C + X"00000000", -- 00001DA0 + X"00000000", -- 00001DA4 + X"00000000", -- 00001DA8 + X"00000000", -- 00001DAC + X"00000000", -- 00001DB0 + X"00000000", -- 00001DB4 + X"00000000", -- 00001DB8 + X"00000000", -- 00001DBC + X"00000000", -- 00001DC0 + X"00000000", -- 00001DC4 + X"00000000", -- 00001DC8 + X"00000000", -- 00001DCC + X"00000000", -- 00001DD0 + X"00000000", -- 00001DD4 + X"00000000", -- 00001DD8 + X"00000000", -- 00001DDC + X"00000000", -- 00001DE0 + X"00000000", -- 00001DE4 + X"00000000", -- 00001DE8 + X"00000000", -- 00001DEC + X"00000000", -- 00001DF0 + X"00000000", -- 00001DF4 + X"00000000", -- 00001DF8 + X"00000000", -- 00001DFC + X"00000000", -- 00001E00 + X"00000000", -- 00001E04 + X"00000000", -- 00001E08 + X"00000000", -- 00001E0C + X"00000000", -- 00001E10 + X"00000000", -- 00001E14 + X"00000000", -- 00001E18 + X"00000000", -- 00001E1C + X"00000000", -- 00001E20 + X"00000000", -- 00001E24 + X"00000000", -- 00001E28 + X"00000000", -- 00001E2C + X"00000000", -- 00001E30 + X"00000000", -- 00001E34 + X"00000000", -- 00001E38 + X"00000000", -- 00001E3C + X"00000000", -- 00001E40 + X"00000000", -- 00001E44 + X"00000000", -- 00001E48 + X"00000000", -- 00001E4C + X"00000000", -- 00001E50 + X"00000000", -- 00001E54 + X"00000000", -- 00001E58 + X"00000000", -- 00001E5C + X"00000000", -- 00001E60 + X"00000000", -- 00001E64 + X"00000000", -- 00001E68 + X"00000000", -- 00001E6C + X"00000000", -- 00001E70 + X"00000000", -- 00001E74 + X"00000000", -- 00001E78 + X"00000000", -- 00001E7C + X"00000000", -- 00001E80 + X"00000000", -- 00001E84 + X"00000000", -- 00001E88 + X"00000000", -- 00001E8C + X"00000000", -- 00001E90 + X"00000000", -- 00001E94 + X"00000000", -- 00001E98 + X"00000000", -- 00001E9C + X"00000000", -- 00001EA0 + X"00000000", -- 00001EA4 + X"00000000", -- 00001EA8 + X"00000000", -- 00001EAC + X"00000000", -- 00001EB0 + X"00000000", -- 00001EB4 + X"00000000", -- 00001EB8 + X"00000000", -- 00001EBC + X"00000000", -- 00001EC0 + X"00000000", -- 00001EC4 + X"00000000", -- 00001EC8 + X"00000000", -- 00001ECC + X"00000000", -- 00001ED0 + X"00000000", -- 00001ED4 + X"00000000", -- 00001ED8 + X"00000000", -- 00001EDC + X"00000000", -- 00001EE0 + X"00000000", -- 00001EE4 + X"00000000", -- 00001EE8 + X"00000000", -- 00001EEC + X"00000000", -- 00001EF0 + X"00000000", -- 00001EF4 + X"00000000", -- 00001EF8 + X"00000000", -- 00001EFC + X"00000000", -- 00001F00 + X"00000000", -- 00001F04 + X"00000000", -- 00001F08 + X"00000000", -- 00001F0C + X"00000000", -- 00001F10 + X"00000000", -- 00001F14 + X"00000000", -- 00001F18 + X"00000000", -- 00001F1C + X"00000000", -- 00001F20 + X"00000000", -- 00001F24 + X"00000000", -- 00001F28 + X"00000000", -- 00001F2C + X"00000000", -- 00001F30 + X"00000000", -- 00001F34 + X"00000000", -- 00001F38 + X"00000000", -- 00001F3C + X"00000000", -- 00001F40 + X"00000000", -- 00001F44 + X"00000000", -- 00001F48 + X"00000000", -- 00001F4C + X"00000000", -- 00001F50 + X"00000000", -- 00001F54 + X"00000000", -- 00001F58 + X"00000000", -- 00001F5C + X"00000000", -- 00001F60 + X"00000000", -- 00001F64 + X"00000000", -- 00001F68 + X"00000000", -- 00001F6C + X"00000000", -- 00001F70 + X"00000000", -- 00001F74 + X"00000000", -- 00001F78 + X"00000000", -- 00001F7C + X"00000000", -- 00001F80 + X"00000000", -- 00001F84 + X"00000000", -- 00001F88 + X"00000000", -- 00001F8C + X"00000000", -- 00001F90 + X"00000000", -- 00001F94 + X"00000000", -- 00001F98 + X"00000000", -- 00001F9C + X"00000000", -- 00001FA0 + X"00000000", -- 00001FA4 + X"00000000", -- 00001FA8 + X"00000000", -- 00001FAC + X"00000000", -- 00001FB0 + X"00000000", -- 00001FB4 + X"00000000", -- 00001FB8 + X"00000000", -- 00001FBC + X"00000000", -- 00001FC0 + X"00000000", -- 00001FC4 + X"00000000", -- 00001FC8 + X"00000000", -- 00001FCC + X"00000000", -- 00001FD0 + X"00000000", -- 00001FD4 + X"00000000", -- 00001FD8 + X"00000000", -- 00001FDC + X"00000000", -- 00001FE0 + X"00000000", -- 00001FE4 + X"00000000", -- 00001FE8 + X"00000000", -- 00001FEC + X"00000000", -- 00001FF0 + X"00000000", -- 00001FF4 + X"00000000", -- 00001FF8 + X"00000000" -- 00001FFC + ); + +begin + +PROM_READ: + process(clk) + begin + if rising_edge(clk) and ce = '1' then + dout <= word_array(to_integer(addr(12 downto 2))); + end if; + end process; + + +-------------------------------------------------------------------------- +-- Virtex-4: JTAG Loader +-------------------------------------------------------------------------- + i00_BUFG : BUFG + port map + ( + O => bs_clk1, + I => bs_clk0 + ); + + i01_BUFG : BUFG + port map + ( + O => bs_update1, + I => bs_update0 + ); + + BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 + generic map + ( + JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) + ) + port map + ( + CAPTURE => bs_capture, -- CAPTURE output from TAP controller + DRCK => bs_clk0, -- Data register output for USER functions + RESET => bs_rst, -- Reset output from TAP controller + SEL => bs_sel, -- USER active output + SHIFT => bs_shift, -- SHIFT output from TAP controller + TDI => bs_tdi, -- TDI output from TAP controller + UPDATE => bs_update0, -- UPDATE output from TAP controller + TDO => bs_tdo -- Data input for USER function + ); + + jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); + jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); + jtag_ld_clk <= bs_update1; + jtag_ld_we <= bs_sel; + +sipo: + process (bs_rst, bs_clk1, bs_tdi, bs_shift) + begin + if bs_rst = '1' then + user_regi <= (others => '0'); + elsif rising_edge(bs_clk1) then + if bs_shift = '1' then + user_regi <= bs_tdi & user_regi(user_regi'left downto 1); + end if; + end if; + end process; + +piso: + process (bs_rst, bs_clk1, bs_shift, user_rego) + begin + bs_tdo <= user_rego(0); + if bs_rst = '1' then + user_rego <= (others => '0'); + elsif rising_edge(bs_clk1) then + if bs_shift = '1' then + user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); + else + user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; + + end if; + end if; + end process; + +PROM_WRITE: + process(jtag_ld_clk, jtag_ld_we) + begin + if rising_edge(jtag_ld_clk) then + if jtag_ld_we = '1' then + word_array(to_integer(jtag_ld_addr(10 downto 0))) <= jtag_ld_din; + else + jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(10 downto 0))); + end if; + end if; + end process; + +end data; diff --git a/projects/mips_sys/src/bootloader.dis b/projects/mips_sys/src/bootloader.dis new file mode 100644 index 0000000..64136b6 --- /dev/null +++ b/projects/mips_sys/src/bootloader.dis @@ -0,0 +1,1229 @@ + +bootloader.elf: file format elf32-littlemips + +Disassembly of section .stext: + +bfc00000 <__entry>: +bfc00000: 3c1a1040 lui k0,0x1040 +bfc00004: 375a000c ori k0,k0,0xc +bfc00008: 409a6000 mtc0 k0,$12 +bfc0000c: 241a0000 li k0,0 +bfc00010: 409a6800 mtc0 k0,$13 +bfc00014: 401a7800 mfc0 k0,$15 +bfc00018: 00000000 nop +bfc0001c: 409af800 mtc0 k0,$31 +bfc00020: 3c1abfc0 lui k0,0xbfc0 +bfc00024: 275a01c4 addiu k0,k0,452 +bfc00028: 03400008 jr k0 +bfc0002c: 00000000 nop +Disassembly of section .ktext: + +bfc00180 <_exc_handler>: +bfc00180: 401a6800 mfc0 k0,$13 +bfc00184: 3c1ba000 lui k1,0xa000 +bfc00188: 277b0000 addiu k1,k1,0 +bfc0018c: 001ad082 srl k0,k0,0x2 +bfc00190: 335a000f andi k0,k0,0xf +bfc00194: 035bd025 or k0,k0,k1 +bfc00198: af7a0000 sw k0,0(k1) +bfc0019c: 401a6800 mfc0 k0,$13 +bfc001a0: 00000000 nop +bfc001a4: 001ad202 srl k0,k0,0x8 +bfc001a8: 335a00ff andi k0,k0,0xff +bfc001ac: 1740fffb bnez k0,bfc0019c <_exc_handler+0x1c> +bfc001b0: 00000000 nop +bfc001b4: 401a7000 mfc0 k0,$14 +bfc001b8: 00000000 nop +bfc001bc: 03400008 jr k0 +bfc001c0: 42000010 rfe +Disassembly of section .text: + +bfc001c4 <_init>: +bfc001c4: 3c1aa000 275a0009 241b000d a35b0000 ...<..Z'...$..[. +bfc001d4: 3c1dbfd0 27bdfff0 241a0005 1340009f ...<...'...$..@. +bfc001e4: 241afffb 1340009d 241a0000 13400003 ...$..@....$..@. +bfc001f4: 00000000 0bf00118 00000000 241a0005 ...............$ +bfc00204: 241b0006 135b0095 241afffb 135b0093 ...$..[....$..[. +bfc00214: 241a0000 135b0091 241a0006 135b0003 ...$..[....$..[. +bfc00224: 00000000 0bf00118 00000000 241afffb ...............$ +bfc00234: 0741008a 241a0005 07410002 00000000 ..A....$..A..... +bfc00244: 0bf00118 241a0000 07410002 00000000 .......$..A..... +bfc00254: 0bf00118 241afffb 1f400080 241a0000 .......$..@....$ +bfc00264: 1f40007e 241a0005 1f400002 00000000 ~.@....$..@..... +bfc00274: 0bf00118 241a0005 1b400078 241a0000 .......$x.@....$ +bfc00284: 1b400002 00000000 0bf00118 241afffb ..@............$ +bfc00294: 1b400002 00000000 0bf00118 241a0005 ..@............$ +bfc002a4: 0740006e 241a0000 0740006c 241afffb n.@....$l.@....$ +bfc002b4: 07400002 00000000 0bf00118 241a0005 ..@............$ +bfc002c4: 241b0006 175b0002 00000000 0bf00118 ...$..[......... +bfc002d4: 241afffb 175b0002 00000000 0bf00118 ...$..[......... +bfc002e4: 241afffa 175b0002 00000000 0bf00118 ...$..[......... +bfc002f4: 241a0000 175b0002 00000000 0bf00118 ...$..[......... +bfc00304: 241a0006 175b0055 241a0005 17400002 ...$U.[....$..@. +bfc00314: 00000000 0bf00118 241afffb 17400002 ...........$..@. +bfc00324: 00000000 0bf00118 241a0000 1740004b ...........$K.@. +bfc00334: 241b0005 2f7a0006 2f7afffa 241bfffb ...$..z/..z/...$ +bfc00344: 2f7a0006 2f7afffa 241b0006 2f7a0005 ..z/..z/...$..z/ +bfc00354: 2f7afffb 241bfffa 2f7a0005 2f7afffb ..z/...$..z/..z/ +bfc00364: 241b0005 2b7a0006 2b7afffa 241bfffb ...$..z+..z+...$ +bfc00374: 2b7a0006 2b7afffa 241b0006 2b7a0005 ..z+..z+...$..z+ +bfc00384: 2b7afffb 241bfffa 2b7a0005 2b7afffb ..z+...$..z+..z+ +bfc00394: 241a0005 241b0006 035bd02b 241a0005 ...$...$+.[....$ +bfc003a4: 241bfffa 035bd02b 241afffb 241b0006 ...$+.[....$...$ +bfc003b4: 035bd02b 241afffb 241bfffa 035bd02b +.[....$...$+.[. +bfc003c4: 241a0006 241b0005 035bd02b 241a0006 ...$...$+.[....$ +bfc003d4: 241bfffb 035bd02b 241afffa 241b0005 ...$+.[....$...$ +bfc003e4: 035bd02b 241afffa 241bfffb 035bd02b +.[....$...$+.[. +bfc003f4: 241a0005 241b0006 035bd02a 241a0005 ...$...$*.[....$ +bfc00404: 241bfffa 035bd02a 241afffb 241b0006 ...$*.[....$...$ +bfc00414: 035bd02a 241afffb 241bfffa 035bd02a *.[....$...$*.[. +bfc00424: 241a0006 241b0005 035bd02a 241a0006 ...$...$*.[....$ +bfc00434: 241bfffb 035bd02a 241afffa 241b0005 ...$*.[....$...$ +bfc00444: 035bd02a 241afffa 241bfffb 035bd02a *.[....$...$*.[. +bfc00454: 3c1abfc0 275a0f4c 0340f809 ...: +bfc00460: 00000000 nop +bfc00464: 0bf00118 j bfc00460 <_terminate> +bfc00468: 00000000 nop + +bfc0046c : +bfc0046c: 27bdfff0 addiu sp,sp,-16 +bfc00470: afbe000c sw s8,12(sp) +bfc00474: 03a0f021 move s8,sp +bfc00478: 40026000 mfc0 v0,$12 +bfc0047c: 03c0e821 move sp,s8 +bfc00480: 8fbe000c lw s8,12(sp) +bfc00484: 03e00008 jr ra +bfc00488: 27bd0010 addiu sp,sp,16 + +bfc0048c : +bfc0048c: 27bdfff0 addiu sp,sp,-16 +bfc00490: afbe000c sw s8,12(sp) +bfc00494: 03a0f021 move s8,sp +bfc00498: 40027800 mfc0 v0,$15 +bfc0049c: 03c0e821 move sp,s8 +bfc004a0: 8fbe000c lw s8,12(sp) +bfc004a4: 03e00008 jr ra +bfc004a8: 27bd0010 addiu sp,sp,16 + +bfc004ac : +bfc004ac: 27bdfff0 addiu sp,sp,-16 +bfc004b0: afbe000c sw s8,12(sp) +bfc004b4: 03a0f021 move s8,sp +bfc004b8: 3c02a000 lui v0,0xa000 +bfc004bc: 34420008 ori v0,v0,0x8 +bfc004c0: afc20004 sw v0,4(s8) +bfc004c4: 3c02a000 lui v0,0xa000 +bfc004c8: 34420004 ori v0,v0,0x4 +bfc004cc: afc20000 sw v0,0(s8) +bfc004d0: 8fc20004 lw v0,4(s8) +bfc004d4: 00000000 nop +bfc004d8: 90420000 lbu v0,0(v0) +bfc004dc: 00000000 nop +bfc004e0: 00021600 sll v0,v0,0x18 +bfc004e4: 00021603 sra v0,v0,0x18 +bfc004e8: 304200ff andi v0,v0,0xff +bfc004ec: 30420010 andi v0,v0,0x10 +bfc004f0: 1040fff7 beqz v0,bfc004d0 +bfc004f4: 00000000 nop +bfc004f8: 8fc20000 lw v0,0(s8) +bfc004fc: 00000000 nop +bfc00500: 90420000 lbu v0,0(v0) +bfc00504: 00000000 nop +bfc00508: 00021600 sll v0,v0,0x18 +bfc0050c: 00021603 sra v0,v0,0x18 +bfc00510: 03c0e821 move sp,s8 +bfc00514: 8fbe000c lw s8,12(sp) +bfc00518: 27bd0010 addiu sp,sp,16 +bfc0051c: 03e00008 jr ra +bfc00520: 00000000 nop + +bfc00524 : +bfc00524: 27bdffe8 addiu sp,sp,-24 +bfc00528: afbe0014 sw s8,20(sp) +bfc0052c: 03a0f021 move s8,sp +bfc00530: 00801021 move v0,a0 +bfc00534: a3c20008 sb v0,8(s8) +bfc00538: 3c02a000 lui v0,0xa000 +bfc0053c: 34420008 ori v0,v0,0x8 +bfc00540: afc20004 sw v0,4(s8) +bfc00544: 3c02a000 lui v0,0xa000 +bfc00548: 34420004 ori v0,v0,0x4 +bfc0054c: afc20000 sw v0,0(s8) +bfc00550: 8fc20004 lw v0,4(s8) +bfc00554: 00000000 nop +bfc00558: 90420000 lbu v0,0(v0) +bfc0055c: 00000000 nop +bfc00560: 00021600 sll v0,v0,0x18 +bfc00564: 00021603 sra v0,v0,0x18 +bfc00568: 304200ff andi v0,v0,0xff +bfc0056c: 30420002 andi v0,v0,0x2 +bfc00570: 1440fff7 bnez v0,bfc00550 +bfc00574: 00000000 nop +bfc00578: 8fc30000 lw v1,0(s8) +bfc0057c: 93c20008 lbu v0,8(s8) +bfc00580: 00000000 nop +bfc00584: a0620000 sb v0,0(v1) +bfc00588: 03c0e821 move sp,s8 +bfc0058c: 8fbe0014 lw s8,20(sp) +bfc00590: 27bd0018 addiu sp,sp,24 +bfc00594: 03e00008 jr ra +bfc00598: 00000000 nop + +bfc0059c <_putchar>: +bfc0059c: 27bdfff0 addiu sp,sp,-16 +bfc005a0: afbf000c sw ra,12(sp) +bfc005a4: afbe0008 sw s8,8(sp) +bfc005a8: 03a0f021 move s8,sp +bfc005ac: 00801021 move v0,a0 +bfc005b0: a3c20000 sb v0,0(s8) +bfc005b4: 83c30000 lb v1,0(s8) +bfc005b8: 2402000a li v0,10 +bfc005bc: 1462000b bne v1,v0,bfc005ec <_putchar+0x50> +bfc005c0: 00000000 nop +bfc005c4: 2404000d li a0,13 +bfc005c8: 0ff00149 jal bfc00524 +bfc005cc: 00000000 nop +bfc005d0: 83c20000 lb v0,0(s8) +bfc005d4: 00000000 nop +bfc005d8: 00402021 move a0,v0 +bfc005dc: 0ff00149 jal bfc00524 +bfc005e0: 00000000 nop +bfc005e4: 0bf00180 j bfc00600 <_putchar+0x64> +bfc005e8: 00000000 nop +bfc005ec: 83c20000 lb v0,0(s8) +bfc005f0: 00000000 nop +bfc005f4: 00402021 move a0,v0 +bfc005f8: 0ff00149 jal bfc00524 +bfc005fc: 00000000 nop +bfc00600: 03c0e821 move sp,s8 +bfc00604: 8fbf000c lw ra,12(sp) +bfc00608: 8fbe0008 lw s8,8(sp) +bfc0060c: 27bd0010 addiu sp,sp,16 +bfc00610: 03e00008 jr ra +bfc00614: 00000000 nop + +bfc00618 : +bfc00618: 27bdffe8 addiu sp,sp,-24 +bfc0061c: afbf0014 sw ra,20(sp) +bfc00620: afbe0010 sw s8,16(sp) +bfc00624: 03a0f021 move s8,sp +bfc00628: afc40008 sw a0,8(s8) +bfc0062c: 8fc20008 lw v0,8(s8) +bfc00630: 00000000 nop +bfc00634: afc20000 sw v0,0(s8) +bfc00638: 0bf0019c j bfc00670 +bfc0063c: 00000000 nop +bfc00640: 8fc20008 lw v0,8(s8) +bfc00644: 00000000 nop +bfc00648: 80420000 lb v0,0(v0) +bfc0064c: 00000000 nop +bfc00650: 00401821 move v1,v0 +bfc00654: 8fc20008 lw v0,8(s8) +bfc00658: 00000000 nop +bfc0065c: 24420001 addiu v0,v0,1 +bfc00660: afc20008 sw v0,8(s8) +bfc00664: 00602021 move a0,v1 +bfc00668: 0ff00167 jal bfc0059c <_putchar> +bfc0066c: 00000000 nop +bfc00670: 8fc20008 lw v0,8(s8) +bfc00674: 00000000 nop +bfc00678: 80420000 lb v0,0(v0) +bfc0067c: 00000000 nop +bfc00680: 1440ffef bnez v0,bfc00640 +bfc00684: 00000000 nop +bfc00688: 8fc30008 lw v1,8(s8) +bfc0068c: 8fc20000 lw v0,0(s8) +bfc00690: 00000000 nop +bfc00694: 00621023 subu v0,v1,v0 +bfc00698: 03c0e821 move sp,s8 +bfc0069c: 8fbf0014 lw ra,20(sp) +bfc006a0: 8fbe0010 lw s8,16(sp) +bfc006a4: 27bd0018 addiu sp,sp,24 +bfc006a8: 03e00008 jr ra +bfc006ac: 00000000 nop + +bfc006b0 : +bfc006b0: 27bdffe8 addiu sp,sp,-24 +bfc006b4: afbf0014 sw ra,20(sp) +bfc006b8: afbe0010 sw s8,16(sp) +bfc006bc: 03a0f021 move s8,sp +bfc006c0: 00801021 move v0,a0 +bfc006c4: a3c20008 sb v0,8(s8) +bfc006c8: afc00004 sw zero,4(s8) +bfc006cc: 0bf001d5 j bfc00754 +bfc006d0: 00000000 nop +bfc006d4: 93c20008 lbu v0,8(s8) +bfc006d8: 00000000 nop +bfc006dc: 00021102 srl v0,v0,0x4 +bfc006e0: a3c20000 sb v0,0(s8) +bfc006e4: 83c20008 lb v0,8(s8) +bfc006e8: 00000000 nop +bfc006ec: 00021100 sll v0,v0,0x4 +bfc006f0: a3c20008 sb v0,8(s8) +bfc006f4: 93c20000 lbu v0,0(s8) +bfc006f8: 00000000 nop +bfc006fc: 2c42000a sltiu v0,v0,10 +bfc00700: 10400007 beqz v0,bfc00720 +bfc00704: 00000000 nop +bfc00708: 93c20000 lbu v0,0(s8) +bfc0070c: 00000000 nop +bfc00710: 24420030 addiu v0,v0,48 +bfc00714: a3c20001 sb v0,1(s8) +bfc00718: 0bf001cc j bfc00730 +bfc0071c: 00000000 nop +bfc00720: 93c20000 lbu v0,0(s8) +bfc00724: 00000000 nop +bfc00728: 24420037 addiu v0,v0,55 +bfc0072c: a3c20001 sb v0,1(s8) +bfc00730: 83c20001 lb v0,1(s8) +bfc00734: 00000000 nop +bfc00738: 00402021 move a0,v0 +bfc0073c: 0ff00149 jal bfc00524 +bfc00740: 00000000 nop +bfc00744: 8fc20004 lw v0,4(s8) +bfc00748: 00000000 nop +bfc0074c: 24420001 addiu v0,v0,1 +bfc00750: afc20004 sw v0,4(s8) +bfc00754: 8fc20004 lw v0,4(s8) +bfc00758: 00000000 nop +bfc0075c: 28420002 slti v0,v0,2 +bfc00760: 1440ffdc bnez v0,bfc006d4 +bfc00764: 00000000 nop +bfc00768: 03c0e821 move sp,s8 +bfc0076c: 8fbf0014 lw ra,20(sp) +bfc00770: 8fbe0010 lw s8,16(sp) +bfc00774: 27bd0018 addiu sp,sp,24 +bfc00778: 03e00008 jr ra +bfc0077c: 00000000 nop + +bfc00780 : +bfc00780: 27bdffe8 addiu sp,sp,-24 +bfc00784: afbf0014 sw ra,20(sp) +bfc00788: afbe0010 sw s8,16(sp) +bfc0078c: 03a0f021 move s8,sp +bfc00790: afc40008 sw a0,8(s8) +bfc00794: afc00004 sw zero,4(s8) +bfc00798: 0bf001f9 j bfc007e4 +bfc0079c: 00000000 nop +bfc007a0: 8fc20008 lw v0,8(s8) +bfc007a4: 00000000 nop +bfc007a8: 00021603 sra v0,v0,0x18 +bfc007ac: a3c20001 sb v0,1(s8) +bfc007b0: 83c20001 lb v0,1(s8) +bfc007b4: 00000000 nop +bfc007b8: 00402021 move a0,v0 +bfc007bc: 0ff001ac jal bfc006b0 +bfc007c0: 00000000 nop +bfc007c4: 8fc20008 lw v0,8(s8) +bfc007c8: 00000000 nop +bfc007cc: 00021200 sll v0,v0,0x8 +bfc007d0: afc20008 sw v0,8(s8) +bfc007d4: 8fc20004 lw v0,4(s8) +bfc007d8: 00000000 nop +bfc007dc: 24420001 addiu v0,v0,1 +bfc007e0: afc20004 sw v0,4(s8) +bfc007e4: 8fc20004 lw v0,4(s8) +bfc007e8: 00000000 nop +bfc007ec: 28420004 slti v0,v0,4 +bfc007f0: 1440ffeb bnez v0,bfc007a0 +bfc007f4: 00000000 nop +bfc007f8: 03c0e821 move sp,s8 +bfc007fc: 8fbf0014 lw ra,20(sp) +bfc00800: 8fbe0010 lw s8,16(sp) +bfc00804: 27bd0018 addiu sp,sp,24 +bfc00808: 03e00008 jr ra +bfc0080c: 00000000 nop + +bfc00810 : +bfc00810: 27bdffe8 addiu sp,sp,-24 +bfc00814: afbe0014 sw s8,20(sp) +bfc00818: 03a0f021 move s8,sp +bfc0081c: afc40008 sw a0,8(s8) +bfc00820: a3c00000 sb zero,0(s8) +bfc00824: afc00004 sw zero,4(s8) +bfc00828: 0bf00231 j bfc008c4 +bfc0082c: 00000000 nop +bfc00830: 8fc30004 lw v1,4(s8) +bfc00834: 8fc20008 lw v0,8(s8) +bfc00838: 00000000 nop +bfc0083c: 00431021 addu v0,v0,v1 +bfc00840: 90420000 lbu v0,0(v0) +bfc00844: 00000000 nop +bfc00848: a3c20001 sb v0,1(s8) +bfc0084c: 93c20001 lbu v0,1(s8) +bfc00850: 00000000 nop +bfc00854: 2c420041 sltiu v0,v0,65 +bfc00858: 14400007 bnez v0,bfc00878 +bfc0085c: 00000000 nop +bfc00860: 93c20001 lbu v0,1(s8) +bfc00864: 00000000 nop +bfc00868: 2442ffc9 addiu v0,v0,-55 +bfc0086c: a3c20001 sb v0,1(s8) +bfc00870: 0bf00222 j bfc00888 +bfc00874: 00000000 nop +bfc00878: 93c20001 lbu v0,1(s8) +bfc0087c: 00000000 nop +bfc00880: 2442ffd0 addiu v0,v0,-48 +bfc00884: a3c20001 sb v0,1(s8) +bfc00888: 93c20000 lbu v0,0(s8) +bfc0088c: 00000000 nop +bfc00890: 00021100 sll v0,v0,0x4 +bfc00894: 00021e00 sll v1,v0,0x18 +bfc00898: 00031e03 sra v1,v1,0x18 +bfc0089c: 83c20001 lb v0,1(s8) +bfc008a0: 00000000 nop +bfc008a4: 00621025 or v0,v1,v0 +bfc008a8: 00021600 sll v0,v0,0x18 +bfc008ac: 00021603 sra v0,v0,0x18 +bfc008b0: a3c20000 sb v0,0(s8) +bfc008b4: 8fc20004 lw v0,4(s8) +bfc008b8: 00000000 nop +bfc008bc: 24420001 addiu v0,v0,1 +bfc008c0: afc20004 sw v0,4(s8) +bfc008c4: 8fc20004 lw v0,4(s8) +bfc008c8: 00000000 nop +bfc008cc: 28420002 slti v0,v0,2 +bfc008d0: 1440ffd7 bnez v0,bfc00830 +bfc008d4: 00000000 nop +bfc008d8: 93c20000 lbu v0,0(s8) +bfc008dc: 03c0e821 move sp,s8 +bfc008e0: 8fbe0014 lw s8,20(sp) +bfc008e4: 27bd0018 addiu sp,sp,24 +bfc008e8: 03e00008 jr ra +bfc008ec: 00000000 nop + +bfc008f0 : +bfc008f0: 27bdffd8 addiu sp,sp,-40 +bfc008f4: afbf0024 sw ra,36(sp) +bfc008f8: afbe0020 sw s8,32(sp) +bfc008fc: 03a0f021 move s8,sp +bfc00900: afc40010 sw a0,16(s8) +bfc00904: afc50014 sw a1,20(s8) +bfc00908: afc60018 sw a2,24(s8) +bfc0090c: 8fc20018 lw v0,24(s8) +bfc00910: 00000000 nop +bfc00914: 14400004 bnez v0,bfc00928 +bfc00918: 00000000 nop +bfc0091c: afc0001c sw zero,28(s8) +bfc00920: 0bf00329 j bfc00ca4 +bfc00924: 00000000 nop +bfc00928: 8fc30010 lw v1,16(s8) +bfc0092c: 24020003 li v0,3 +bfc00930: ac620008 sw v0,8(v1) +bfc00934: afc00004 sw zero,4(s8) +bfc00938: 8fc20014 lw v0,20(s8) +bfc0093c: 00000000 nop +bfc00940: 24420001 addiu v0,v0,1 +bfc00944: 90420000 lbu v0,0(v0) +bfc00948: 00000000 nop +bfc0094c: 2c420031 sltiu v0,v0,49 +bfc00950: 14400015 bnez v0,bfc009a8 +bfc00954: 00000000 nop +bfc00958: 8fc20014 lw v0,20(s8) +bfc0095c: 00000000 nop +bfc00960: 24420001 addiu v0,v0,1 +bfc00964: 90420000 lbu v0,0(v0) +bfc00968: 00000000 nop +bfc0096c: 2c420034 sltiu v0,v0,52 +bfc00970: 1040000d beqz v0,bfc009a8 +bfc00974: 00000000 nop +bfc00978: 8fc20014 lw v0,20(s8) +bfc0097c: 00000000 nop +bfc00980: 24420001 addiu v0,v0,1 +bfc00984: 90420000 lbu v0,0(v0) +bfc00988: 00000000 nop +bfc0098c: 2442ffd1 addiu v0,v0,-47 +bfc00990: afc20004 sw v0,4(s8) +bfc00994: 8fc30010 lw v1,16(s8) +bfc00998: 24020002 li v0,2 +bfc0099c: ac620008 sw v0,8(v1) +bfc009a0: 0bf00294 j bfc00a50 +bfc009a4: 00000000 nop +bfc009a8: 8fc20014 lw v0,20(s8) +bfc009ac: 00000000 nop +bfc009b0: 24420001 addiu v0,v0,1 +bfc009b4: 90420000 lbu v0,0(v0) +bfc009b8: 00000000 nop +bfc009bc: 2c420037 sltiu v0,v0,55 +bfc009c0: 14400017 bnez v0,bfc00a20 +bfc009c4: 00000000 nop +bfc009c8: 8fc20014 lw v0,20(s8) +bfc009cc: 00000000 nop +bfc009d0: 24420001 addiu v0,v0,1 +bfc009d4: 90420000 lbu v0,0(v0) +bfc009d8: 00000000 nop +bfc009dc: 2c42003a sltiu v0,v0,58 +bfc009e0: 1040000f beqz v0,bfc00a20 +bfc009e4: 00000000 nop +bfc009e8: 8fc20014 lw v0,20(s8) +bfc009ec: 00000000 nop +bfc009f0: 24420001 addiu v0,v0,1 +bfc009f4: 90420000 lbu v0,0(v0) +bfc009f8: 00000000 nop +bfc009fc: 00401821 move v1,v0 +bfc00a00: 2402003b li v0,59 +bfc00a04: 00431023 subu v0,v0,v1 +bfc00a08: afc20004 sw v0,4(s8) +bfc00a0c: 8fc30010 lw v1,16(s8) +bfc00a10: 24020004 li v0,4 +bfc00a14: ac620008 sw v0,8(v1) +bfc00a18: 0bf00294 j bfc00a50 +bfc00a1c: 00000000 nop +bfc00a20: 8fc20014 lw v0,20(s8) +bfc00a24: 00000000 nop +bfc00a28: 24420001 addiu v0,v0,1 +bfc00a2c: 90430000 lbu v1,0(v0) +bfc00a30: 24020030 li v0,48 +bfc00a34: 14620006 bne v1,v0,bfc00a50 +bfc00a38: 00000000 nop +bfc00a3c: 24020002 li v0,2 +bfc00a40: afc20004 sw v0,4(s8) +bfc00a44: 8fc30010 lw v1,16(s8) +bfc00a48: 24020001 li v0,1 +bfc00a4c: ac620008 sw v0,8(v1) +bfc00a50: 8fc20014 lw v0,20(s8) +bfc00a54: 00000000 nop +bfc00a58: 24420002 addiu v0,v0,2 +bfc00a5c: 00402021 move a0,v0 +bfc00a60: 0ff00204 jal bfc00810 +bfc00a64: 00000000 nop +bfc00a68: a3c20008 sb v0,8(s8) +bfc00a6c: 93c30008 lbu v1,8(s8) +bfc00a70: 8fc20010 lw v0,16(s8) +bfc00a74: 00000000 nop +bfc00a78: ac430004 sw v1,4(v0) +bfc00a7c: 93c20008 lbu v0,8(s8) +bfc00a80: 00000000 nop +bfc00a84: a3c20009 sb v0,9(s8) +bfc00a88: 8fc20010 lw v0,16(s8) +bfc00a8c: 00000000 nop +bfc00a90: ac400000 sw zero,0(v0) +bfc00a94: afc00000 sw zero,0(s8) +bfc00a98: 0bf002c8 j bfc00b20 +bfc00a9c: 00000000 nop +bfc00aa0: 8fc20000 lw v0,0(s8) +bfc00aa4: 00000000 nop +bfc00aa8: 24420002 addiu v0,v0,2 +bfc00aac: 00021040 sll v0,v0,0x1 +bfc00ab0: 00401821 move v1,v0 +bfc00ab4: 8fc20014 lw v0,20(s8) +bfc00ab8: 00000000 nop +bfc00abc: 00431021 addu v0,v0,v1 +bfc00ac0: 00402021 move a0,v0 +bfc00ac4: 0ff00204 jal bfc00810 +bfc00ac8: 00000000 nop +bfc00acc: a3c20008 sb v0,8(s8) +bfc00ad0: 8fc20010 lw v0,16(s8) +bfc00ad4: 00000000 nop +bfc00ad8: 8c420000 lw v0,0(v0) +bfc00adc: 00000000 nop +bfc00ae0: 00021a00 sll v1,v0,0x8 +bfc00ae4: 93c20008 lbu v0,8(s8) +bfc00ae8: 00000000 nop +bfc00aec: 00621825 or v1,v1,v0 +bfc00af0: 8fc20010 lw v0,16(s8) +bfc00af4: 00000000 nop +bfc00af8: ac430000 sw v1,0(v0) +bfc00afc: 93c30009 lbu v1,9(s8) +bfc00b00: 93c20008 lbu v0,8(s8) +bfc00b04: 00000000 nop +bfc00b08: 00621021 addu v0,v1,v0 +bfc00b0c: a3c20009 sb v0,9(s8) +bfc00b10: 8fc20000 lw v0,0(s8) +bfc00b14: 00000000 nop +bfc00b18: 24420001 addiu v0,v0,1 +bfc00b1c: afc20000 sw v0,0(s8) +bfc00b20: 8fc20000 lw v0,0(s8) +bfc00b24: 8fc30004 lw v1,4(s8) +bfc00b28: 00000000 nop +bfc00b2c: 0043102a slt v0,v0,v1 +bfc00b30: 1440ffdb bnez v0,bfc00aa0 +bfc00b34: 00000000 nop +bfc00b38: 8fc20010 lw v0,16(s8) +bfc00b3c: 00000000 nop +bfc00b40: 8c430004 lw v1,4(v0) +bfc00b44: 8fc20004 lw v0,4(s8) +bfc00b48: 00000000 nop +bfc00b4c: 00021027 nor v0,zero,v0 +bfc00b50: 00621821 addu v1,v1,v0 +bfc00b54: 8fc20010 lw v0,16(s8) +bfc00b58: 00000000 nop +bfc00b5c: ac430004 sw v1,4(v0) +bfc00b60: 8fc20004 lw v0,4(s8) +bfc00b64: 00000000 nop +bfc00b68: 24420002 addiu v0,v0,2 +bfc00b6c: 00021040 sll v0,v0,0x1 +bfc00b70: 00401821 move v1,v0 +bfc00b74: 8fc20014 lw v0,20(s8) +bfc00b78: 00000000 nop +bfc00b7c: 00431821 addu v1,v0,v1 +bfc00b80: 8fc20010 lw v0,16(s8) +bfc00b84: 00000000 nop +bfc00b88: ac43000c sw v1,12(v0) +bfc00b8c: afc00000 sw zero,0(s8) +bfc00b90: 0bf00303 j bfc00c0c +bfc00b94: 00000000 nop +bfc00b98: 8fc20010 lw v0,16(s8) +bfc00b9c: 00000000 nop +bfc00ba0: 8c43000c lw v1,12(v0) +bfc00ba4: 8fc20000 lw v0,0(s8) +bfc00ba8: 00000000 nop +bfc00bac: 00021040 sll v0,v0,0x1 +bfc00bb0: 00621021 addu v0,v1,v0 +bfc00bb4: 00402021 move a0,v0 +bfc00bb8: 0ff00204 jal bfc00810 +bfc00bbc: 00000000 nop +bfc00bc0: a3c20008 sb v0,8(s8) +bfc00bc4: 8fc20010 lw v0,16(s8) +bfc00bc8: 00000000 nop +bfc00bcc: 8c43000c lw v1,12(v0) +bfc00bd0: 8fc20000 lw v0,0(s8) +bfc00bd4: 00000000 nop +bfc00bd8: 00621821 addu v1,v1,v0 +bfc00bdc: 93c20008 lbu v0,8(s8) +bfc00be0: 00000000 nop +bfc00be4: a0620000 sb v0,0(v1) +bfc00be8: 93c30009 lbu v1,9(s8) +bfc00bec: 93c20008 lbu v0,8(s8) +bfc00bf0: 00000000 nop +bfc00bf4: 00621021 addu v0,v1,v0 +bfc00bf8: a3c20009 sb v0,9(s8) +bfc00bfc: 8fc20000 lw v0,0(s8) +bfc00c00: 00000000 nop +bfc00c04: 24420001 addiu v0,v0,1 +bfc00c08: afc20000 sw v0,0(s8) +bfc00c0c: 8fc20010 lw v0,16(s8) +bfc00c10: 00000000 nop +bfc00c14: 8c420004 lw v0,4(v0) +bfc00c18: 00000000 nop +bfc00c1c: 00401821 move v1,v0 +bfc00c20: 8fc20000 lw v0,0(s8) +bfc00c24: 00000000 nop +bfc00c28: 0043102a slt v0,v0,v1 +bfc00c2c: 1440ffda bnez v0,bfc00b98 +bfc00c30: 00000000 nop +bfc00c34: 93c20009 lbu v0,9(s8) +bfc00c38: 00000000 nop +bfc00c3c: 00021027 nor v0,zero,v0 +bfc00c40: a3c20009 sb v0,9(s8) +bfc00c44: 8fc20010 lw v0,16(s8) +bfc00c48: 00000000 nop +bfc00c4c: 8c43000c lw v1,12(v0) +bfc00c50: 8fc20000 lw v0,0(s8) +bfc00c54: 00000000 nop +bfc00c58: 00021040 sll v0,v0,0x1 +bfc00c5c: 00621021 addu v0,v1,v0 +bfc00c60: 00402021 move a0,v0 +bfc00c64: 0ff00204 jal bfc00810 +bfc00c68: 00000000 nop +bfc00c6c: a3c20008 sb v0,8(s8) +bfc00c70: 93c30009 lbu v1,9(s8) +bfc00c74: 93c20008 lbu v0,8(s8) +bfc00c78: 00000000 nop +bfc00c7c: 10620004 beq v1,v0,bfc00c90 +bfc00c80: 00000000 nop +bfc00c84: afc0001c sw zero,28(s8) +bfc00c88: 0bf00329 j bfc00ca4 +bfc00c8c: 00000000 nop +bfc00c90: 8fc20010 lw v0,16(s8) +bfc00c94: 00000000 nop +bfc00c98: 8c420008 lw v0,8(v0) +bfc00c9c: 00000000 nop +bfc00ca0: afc2001c sw v0,28(s8) +bfc00ca4: 8fc2001c lw v0,28(s8) +bfc00ca8: 03c0e821 move sp,s8 +bfc00cac: 8fbf0024 lw ra,36(sp) +bfc00cb0: 8fbe0020 lw s8,32(sp) +bfc00cb4: 27bd0028 addiu sp,sp,40 +bfc00cb8: 03e00008 jr ra +bfc00cbc: 00000000 nop + +bfc00cc0 : +bfc00cc0: 27bdffe8 addiu sp,sp,-24 +bfc00cc4: afbf0014 sw ra,20(sp) +bfc00cc8: afbe0010 sw s8,16(sp) +bfc00ccc: 03a0f021 move s8,sp +bfc00cd0: afc40008 sw a0,8(s8) +bfc00cd4: afc00000 sw zero,0(s8) +bfc00cd8: 0ff0012b jal bfc004ac +bfc00cdc: 00000000 nop +bfc00ce0: a3c20004 sb v0,4(s8) +bfc00ce4: 83c30004 lb v1,4(s8) +bfc00ce8: 24020073 li v0,115 +bfc00cec: 10620015 beq v1,v0,bfc00d44 +bfc00cf0: 00000000 nop +bfc00cf4: 83c30004 lb v1,4(s8) +bfc00cf8: 24020053 li v0,83 +bfc00cfc: 1462fff6 bne v1,v0,bfc00cd8 +bfc00d00: 00000000 nop +bfc00d04: 0bf00351 j bfc00d44 +bfc00d08: 00000000 nop +bfc00d0c: 8fc30000 lw v1,0(s8) +bfc00d10: 8fc20008 lw v0,8(s8) +bfc00d14: 00000000 nop +bfc00d18: 00431821 addu v1,v0,v1 +bfc00d1c: 93c20004 lbu v0,4(s8) +bfc00d20: 00000000 nop +bfc00d24: a0620000 sb v0,0(v1) +bfc00d28: 8fc20000 lw v0,0(s8) +bfc00d2c: 00000000 nop +bfc00d30: 24420001 addiu v0,v0,1 +bfc00d34: afc20000 sw v0,0(s8) +bfc00d38: 0ff0012b jal bfc004ac +bfc00d3c: 00000000 nop +bfc00d40: a3c20004 sb v0,4(s8) +bfc00d44: 83c30004 lb v1,4(s8) +bfc00d48: 2402000d li v0,13 +bfc00d4c: 10620005 beq v1,v0,bfc00d64 +bfc00d50: 00000000 nop +bfc00d54: 83c30004 lb v1,4(s8) +bfc00d58: 2402000a li v0,10 +bfc00d5c: 1462ffeb bne v1,v0,bfc00d0c +bfc00d60: 00000000 nop +bfc00d64: 8fc20000 lw v0,0(s8) +bfc00d68: 03c0e821 move sp,s8 +bfc00d6c: 8fbf0014 lw ra,20(sp) +bfc00d70: 8fbe0010 lw s8,16(sp) +bfc00d74: 27bd0018 addiu sp,sp,24 +bfc00d78: 03e00008 jr ra +bfc00d7c: 00000000 nop + +bfc00d80 : +bfc00d80: 27bdfff0 addiu sp,sp,-16 +bfc00d84: afbe000c sw s8,12(sp) +bfc00d88: 03a0f021 move s8,sp +bfc00d8c: afc40000 sw a0,0(s8) +bfc00d90: 401a6000 mfc0 k0,$12 +bfc00d94: 3c1bffbf lui k1,0xffbf +bfc00d98: 377bffff ori k1,k1,0xffff +bfc00d9c: 035bd024 and k0,k0,k1 +bfc00da0: 409a6000 mtc0 k0,$12 +bfc00da4: 00800008 jr a0 +bfc00da8: 42000010 rfe +bfc00dac: 03c0e821 move sp,s8 +bfc00db0: 8fbe000c lw s8,12(sp) +bfc00db4: 03e00008 jr ra +bfc00db8: 27bd0010 addiu sp,sp,16 + +bfc00dbc : +bfc00dbc: 27bdffd0 addiu sp,sp,-48 +bfc00dc0: afbf002c sw ra,44(sp) +bfc00dc4: afbe0028 sw s8,40(sp) +bfc00dc8: 03a0f021 move s8,sp +bfc00dcc: 3c02bfc0 lui v0,0xbfc0 +bfc00dd0: 244215d0 addiu v0,v0,5584 +bfc00dd4: afc20008 sw v0,8(s8) +bfc00dd8: 3c02bfc0 lui v0,0xbfc0 +bfc00ddc: 244215d8 addiu v0,v0,5592 +bfc00de0: afc2000c sw v0,12(s8) +bfc00de4: 3c02bfc0 lui v0,0xbfc0 +bfc00de8: 244215e0 addiu v0,v0,5600 +bfc00dec: afc20010 sw v0,16(s8) +bfc00df0: 3c02bfc0 lui v0,0xbfc0 +bfc00df4: 244215e8 addiu v0,v0,5608 +bfc00df8: afc20014 sw v0,20(s8) +bfc00dfc: 3c02bfc0 lui v0,0xbfc0 +bfc00e00: 244215f0 addiu v0,v0,5616 +bfc00e04: afc20018 sw v0,24(s8) +bfc00e08: 3c02bfc0 lui v0,0xbfc0 +bfc00e0c: 244215f8 addiu v0,v0,5624 +bfc00e10: afc2001c sw v0,28(s8) +bfc00e14: 3c02bfc0 lui v0,0xbfc0 +bfc00e18: 24421604 addiu v0,v0,5636 +bfc00e1c: afc20020 sw v0,32(s8) +bfc00e20: 0ff0011b jal bfc0046c +bfc00e24: 00000000 nop +bfc00e28: afc20004 sw v0,4(s8) +bfc00e2c: 3c02bfc0 lui v0,0xbfc0 +bfc00e30: 2444160c addiu a0,v0,5644 +bfc00e34: 0ff00186 jal bfc00618 +bfc00e38: 00000000 nop +bfc00e3c: 8fc40004 lw a0,4(s8) +bfc00e40: 0ff001e0 jal bfc00780 +bfc00e44: 00000000 nop +bfc00e48: 3c02bfc0 lui v0,0xbfc0 +bfc00e4c: 24441618 addiu a0,v0,5656 +bfc00e50: 0ff00186 jal bfc00618 +bfc00e54: 00000000 nop +bfc00e58: 0ff00123 jal bfc0048c +bfc00e5c: 00000000 nop +bfc00e60: afc20004 sw v0,4(s8) +bfc00e64: 8fc20004 lw v0,4(s8) +bfc00e68: 00000000 nop +bfc00e6c: 00021203 sra v0,v0,0x8 +bfc00e70: 304200ff andi v0,v0,0xff +bfc00e74: afc20000 sw v0,0(s8) +bfc00e78: 3c02bfc0 lui v0,0xbfc0 +bfc00e7c: 2444161c addiu a0,v0,5660 +bfc00e80: 0ff00186 jal bfc00618 +bfc00e84: 00000000 nop +bfc00e88: 8fc20000 lw v0,0(s8) +bfc00e8c: 00000000 nop +bfc00e90: 18400020 blez v0,bfc00f14 +bfc00e94: 00000000 nop +bfc00e98: 8fc20000 lw v0,0(s8) +bfc00e9c: 00000000 nop +bfc00ea0: 28420007 slti v0,v0,7 +bfc00ea4: 1040001b beqz v0,bfc00f14 +bfc00ea8: 00000000 nop +bfc00eac: 8fc20000 lw v0,0(s8) +bfc00eb0: 00000000 nop +bfc00eb4: 00021080 sll v0,v0,0x2 +bfc00eb8: 03c21021 addu v0,s8,v0 +bfc00ebc: 8c420008 lw v0,8(v0) +bfc00ec0: 00000000 nop +bfc00ec4: 00402021 move a0,v0 +bfc00ec8: 0ff00186 jal bfc00618 +bfc00ecc: 00000000 nop +bfc00ed0: 3c02bfc0 lui v0,0xbfc0 +bfc00ed4: 24441628 addiu a0,v0,5672 +bfc00ed8: 0ff00186 jal bfc00618 +bfc00edc: 00000000 nop +bfc00ee0: 8fc20004 lw v0,4(s8) +bfc00ee4: 00000000 nop +bfc00ee8: 304200ff andi v0,v0,0xff +bfc00eec: afc20000 sw v0,0(s8) +bfc00ef0: 8fc20000 lw v0,0(s8) +bfc00ef4: 00000000 nop +bfc00ef8: 00021600 sll v0,v0,0x18 +bfc00efc: 00021603 sra v0,v0,0x18 +bfc00f00: 00402021 move a0,v0 +bfc00f04: 0ff001ac jal bfc006b0 +bfc00f08: 00000000 nop +bfc00f0c: 0bf003c9 j bfc00f24 +bfc00f10: 00000000 nop +bfc00f14: 3c02bfc0 lui v0,0xbfc0 +bfc00f18: 24441630 addiu a0,v0,5680 +bfc00f1c: 0ff00186 jal bfc00618 +bfc00f20: 00000000 nop +bfc00f24: 3c02bfc0 lui v0,0xbfc0 +bfc00f28: 24441618 addiu a0,v0,5656 +bfc00f2c: 0ff00186 jal bfc00618 +bfc00f30: 00000000 nop +bfc00f34: 03c0e821 move sp,s8 +bfc00f38: 8fbf002c lw ra,44(sp) +bfc00f3c: 8fbe0028 lw s8,40(sp) +bfc00f40: 27bd0030 addiu sp,sp,48 +bfc00f44: 03e00008 jr ra +bfc00f48: 00000000 nop + +bfc00f4c
: +bfc00f4c: 27bdfea8 addiu sp,sp,-344 +bfc00f50: afbf0154 sw ra,340(sp) +bfc00f54: afbe0150 sw s8,336(sp) +bfc00f58: 03a0f021 move s8,sp +bfc00f5c: afc40140 sw a0,320(s8) +bfc00f60: afc50144 sw a1,324(s8) +bfc00f64: 3c02a000 lui v0,0xa000 +bfc00f68: afc2001c sw v0,28(s8) +bfc00f6c: 3c024000 lui v0,0x4000 +bfc00f70: afc2000c sw v0,12(s8) +bfc00f74: 3c024000 lui v0,0x4000 +bfc00f78: afc20008 sw v0,8(s8) +bfc00f7c: 3c024000 lui v0,0x4000 +bfc00f80: afc20004 sw v0,4(s8) +bfc00f84: 3c02bfc0 lui v0,0xbfc0 +bfc00f88: 24421638 addiu v0,v0,5688 +bfc00f8c: afc20000 sw v0,0(s8) +bfc00f90: 8fc2001c lw v0,28(s8) +bfc00f94: 00000000 nop +bfc00f98: ac400000 sw zero,0(v0) +bfc00f9c: afc00020 sw zero,32(s8) +bfc00fa0: 0ff0036f jal bfc00dbc +bfc00fa4: 00000000 nop +bfc00fa8: 3c024000 lui v0,0x4000 +bfc00fac: afc20010 sw v0,16(s8) +bfc00fb0: afc00014 sw zero,20(s8) +bfc00fb4: afc00024 sw zero,36(s8) +bfc00fb8: 0bf00402 j bfc01008 +bfc00fbc: 00000000 nop +bfc00fc0: 8fc20014 lw v0,20(s8) +bfc00fc4: 00000000 nop +bfc00fc8: 8c430000 lw v1,0(v0) +bfc00fcc: 8fc20010 lw v0,16(s8) +bfc00fd0: 00000000 nop +bfc00fd4: ac430000 sw v1,0(v0) +bfc00fd8: 8fc20010 lw v0,16(s8) +bfc00fdc: 00000000 nop +bfc00fe0: 24420004 addiu v0,v0,4 +bfc00fe4: afc20010 sw v0,16(s8) +bfc00fe8: 8fc20014 lw v0,20(s8) +bfc00fec: 00000000 nop +bfc00ff0: 24420004 addiu v0,v0,4 +bfc00ff4: afc20014 sw v0,20(s8) +bfc00ff8: 8fc20024 lw v0,36(s8) +bfc00ffc: 00000000 nop +bfc01000: 24420004 addiu v0,v0,4 +bfc01004: afc20024 sw v0,36(s8) +bfc01008: 8fc20024 lw v0,36(s8) +bfc0100c: 00000000 nop +bfc01010: 28421c00 slti v0,v0,7168 +bfc01014: 1440ffea bnez v0,bfc00fc0 +bfc01018: 00000000 nop +bfc0101c: 3c044000 lui a0,0x4000 +bfc01020: 0ff00360 jal bfc00d80 +bfc01024: 00000000 nop +bfc01028: 3c02bfc0 lui v0,0xbfc0 +bfc0102c: 24441644 addiu a0,v0,5700 +bfc01030: 0ff00186 jal bfc00618 +bfc01034: 00000000 nop +bfc01038: 3c02bfc0 lui v0,0xbfc0 +bfc0103c: 24441658 addiu a0,v0,5720 +bfc01040: 0ff00186 jal bfc00618 +bfc01044: 00000000 nop +bfc01048: afc00024 sw zero,36(s8) +bfc0104c: 0bf00421 j bfc01084 +bfc01050: 00000000 nop +bfc01054: 8fc30024 lw v1,36(s8) +bfc01058: 8fc2000c lw v0,12(s8) +bfc0105c: 00000000 nop +bfc01060: 00431821 addu v1,v0,v1 +bfc01064: 8fc20024 lw v0,36(s8) +bfc01068: 00000000 nop +bfc0106c: 304200ff andi v0,v0,0xff +bfc01070: a0620000 sb v0,0(v1) +bfc01074: 8fc20024 lw v0,36(s8) +bfc01078: 00000000 nop +bfc0107c: 24420001 addiu v0,v0,1 +bfc01080: afc20024 sw v0,36(s8) +bfc01084: 8fc20024 lw v0,36(s8) +bfc01088: 3c030040 lui v1,0x40 +bfc0108c: 0043102a slt v0,v0,v1 +bfc01090: 1440fff0 bnez v0,bfc01054 +bfc01094: 00000000 nop +bfc01098: 3c02bfc0 lui v0,0xbfc0 +bfc0109c: 24441670 addiu a0,v0,5744 +bfc010a0: 0ff00186 jal bfc00618 +bfc010a4: 00000000 nop +bfc010a8: 3c02bfc0 lui v0,0xbfc0 +bfc010ac: 24441678 addiu a0,v0,5752 +bfc010b0: 0ff00186 jal bfc00618 +bfc010b4: 00000000 nop +bfc010b8: 3c02003f lui v0,0x3f +bfc010bc: 3442ffff ori v0,v0,0xffff +bfc010c0: afc20024 sw v0,36(s8) +bfc010c4: 0bf00441 j bfc01104 +bfc010c8: 00000000 nop +bfc010cc: 8fc30024 lw v1,36(s8) +bfc010d0: 8fc2000c lw v0,12(s8) +bfc010d4: 00000000 nop +bfc010d8: 00431021 addu v0,v0,v1 +bfc010dc: 90430000 lbu v1,0(v0) +bfc010e0: 8fc20024 lw v0,36(s8) +bfc010e4: 00000000 nop +bfc010e8: 304200ff andi v0,v0,0xff +bfc010ec: 14620009 bne v1,v0,bfc01114 +bfc010f0: 00000000 nop +bfc010f4: 8fc20024 lw v0,36(s8) +bfc010f8: 00000000 nop +bfc010fc: 2442ffff addiu v0,v0,-1 +bfc01100: afc20024 sw v0,36(s8) +bfc01104: 8fc20024 lw v0,36(s8) +bfc01108: 00000000 nop +bfc0110c: 0441ffef bgez v0,bfc010cc +bfc01110: 00000000 nop +bfc01114: 8fc20024 lw v0,36(s8) +bfc01118: 00000000 nop +bfc0111c: 24420001 addiu v0,v0,1 +bfc01120: afc20024 sw v0,36(s8) +bfc01124: 8fc20024 lw v0,36(s8) +bfc01128: 00000000 nop +bfc0112c: 10400007 beqz v0,bfc0114c +bfc01130: 00000000 nop +bfc01134: 3c02bfc0 lui v0,0xbfc0 +bfc01138: 24441694 addiu a0,v0,5780 +bfc0113c: 0ff00186 jal bfc00618 +bfc01140: 00000000 nop +bfc01144: 0bf00457 j bfc0115c +bfc01148: 00000000 nop +bfc0114c: 3c02bfc0 lui v0,0xbfc0 +bfc01150: 244416a0 addiu a0,v0,5792 +bfc01154: 0ff00186 jal bfc00618 +bfc01158: 00000000 nop +bfc0115c: 3c02bfc0 lui v0,0xbfc0 +bfc01160: 244416ac addiu a0,v0,5804 +bfc01164: 0ff00186 jal bfc00618 +bfc01168: 00000000 nop +bfc0116c: afc00024 sw zero,36(s8) +bfc01170: 0bf0046c j bfc011b0 +bfc01174: 00000000 nop +bfc01178: 8fc20024 lw v0,36(s8) +bfc0117c: 00000000 nop +bfc01180: 00021840 sll v1,v0,0x1 +bfc01184: 8fc20008 lw v0,8(s8) +bfc01188: 00000000 nop +bfc0118c: 00431821 addu v1,v0,v1 +bfc01190: 8fc20024 lw v0,36(s8) +bfc01194: 00000000 nop +bfc01198: 3042ffff andi v0,v0,0xffff +bfc0119c: a4620000 sh v0,0(v1) +bfc011a0: 8fc20024 lw v0,36(s8) +bfc011a4: 00000000 nop +bfc011a8: 24420001 addiu v0,v0,1 +bfc011ac: afc20024 sw v0,36(s8) +bfc011b0: 8fc20024 lw v0,36(s8) +bfc011b4: 3c030020 lui v1,0x20 +bfc011b8: 0043102a slt v0,v0,v1 +bfc011bc: 1440ffee bnez v0,bfc01178 +bfc011c0: 00000000 nop +bfc011c4: 3c02bfc0 lui v0,0xbfc0 +bfc011c8: 24441670 addiu a0,v0,5744 +bfc011cc: 0ff00186 jal bfc00618 +bfc011d0: 00000000 nop +bfc011d4: 3c02bfc0 lui v0,0xbfc0 +bfc011d8: 244416c8 addiu a0,v0,5832 +bfc011dc: 0ff00186 jal bfc00618 +bfc011e0: 00000000 nop +bfc011e4: 3c02001f lui v0,0x1f +bfc011e8: 3442ffff ori v0,v0,0xffff +bfc011ec: afc20024 sw v0,36(s8) +bfc011f0: 0bf0048e j bfc01238 +bfc011f4: 00000000 nop +bfc011f8: 8fc20024 lw v0,36(s8) +bfc011fc: 00000000 nop +bfc01200: 00021840 sll v1,v0,0x1 +bfc01204: 8fc20008 lw v0,8(s8) +bfc01208: 00000000 nop +bfc0120c: 00431021 addu v0,v0,v1 +bfc01210: 94430000 lhu v1,0(v0) +bfc01214: 8fc20024 lw v0,36(s8) +bfc01218: 00000000 nop +bfc0121c: 3042ffff andi v0,v0,0xffff +bfc01220: 14620009 bne v1,v0,bfc01248 +bfc01224: 00000000 nop +bfc01228: 8fc20024 lw v0,36(s8) +bfc0122c: 00000000 nop +bfc01230: 2442ffff addiu v0,v0,-1 +bfc01234: afc20024 sw v0,36(s8) +bfc01238: 8fc20024 lw v0,36(s8) +bfc0123c: 00000000 nop +bfc01240: 0441ffed bgez v0,bfc011f8 +bfc01244: 00000000 nop +bfc01248: 8fc20024 lw v0,36(s8) +bfc0124c: 00000000 nop +bfc01250: 24420001 addiu v0,v0,1 +bfc01254: afc20024 sw v0,36(s8) +bfc01258: 8fc20024 lw v0,36(s8) +bfc0125c: 00000000 nop +bfc01260: 10400007 beqz v0,bfc01280 +bfc01264: 00000000 nop +bfc01268: 3c02bfc0 lui v0,0xbfc0 +bfc0126c: 24441694 addiu a0,v0,5780 +bfc01270: 0ff00186 jal bfc00618 +bfc01274: 00000000 nop +bfc01278: 0bf004a4 j bfc01290 +bfc0127c: 00000000 nop +bfc01280: 3c02bfc0 lui v0,0xbfc0 +bfc01284: 244416a0 addiu a0,v0,5792 +bfc01288: 0ff00186 jal bfc00618 +bfc0128c: 00000000 nop +bfc01290: 3c02bfc0 lui v0,0xbfc0 +bfc01294: 244416e4 addiu a0,v0,5860 +bfc01298: 0ff00186 jal bfc00618 +bfc0129c: 00000000 nop +bfc012a0: afc00024 sw zero,36(s8) +bfc012a4: 0bf004b8 j bfc012e0 +bfc012a8: 00000000 nop +bfc012ac: 8fc20024 lw v0,36(s8) +bfc012b0: 00000000 nop +bfc012b4: 00021880 sll v1,v0,0x2 +bfc012b8: 8fc20004 lw v0,4(s8) +bfc012bc: 00000000 nop +bfc012c0: 00431821 addu v1,v0,v1 +bfc012c4: 8fc20024 lw v0,36(s8) +bfc012c8: 00000000 nop +bfc012cc: ac620000 sw v0,0(v1) +bfc012d0: 8fc20024 lw v0,36(s8) +bfc012d4: 00000000 nop +bfc012d8: 24420001 addiu v0,v0,1 +bfc012dc: afc20024 sw v0,36(s8) +bfc012e0: 8fc20024 lw v0,36(s8) +bfc012e4: 3c030010 lui v1,0x10 +bfc012e8: 0043102a slt v0,v0,v1 +bfc012ec: 1440ffef bnez v0,bfc012ac +bfc012f0: 00000000 nop +bfc012f4: 3c02bfc0 lui v0,0xbfc0 +bfc012f8: 24441670 addiu a0,v0,5744 +bfc012fc: 0ff00186 jal bfc00618 +bfc01300: 00000000 nop +bfc01304: 3c02bfc0 lui v0,0xbfc0 +bfc01308: 24441700 addiu a0,v0,5888 +bfc0130c: 0ff00186 jal bfc00618 +bfc01310: 00000000 nop +bfc01314: 3c02000f lui v0,0xf +bfc01318: 3442ffff ori v0,v0,0xffff +bfc0131c: afc20024 sw v0,36(s8) +bfc01320: 0bf004d9 j bfc01364 +bfc01324: 00000000 nop +bfc01328: 8fc20024 lw v0,36(s8) +bfc0132c: 00000000 nop +bfc01330: 00021880 sll v1,v0,0x2 +bfc01334: 8fc20004 lw v0,4(s8) +bfc01338: 00000000 nop +bfc0133c: 00431021 addu v0,v0,v1 +bfc01340: 8c430000 lw v1,0(v0) +bfc01344: 8fc20024 lw v0,36(s8) +bfc01348: 00000000 nop +bfc0134c: 14620009 bne v1,v0,bfc01374 +bfc01350: 00000000 nop +bfc01354: 8fc20024 lw v0,36(s8) +bfc01358: 00000000 nop +bfc0135c: 2442ffff addiu v0,v0,-1 +bfc01360: afc20024 sw v0,36(s8) +bfc01364: 8fc20024 lw v0,36(s8) +bfc01368: 00000000 nop +bfc0136c: 0441ffee bgez v0,bfc01328 +bfc01370: 00000000 nop +bfc01374: 8fc20024 lw v0,36(s8) +bfc01378: 00000000 nop +bfc0137c: 24420001 addiu v0,v0,1 +bfc01380: afc20024 sw v0,36(s8) +bfc01384: 8fc20024 lw v0,36(s8) +bfc01388: 00000000 nop +bfc0138c: 10400007 beqz v0,bfc013ac +bfc01390: 00000000 nop +bfc01394: 3c02bfc0 lui v0,0xbfc0 +bfc01398: 24441694 addiu a0,v0,5780 +bfc0139c: 0ff00186 jal bfc00618 +bfc013a0: 00000000 nop +bfc013a4: 0bf004ef j bfc013bc +bfc013a8: 00000000 nop +bfc013ac: 3c02bfc0 lui v0,0xbfc0 +bfc013b0: 244416a0 addiu a0,v0,5792 +bfc013b4: 0ff00186 jal bfc00618 +bfc013b8: 00000000 nop +bfc013bc: afc00024 sw zero,36(s8) +bfc013c0: 0bf004fd j bfc013f4 +bfc013c4: 00000000 nop +bfc013c8: 8fc20024 lw v0,36(s8) +bfc013cc: 00000000 nop +bfc013d0: 00021880 sll v1,v0,0x2 +bfc013d4: 8fc20004 lw v0,4(s8) +bfc013d8: 00000000 nop +bfc013dc: 00431021 addu v0,v0,v1 +bfc013e0: ac400000 sw zero,0(v0) +bfc013e4: 8fc20024 lw v0,36(s8) +bfc013e8: 00000000 nop +bfc013ec: 24420001 addiu v0,v0,1 +bfc013f0: afc20024 sw v0,36(s8) +bfc013f4: 8fc20024 lw v0,36(s8) +bfc013f8: 3c030010 lui v1,0x10 +bfc013fc: 0043102a slt v0,v0,v1 +bfc01400: 1440fff1 bnez v0,bfc013c8 +bfc01404: 00000000 nop +bfc01408: 8fc40000 lw a0,0(s8) +bfc0140c: 0ff00186 jal bfc00618 +bfc01410: 00000000 nop +bfc01414: 27c2002c addiu v0,s8,44 +bfc01418: 00402021 move a0,v0 +bfc0141c: 0ff00330 jal bfc00cc0 +bfc01420: 00000000 nop +bfc01424: afc20028 sw v0,40(s8) +bfc01428: 27c2012c addiu v0,s8,300 +bfc0142c: 27c3002c addiu v1,s8,44 +bfc01430: 00402021 move a0,v0 +bfc01434: 00602821 move a1,v1 +bfc01438: 8fc60028 lw a2,40(s8) +bfc0143c: 0ff0023c jal bfc008f0 +bfc01440: 00000000 nop +bfc01444: afc20028 sw v0,40(s8) +bfc01448: 8fc2001c lw v0,28(s8) +bfc0144c: 00000000 nop +bfc01450: ac400000 sw zero,0(v0) +bfc01454: 8fc20028 lw v0,40(s8) +bfc01458: 00000000 nop +bfc0145c: afc20148 sw v0,328(s8) +bfc01460: 24020002 li v0,2 +bfc01464: 8fc30148 lw v1,328(s8) +bfc01468: 00000000 nop +bfc0146c: 10620008 beq v1,v0,bfc01490 +bfc01470: 00000000 nop +bfc01474: 24020004 li v0,4 +bfc01478: 8fc30148 lw v1,328(s8) +bfc0147c: 00000000 nop +bfc01480: 1062002f beq v1,v0,bfc01540 +bfc01484: 00000000 nop +bfc01488: 0bf0056b j bfc015ac +bfc0148c: 00000000 nop +bfc01490: 8fc3012c lw v1,300(s8) +bfc01494: 8fc20130 lw v0,304(s8) +bfc01498: 00000000 nop +bfc0149c: 00621821 addu v1,v1,v0 +bfc014a0: 8fc20020 lw v0,32(s8) +bfc014a4: 00000000 nop +bfc014a8: 0043102b sltu v0,v0,v1 +bfc014ac: 10400006 beqz v0,bfc014c8 +bfc014b0: 00000000 nop +bfc014b4: 8fc2012c lw v0,300(s8) +bfc014b8: 8fc30130 lw v1,304(s8) +bfc014bc: 00000000 nop +bfc014c0: 00431021 addu v0,v0,v1 +bfc014c4: afc20020 sw v0,32(s8) +bfc014c8: 8fc2012c lw v0,300(s8) +bfc014cc: 00000000 nop +bfc014d0: afc20018 sw v0,24(s8) +bfc014d4: afc00024 sw zero,36(s8) +bfc014d8: 0bf00548 j bfc01520 +bfc014dc: 00000000 nop +bfc014e0: 8fc30138 lw v1,312(s8) +bfc014e4: 8fc20024 lw v0,36(s8) +bfc014e8: 00000000 nop +bfc014ec: 00621021 addu v0,v1,v0 +bfc014f0: 90430000 lbu v1,0(v0) +bfc014f4: 8fc20018 lw v0,24(s8) +bfc014f8: 00000000 nop +bfc014fc: a0430000 sb v1,0(v0) +bfc01500: 8fc20018 lw v0,24(s8) +bfc01504: 00000000 nop +bfc01508: 24420001 addiu v0,v0,1 +bfc0150c: afc20018 sw v0,24(s8) +bfc01510: 8fc20024 lw v0,36(s8) +bfc01514: 00000000 nop +bfc01518: 24420001 addiu v0,v0,1 +bfc0151c: afc20024 sw v0,36(s8) +bfc01520: 8fc20024 lw v0,36(s8) +bfc01524: 8fc30130 lw v1,304(s8) +bfc01528: 00000000 nop +bfc0152c: 0043102b sltu v0,v0,v1 +bfc01530: 1440ffeb bnez v0,bfc014e0 +bfc01534: 00000000 nop +bfc01538: 0bf0056b j bfc015ac +bfc0153c: 00000000 nop +bfc01540: 8fc3001c lw v1,28(s8) +bfc01544: 24020001 li v0,1 +bfc01548: ac620000 sw v0,0(v1) +bfc0154c: 8fc2012c lw v0,300(s8) +bfc01550: 00000000 nop +bfc01554: 00402021 move a0,v0 +bfc01558: 0ff001e0 jal bfc00780 +bfc0155c: 00000000 nop +bfc01560: 3c02bfc0 lui v0,0xbfc0 +bfc01564: 2444171c addiu a0,v0,5916 +bfc01568: 0ff00186 jal bfc00618 +bfc0156c: 00000000 nop +bfc01570: 8fc20020 lw v0,32(s8) +bfc01574: 00000000 nop +bfc01578: 2442fffc addiu v0,v0,-4 +bfc0157c: 00402021 move a0,v0 +bfc01580: 0ff001e0 jal bfc00780 +bfc01584: 00000000 nop +bfc01588: 3c02bfc0 lui v0,0xbfc0 +bfc0158c: 24441724 addiu a0,v0,5924 +bfc01590: 0ff00186 jal bfc00618 +bfc01594: 00000000 nop +bfc01598: 8fc2012c lw v0,300(s8) +bfc0159c: 00000000 nop +bfc015a0: 00402021 move a0,v0 +bfc015a4: 0ff00360 jal bfc00d80 +bfc015a8: 00000000 nop +bfc015ac: 8fc20028 lw v0,40(s8) +bfc015b0: 00000000 nop +bfc015b4: 1440ff97 bnez v0,bfc01414 +bfc015b8: 00000000 nop +bfc015bc: 8fc3001c lw v1,28(s8) +bfc015c0: 3c024000 lui v0,0x4000 +bfc015c4: ac620000 sw v0,0(v1) +bfc015c8: 0bf00502 j bfc01408 +bfc015cc: 00000000 nop diff --git a/projects/mips_sys/src/mips_pipeline.vhd b/projects/mips_sys/src/mips_pipeline.vhd new file mode 100644 index 0000000..ab2d777 --- /dev/null +++ b/projects/mips_sys/src/mips_pipeline.vhd @@ -0,0 +1,886 @@ +-------------------------------------------------------------------------- +-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL +-- This file: The pipeline +-- +-- Copyright (C) 2008 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +library work; +use work.mips_types.all; +use work.mips_instr.all; + +entity pipeline is + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + halt : in STD_LOGIC; + int : in unsigned(5 downto 0); + imem_rdy : in STD_LOGIC; + imem_en : out STD_LOGIC; + imem_addr : out word_t; + imem_data : in word_t; + dmem_rdy : in STD_LOGIC; + dmem_en : out STD_LOGIC; + dmem_re : out STD_LOGIC; + dmem_we : out unsigned(3 downto 0); + dmem_addr : out word_t; + dmem_din : in word_t; + dmem_dout : out word_t + ); +end pipeline; + +architecture Behavioral of pipeline is + +-------------------------------------------------------------------------- + COMPONENT reg_dual is + Generic + ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port + ( + clk_w : in STD_LOGIC; + en : in STD_LOGIC; + we : in STD_LOGIC; + wptr : in unsigned (addr_width-1 downto 0); + din : in unsigned (data_width-1 downto 0); + rptr_a : in unsigned (addr_width-1 downto 0); + rptr_b : in unsigned (addr_width-1 downto 0); + dout_a : out unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); + END COMPONENT; + +-------------------------------------------------------------------------- + COMPONENT idecode_rom is + Port + ( + nop : in std_logic; + inst_in : in word_t; + ctrl_out : out ctrl_lines_t + ); + END COMPONENT; + +-------------------------------------------------------------------------- + COMPONENT shifter is + Generic + ( + data_width : integer + ); + Port + ( + shift_ctrl : in shift_ctrl_t; + din : in unsigned (data_width-1 downto 0); + dout : out unsigned (data_width-1 downto 0) + ); + END COMPONENT; + +-------------------------------------------------------------------------- + COMPONENT alu is + Generic + ( + data_width : integer + ); + Port + ( + op1_in : in unsigned (data_width-1 downto 0); + op2_in : in unsigned (data_width-1 downto 0); + op2_shifted : in unsigned (data_width-1 downto 0); + ctrl : in alu_ctrl_t; + result : out unsigned (data_width-1 downto 0); + flags : out alu_flags_t + ); + END COMPONENT; + +-------------------------------------------------------------------------- + COMPONENT bcu is + Generic + ( + data_width : integer + ); + Port + ( + op1_in : in unsigned (data_width-1 downto 0); + op2_in : in unsigned (data_width-1 downto 0); + flags : out bcu_flags_t + ); + END COMPONENT; + +-------------------------------------------------------------------------- + COMPONENT cop is + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + ce : in STD_LOGIC; + IR_valid : in STD_LOGIC; + IR : in word_t; + events : in event_t; + ctrl_in : in cop_ctrl_in_t; + ctrl_out : out cop_ctrl_out_t; + din : in word_t; + dout : out word_t + ); + END COMPONENT; + +-------------------------------------------------------------------------- + COMPONENT muldiv is + Port + ( + rst : in std_logic; + clk : in std_logic; + hilo_we : in std_logic; + din_hi : in word_t; + din_lo : in word_t; + mul_divn : in std_logic; + start : in std_logic; + s_un : in std_logic; + hilo_sel : in std_logic; + busy : out std_logic; + dout : out word_t + ); + END COMPONENT; + +-------------------------------------------------------------------------- + constant RESET_VECTOR : word_t := X"BFC00000"; + + signal ID_stage : ID_t; + signal EX_stage : EX_t; + signal MEM_stage : MEM_t; + signal WB_stage : WB_t; + signal clk_2, clk_1 : STD_LOGIC; + signal hdu : hdu_t; + signal cpu_rst : STD_LOGIC; + signal reg_a : word_t; + signal reg_b : word_t; + signal ctrl_lines : ctrl_lines_t; + signal ID_act : STD_LOGIC; + signal EX_act : STD_LOGIC; + signal MEM_act : STD_LOGIC; + signal WB_act : STD_LOGIC; + signal ID_nop : STD_LOGIC; + signal EX_nop : STD_LOGIC; + signal MEM_nop : STD_LOGIC; + signal WB_nop : STD_LOGIC; + signal IF_stall : STD_LOGIC; + signal EX_stall : STD_LOGIC; + signal MEM_stall : STD_LOGIC; + signal WB_stall : STD_LOGIC; + signal cpu_run : STD_LOGIC; + signal branch_ce : STD_LOGIC; + signal run_en : STD_LOGIC; + signal mul_dep : STD_LOGIC; + signal imem_dep : STD_LOGIC; + signal dmem_dep : STD_LOGIC; + signal cop_en : STD_LOGIC; + signal cop_ctrl : cop_ctrl_in_t; + signal cop_din : word_t; + signal cop_dout : word_t; + signal alu_result : word_t; + signal mul_result : word_t; + signal mul_busy : STD_LOGIC; + signal events : event_t; + signal bcu_op_a : word_t; + signal bcu_op_b : word_t; + signal bcu_flags : bcu_flags_t; + + attribute ram_style : string; + + attribute ram_style of reg_a: signal is "distributed"; + attribute ram_style of reg_b: signal is "distributed"; + + signal pc : pc_t; + +-------------------------------------------------------------------------- +begin + + clk_1 <= clk; + clk_2 <= not clk; + cpu_run <= not halt and run_en; + + events.Int <= int; + events.illegal <= EX_stage.ctrl.exc_illegal; + events.break <= EX_stage.ctrl.exc_break; + events.syscall <= EX_stage.ctrl.exc_syscall; + + -- Stall Detection Unit --------------------------------------------------- + imem_en <= run_en and (not (ID_stage.cop_stat.exc_strobe or mul_dep) or ID_stage.cop_stat.ec) and not dmem_dep; + + ID_nop <= cpu_rst or imem_dep; + EX_nop <= cpu_rst or EX_stage.cop_stat.exc_strobe or mul_dep; + MEM_nop <= cpu_rst or EX_stage.cop_stat.exc_strobe; + WB_nop <= cpu_rst or EX_stage.cop_stat.exc_strobe or dmem_dep; + + IF_stall <= not cpu_run or mul_dep or ID_stage.cop_stat.ec or imem_dep or dmem_dep; + EX_stall <= not cpu_run or dmem_dep; + MEM_stall <= not cpu_run or dmem_dep; + WB_stall <= not cpu_run; + + mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy); + imem_dep <= not imem_rdy; + dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en; + --------------------------------------------------------------------------- + + events.inst_load_err <= '1' when EX_stage.epc(1 downto 0) /= "00" else '0'; + events.inst_priv_addr <= EX_stage.epc(word_t'left); + + cop_en <= not ID_nop; + +-------------------------------------------------------------------------- +-- Muldiv +-------------------------------------------------------------------------- +inst_muldiv: muldiv + PORT MAP + ( + rst => cpu_rst, + clk => clk, + hilo_we => EX_stage.ctrl.mul_hilo_we, + din_hi => EX_stage.reg_a, + din_lo => EX_stage.reg_b, + mul_divn => EX_stage.ctrl.mul_mul_divn, + start => EX_stage.ctrl.mul_start, + s_un => EX_stage.ctrl.mul_s_un, + hilo_sel => EX_stage.ctrl.mul_hilo_sel, + busy => mul_busy, + dout => mul_result + ); + +-------------------------------------------------------------------------- +-- Coprocessor +-------------------------------------------------------------------------- +inst_cop: cop + PORT MAP + ( + rst => cpu_rst, + clk => clk, + ce => cop_en, + events => events, + IR_valid => ID_stage.ctrl.cop_instr_en, + IR => ID_stage.IR, + ctrl_in => cop_ctrl, + ctrl_out => ID_stage.cop_stat, + dout => cop_dout, + din => cop_din + ); + + cop_ctrl.bd_ex <= EX_stage.ctrl.branch; + cop_ctrl.bd_mem <= MEM_stage.ctrl.branch; + cop_ctrl.bd_wb <= WB_stage.ctrl.branch; + cop_ctrl.epc_id <= ID_stage.epc; + cop_ctrl.epc_ex <= EX_stage.epc; + cop_ctrl.epc_mem <= MEM_stage.epc; + cop_ctrl.epc_wb <= WB_stage.epc; + cop_ctrl.dmem_addr <= EX_stage.va; + +-------------------------------------------------------------------------- +-- IF stage +-------------------------------------------------------------------------- + imem_addr <= pc.curr; + +proc_stage_pc: + process(pc, rst, IF_stall) + begin + if rst = '1' then + pc.curr <= RESET_VECTOR after 2 ns; + elsif IF_stall = '0' then + if pc.is_branch then + pc.curr <= pc.pc_branch after 2 ns; + else + pc.curr <= pc.nxt after 2 ns; + end if; + end if; + end process; + +proc_stage_pc_branch: + process(clk_1) + begin + if rising_edge(clk_1) then + if IF_stall = '0' then + pc.pc_branch <= pc.curr + ID_stage.bimm18; + end if; + end if; + end process; + +proc_stage_pc_next: + process(clk_1) + begin + if rising_edge(clk_1) then + branch_ce <= '0'; + if rst = '1' then + pc.nxt <= RESET_VECTOR; + pc.last <= RESET_VECTOR; + elsif ID_stage.cop_stat.exc_strobe = '1' then + pc.nxt <= ID_stage.cop_stat.exc_vec; + elsif IF_stall = '0' then + branch_ce <= '1'; + pc.last <= pc.curr; + if ID_stage.ctrl.jump = '1' then + pc.nxt <= ID_stage.jimm32; + elsif ID_stage.ctrl.jump_long = '1' then + pc.nxt <= ID_stage.reg_a; + else + pc.nxt <= pc.curr + 4; + end if; + end if; + end if; + end process; + +proc_stage_branch: + process(clk_2) + begin + if rising_edge(clk_2) and branch_ce = '1' then + pc.is_branch <= false; + if EX_stage.ctrl.branch = '1' then + + case EX_stage.ctrl.bc_src is + + when bc_eq_ne => + if (EX_stage.ctrl.bc_not xor bcu_flags.eq) = '1' then + pc.is_branch <= true; + end if; + + when bc_lez_gtz => + if (EX_stage.ctrl.bc_not xor (bcu_flags.z or bcu_flags.ltz)) = '1' then + pc.is_branch <= true; + end if; + + when bc_ltz_gez => + if (EX_stage.ctrl.bc_not xor bcu_flags.ltz) = '1' then + pc.is_branch <= true; + end if; + + when others => null; + end case; + end if; + end if; + end process; + + process(rst, clk_1) + variable reset_delay : unsigned (5 downto 0); + begin + if rst = '1' then + reset_delay := (others => '1'); + cpu_rst <= '1'; + run_en <= '0'; + elsif rising_edge(clk_1) then + if reset_delay /= (5 downto 0 => '0') then + reset_delay := reset_delay - 1; + else + cpu_rst <= '0'; + end if; + if reset_delay(reset_delay'left) = '0' then + run_en <= '1'; + end if; + end if; + end process; + +-------------------------------------------------------------------------- +-- ID stage +-------------------------------------------------------------------------- + ID_act <= not ID_nop; + ID_stage.IR <= imem_data; + ID_stage.pcn <= pc.curr; + ID_stage.op <= decode_op(ID_stage.IR) when ID_nop = '0' else NOP; + ID_stage.jimm32 <= extract_jimm32(ID_stage.IR, ID_stage.pcn); + ID_stage.bimm18 <= extract_bimm18(ID_stage.IR, ID_stage.pcn); + ID_stage.shamt <= extract_shamt(ID_stage.IR); + ID_stage.reg_a_rptr <= extract_rs(ID_stage.IR); + ID_stage.reg_b_rptr <= extract_rt(ID_stage.IR); + ID_stage.ctrl <= ctrl_lines; + ID_stage.reg_write <= ID_stage.ctrl.reg_write or ID_stage.cop_stat.reg_write; + ID_stage.epc <= pc.last; + +proc_stage_hdu: + process(ID_stage, EX_stage, MEM_stage, WB_stage) + variable read_a, read_b : boolean; + variable raw_a_EX, raw_a_MEM, raw_a_WB : boolean; + variable raw_b_EX, raw_b_MEM, raw_b_WB : boolean; + variable reg_ptr_a : reg_ptr_t; + variable reg_ptr_b : reg_ptr_t; + begin + + reg_ptr_a := ID_stage.reg_a_rptr; + reg_ptr_b := ID_stage.reg_b_rptr; + raw_a_EX := reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; + raw_a_MEM := reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; + raw_a_WB := reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; + raw_b_EX := reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; + raw_b_MEM := reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; + raw_b_WB := reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; + + hdu.alu_fwd_a_ex <= raw_a_EX after 1 ns; + hdu.alu_fwd_a_mem <= raw_a_MEM after 1 ns; + hdu.alu_fwd_a_wb <= raw_a_WB after 1 ns; + hdu.alu_fwd_b_ex <= raw_b_EX after 1 ns; + hdu.alu_fwd_b_mem <= raw_b_MEM after 1 ns; + hdu.alu_fwd_b_wb <= raw_b_WB after 1 ns; + + end process; + +proc_stage_fwd_a: + process(reg_a, hdu, EX_stage, MEM_stage, WB_stage) + variable data : word_t; + begin + data := reg_a; + if hdu.alu_fwd_a_ex then + data := EX_stage.result; + elsif hdu.alu_fwd_a_mem then + data := MEM_stage.data; + elsif hdu.alu_fwd_a_wb then + data := WB_stage.data; + end if; + ID_stage.reg_a <= data after 2 ns; + end process; + +proc_stage_fwd_b: + process(reg_b, hdu, EX_stage, MEM_stage, WB_stage) + variable data : word_t; + begin + data := reg_b; + if hdu.alu_fwd_b_ex then + data := EX_stage.result; + elsif hdu.alu_fwd_b_mem then + data := MEM_stage.data; + elsif hdu.alu_fwd_b_wb then + data := WB_stage.data; + end if; + ID_stage.reg_b <= data after 2 ns; + end process; + +proc_imm_mux: + process(ID_stage) + variable data : word_t; + begin + data := extract_uimm16(ID_stage.IR); + + case ID_stage.ctrl.imm_src is + + when src_imm32 => + data := extract_simm32(ID_stage.IR); + + when src_imm16 => + data := extract_uimm16(ID_stage.IR); + + when src_imm16_high => + data := ID_stage.IR(word_t'length/2-1 downto 0) & (word_t'length/2-1 downto 0 => '0'); + + when others => null; + + end case; + + ID_stage.imm <= data after 2 ns; + + end process; + +-------------------------------------------------------------------------- +inst_idecode_rom: idecode_rom + PORT MAP + ( + nop => ID_nop, + inst_in => ID_stage.IR, + ctrl_out => ctrl_lines + ); + +inst_reg_dual: reg_dual + GENERIC MAP + ( + addr_width => reg_ptr_t'length, + data_width => word_t'length + ) + PORT MAP + ( + clk_w => clk_1, + we => WB_stage.wreg_we, + en => '1', + wptr => WB_stage.reg_wptr, + din => WB_stage.data, + rptr_a => ID_stage.reg_a_rptr, + rptr_b => ID_stage.reg_b_rptr, + dout_a => reg_a, + dout_b => reg_b + ); + +-------------------------------------------------------------------------- +-- EX stage +-------------------------------------------------------------------------- + EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR); + EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR); + EX_stage.result <= mul_result when EX_stage.ctrl.mul_access = '1' else alu_result; + EX_act <= not (EX_nop or EX_stall); + +proc_stage_ID_EX_1: + process(clk_1) + begin + if rising_edge(clk_1) then + if cpu_rst = '1' then + EX_stage.epc <= (others => '0'); + elsif EX_stall = '0' then + EX_stage.op <= ID_stage.op; + if ID_nop = '0' then + EX_stage.IR <= ID_stage.IR; + else + EX_stage.IR <= (others => '0'); + end if; + EX_stage.ctrl <= ID_stage.ctrl; + EX_stage.reg_write <= ID_stage.reg_write; + EX_stage.pcn <= ID_stage.pcn; + EX_stage.epc <= ID_stage.epc; + EX_stage.cop_stat <= ID_stage.cop_stat; + if EX_nop = '1' then + EX_stage.op <= NOP; + EX_stage.IR <= (others => '0'); + EX_stage.ctrl <= ctrl_lines_default; + EX_stage.cop_stat.exc_strobe <= '0'; + EX_stage.reg_write <= '0'; + end if; + end if; + end if; + end process; + +proc_stage_EX_except: + process(EX_stage) + begin + events.data_load_err <= '0'; + events.data_store_err <= '0'; + events.alu_ovf <= '0'; + events.alu_uvf <= '0'; + if EX_stage.ctrl.alu_exc_en = '1' then + if EX_stage.alu_flags.ovf = '1' then + events.alu_ovf <= '1'; + end if; + if EX_stage.alu_flags.uvf = '1' then + events.alu_uvf <= '1'; + end if; + end if; + if EX_stage.ctrl.except_en = '1' then + if EX_stage.ctrl.word2_en = '1' then + if EX_stage.va(0) = '1' then + events.data_load_err <= EX_stage.ctrl.dmem_en and not EX_stage.ctrl.dmem_we; + events.data_store_err <= EX_stage.ctrl.dmem_en and EX_stage.ctrl.dmem_we; + end if; + elsif EX_stage.va(1 downto 0) /= "00" then + events.data_load_err <= EX_stage.ctrl.dmem_en and not EX_stage.ctrl.dmem_we; + events.data_store_err <= EX_stage.ctrl.dmem_en and EX_stage.ctrl.dmem_we; + end if; + end if; + end process; + +proc_stage_DMEM_ADDR: + process(clk_1) + variable vaddr : word_t; + begin + if rising_edge(clk_1) and EX_act = '1' then + vaddr := ID_stage.reg_a + extract_simm32(ID_stage.IR); + EX_stage.va <= vaddr; + if ID_stage.cop_stat.RE = '1' then + EX_stage.pa_off <= not vaddr(1 downto 0); + else + EX_stage.pa_off <= vaddr(1 downto 0); + end if; + end if; + end process; + dmem_we <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns; + dmem_re <= not EX_stage.ctrl.dmem_we; + dmem_en <= EX_stage.ctrl.dmem_en and not(ID_stage.cop_stat.exc_strobe) after 1 ns; + dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns; + dmem_addr <= EX_stage.va; + cop_din <= EX_stage.reg_b; + +-------------------------------------------------------------------------- +proc_wptr_mux: + process(EX_stage) + variable opclass : opcode_t; + variable reg_wptr : reg_ptr_t; + begin + + opclass := extract_opc(EX_stage.IR); + case opclass is + when "000000" => + reg_wptr := extract_rd(EX_stage.IR); + when others => + reg_wptr := extract_rt(EX_stage.IR); + end case; + + EX_stage.wreg_we <= EX_stage.reg_write after 1 ns; + if reg_wptr = "00000" then + EX_stage.wreg_we <= '0' after 1 ns; + end if; + + EX_stage.reg_wptr <= reg_wptr after 1 ns; + case EX_stage.ctrl.wptr_srcsel is + when wptr_src_imm => + EX_stage.reg_wptr <= reg_wptr after 1 ns; + + when wptr_src_const => + EX_stage.reg_wptr <= to_unsigned(31, reg_ptr_t'length) after 1 ns; + EX_stage.wreg_we <= '1' after 1 ns; + + when others => null; + end case; + + end process; + +-------------------------------------------------------------------------- +proc_stage_fwd_reg_a: + process(clk_1) + begin + if rising_edge(clk_1) then + if EX_act = '1' then + EX_stage.reg_a <= ID_stage.reg_a; + bcu_op_a <= ID_stage.reg_a; + end if; + end if; + end process; + +proc_stage_fwd_reg_b: + process(clk_1) + begin + if rising_edge(clk_1) then + if EX_act = '1' then + EX_stage.reg_b <= ID_stage.reg_b; + bcu_op_b <= ID_stage.reg_b; + end if; + end if; + end process; + +alu_op1_mux: + process(EX_stage) + variable data : word_t; + begin + + data := EX_stage.reg_a; + +-- case EX_stage.ctrl.alu.op1_src is +-- +-- when alu_src_reg => +-- data := EX_stage.reg_a; +-- +-- when alu_src_muldiv => +-- data := mul_result; +-- +-- when others => null; +-- +-- end case; + + EX_stage.alu_op1 <= data; + + end process; + +alu_op2_mux: + process(clk_1) + variable data : word_t; + begin + + if rising_edge(clk_1) and EX_act = '1' then + data := ID_stage.reg_b; + + case ID_stage.ctrl.alu.op2_src is + + when alu_src_reg => + data := ID_stage.reg_b; + + when alu_src_imm => + data := ID_stage.imm; + + when others => null; + + end case; + + EX_stage.alu_op2 <= data; + end if; + + end process; + +shifter_sa_mux: + process(clk_1) + variable data : shamt_t; + variable data_inv : shamt_t; + + begin + if rising_edge(clk_1) and EX_act = '1' then + data := ID_stage.reg_a(4 downto 0); + case ID_stage.ctrl.shamt2_srcsel is + + when sa_src_reg => + data := ID_stage.reg_a(4 downto 0); + + when sa_src_imm => + data := ID_stage.shamt; + + when others => null; + + end case; + data_inv := not data + 1; + if ID_stage.ctrl.alu.shift_right = '0' then + EX_stage.shift_ctrl.shamt_rnd <= data_inv after 2 ns; + else + EX_stage.shift_ctrl.shamt_rnd <= data after 2 ns; + end if; + EX_stage.shift_ctrl.shamt_nrm <= data after 1 ns; + EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right; + EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith; + end if; + + end process; + +-------------------------------------------------------------------------- +inst_shifter: shifter + GENERIC MAP + ( + data_width => word_t'length + ) + PORT MAP + ( + shift_ctrl => EX_stage.shift_ctrl, + din => EX_stage.reg_b, + dout => EX_stage.alu_op2_s + ); + +inst_alu: alu + GENERIC MAP + ( + data_width => word_t'length + ) + PORT MAP + ( + op1_in => EX_stage.alu_op1, + op2_in => EX_stage.alu_op2, + op2_shifted => EX_stage.alu_op2_s, + ctrl => EX_stage.ctrl.alu, + result => alu_result, + flags => EX_stage.alu_flags + ); + +inst_bcu: bcu + GENERIC MAP + ( + data_width => word_t'length + ) + PORT MAP + ( + op1_in => bcu_op_a, + op2_in => bcu_op_b, + flags => bcu_flags + ); + +-------------------------------------------------------------------------- +-- MEM stage +-------------------------------------------------------------------------- + MEM_act <= not (MEM_nop or MEM_stall); + +proc_stage_MEM_n: + process(clk_1) + begin + if rising_edge(clk_1) then + if MEM_stall = '0' then + MEM_stage.op <= EX_stage.op; + MEM_stage.wreg_we <= EX_stage.wreg_we; + MEM_stage.ctrl <= EX_stage.ctrl; + MEM_stage.pcn <= EX_stage.pcn; + MEM_stage.epc <= EX_stage.epc; + MEM_stage.pa_off <= EX_stage.pa_off; + MEM_stage.reg_wptr <= EX_stage.reg_wptr; + MEM_stage.cop_stat <= EX_stage.cop_stat; + if EX_stage.ctrl.dmem_en = '1' then + MEM_stage.ex_result <= EX_stage.reg_b; + else + MEM_stage.ex_result <= EX_stage.result; + end if; + if MEM_nop = '1' then + MEM_stage.op <= NOP; + MEM_stage.wreg_we <= '0'; + MEM_stage.ctrl <= ctrl_lines_default; + -- MEM_stage.epc <= (others => '0'); + -- MEM_stage.pcn <= (others => '0'); + -- MEM_stage.pa_off <= (others => '0'); + -- MEM_stage.reg_wptr <= (others => '0'); + -- MEM_stage.ex_result <= (others => '0'); + end if; + end if; + end if; + end process; + +proc_stage_MEM_mux: + process(MEM_stage, dmem_din, cop_dout) + variable temp1 : word_t; + variable temp2 : word_t; + variable data : word_t; + variable be : unsigned(3 downto 0); + begin + data := MEM_stage.ex_result; + be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp); + if MEM_stage.cop_stat.cop_access = '1' then + data := cop_dout; + elsif MEM_stage.ctrl.reg_link = '1' then + data := MEM_stage.pcn + 4; + elsif MEM_stage.ctrl.dmem_en = '1' then + temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp); + temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en); + if be(0) = '1' then + data(7 downto 0) := temp2(7 downto 0); + end if; + if be(1) = '1' then + data(15 downto 8) := temp2(15 downto 8); + end if; + if be(2) = '1' then + data(23 downto 16) := temp2(23 downto 16); + end if; + if be(3) = '1' then + data(31 downto 24) := temp2(31 downto 24); + end if; + end if; + MEM_stage.data <= data after 1 ns; + + end process; + +-------------------------------------------------------------------------- +-- WB stage +-------------------------------------------------------------------------- + WB_act <= not (WB_nop or WB_stall); + +proc_stage_WB_p: + process(clk_1) + begin + if rising_edge(clk_1) then + if WB_stall = '0' then + WB_stage.op <= MEM_stage.op; + WB_stage.ctrl <= MEM_stage.ctrl; + WB_stage.wreg_we <= MEM_stage.wreg_we; + WB_stage.reg_wptr <= MEM_stage.reg_wptr; + WB_stage.data <= MEM_stage.data; + WB_stage.epc <= MEM_stage.epc; + if WB_nop = '1' then + WB_stage.op <= NOP; + WB_stage.ctrl <= ctrl_lines_default; + WB_stage.wreg_we <= '0'; + -- WB_stage.epc <= (others => '0'); + -- WB_stage.reg_wptr <= (others => '0'); + -- WB_stage.data <= (others => '0'); + end if; + end if; + end if; + end process; + +-------------------------------------------------------------------------- +end Behavioral; diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd new file mode 100644 index 0000000..222160a --- /dev/null +++ b/projects/mips_sys/src/mips_sys.vhd @@ -0,0 +1,681 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: system test using Xilinx ML-402 + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +use std.textio.all; -- Imports the standard textio package. + +Library UNISIM; +use UNISIM.vcomponents.all; + +library work; +use work.mips_types.all; +--use work.fifo_ctrl_pkg.all; +use work.sdram_config.all; +use work.sdram_types.all; + +ENTITY mips_sys IS +GENERIC +( + sys_freq : integer := 100E6; + ddr_phaseshift : integer := 0; + ddr_frequency_hz : integer := 100E6 +); +PORT +( + sys_rst_n_in : in std_logic; + sys_clk_in : in std_logic; + + -- Buttons and LEDs + sys_btn : in unsigned(4 downto 0); + sys_dip : in unsigned(7 downto 0); + sys_led : out unsigned(8 downto 0); + + -- UART + sys_rx : in std_logic; + sys_tx : out std_logic; + + -- LCD + sys_lcd_d : inout unsigned(3 downto 0); + sys_lcd_e : out std_logic; + sys_lcd_rs : out std_logic; + sys_lcd_rw : out std_logic; + + -- DDR SDRAM + sys_sdr_clk_p : out std_logic; -- ddr_sdram_clock + sys_sdr_clk_n : out std_logic; -- /ddr_sdram_clock + sys_sdr_cke_q : out std_logic; -- clock enable + sys_sdr_cs_qn : out std_logic; -- /chip select + sys_sdr_ras_qn : out std_logic; -- /ras + sys_sdr_cas_qn : out std_logic; -- /cas + sys_sdr_we_qn : out std_logic; -- /write enable + sys_sdr_dm_q : out unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00" + sys_sdr_dqs_q : inout unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write + sys_sdr_ba_q : out unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select + sys_sdr_a_q : out unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus + sys_sdr_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus + sys_sdr_clk_fb : in std_logic; + + -- VGA +-- sys_vga_red : out unsigned(7 downto 0); +-- sys_vga_green : out unsigned(7 downto 0); +-- sys_vga_blue : out unsigned(7 downto 0); +-- sys_vga_blank_n : out std_logic; +-- sys_vga_sync_n : out std_logic; +-- sys_vga_hsync : out std_logic; +-- sys_vga_vsync : out std_logic; +-- sys_vga_clk : out std_logic; + + sys_error : out unsigned(1 downto 0) -- indicates Errors + +); +-- attribute BUFFER_TYPE : string; +-- attribute BUFFER_TYPE of sys_clk_in : signal is "BUFG"; +-- attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb : signal is "BUFG"; + +END mips_sys; + +ARCHITECTURE behavior OF mips_sys IS + + COMPONENT mips_top + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + int : in unsigned(5 downto 0); + mem_valid : in STD_LOGIC; + mem_rdy : in STD_LOGIC; + mem_re : out STD_LOGIC; + mem_en : out STD_LOGIC; + mem_we : out unsigned(3 downto 0); + mem_din : in word_t; + mem_dout : out word_t; + mem_addr : out word_t + + ); + END COMPONENT; + signal int : unsigned(5 downto 0); + signal mem_din : word_t; + signal mem_dout : word_t; + signal mem_addr : word_t; + signal mem_re : std_logic; + signal mem_en : std_logic; + signal mem_we : unsigned(3 downto 0); + signal mem_valid : std_logic; + signal mem_rdy : std_logic; + + COMPONENT rom + Port + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + addr : in word_t; + dout : out word_t + ); + END COMPONENT; + signal rom_data : word_t; + + COMPONENT ram + PORT + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + we : in unsigned(3 downto 0); + addr : in unsigned(31 downto 0); + din : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); + END COMPONENT; + signal ram_data : word_t; + + COMPONENT lcd_port + PORT ( + rst : in std_logic; + clk : in std_logic; + we : in std_logic; + din : in unsigned(7 downto 0); + dout : out unsigned(7 downto 0); + lcd_d : inout unsigned(3 downto 0); + lcd_e : out std_logic; + lcd_rs : out std_logic; + lcd_rw : out std_logic + ); + END COMPONENT; + + COMPONENT uart_tx + Port + ( + data_in : in std_logic_vector(7 downto 0); + write_buffer : in std_logic; + reset_buffer : in std_logic; + en_16_x_baud : in std_logic; + serial_out : out std_logic; + buffer_full : out std_logic; + buffer_half_full : out std_logic; + clk : in std_logic + ); + END COMPONENT; + + COMPONENT uart_rx + Port + ( + serial_in : in std_logic; + data_out : out std_logic_vector(7 downto 0); + read_buffer : in std_logic; + reset_buffer : in std_logic; + en_16_x_baud : in std_logic; + buffer_data_present : out std_logic; + buffer_full : out std_logic; + buffer_half_full : out std_logic; + clk : in std_logic + ); + END COMPONENT; + + signal rst : std_logic; + signal rst_in : std_logic; + signal started_up : std_logic := '1'; + signal clk : std_logic; + + + signal led_reg : unsigned(7 downto 0); + signal cpu_lcd_out_reg, cpu_lcd_in_reg, reg_uart_tx: unsigned(7 downto 0); + signal cpu_lcd_we : std_logic; + signal err_led_reg : unsigned(1 downto 0); + signal btn_ps2_reg : unsigned(7 downto 0); + + -- Signals to form an timer generating an interrupt every microsecond + subtype tick_usec_t is natural range 0 to 99; + signal tick_usec : tick_usec_t; + signal cnt_usec : word_t; + signal cnt_sec : word_t; + signal cnt_usec_preset : word_t; + signal cnt_sec_preset : word_t; + signal cnt_usec_en : std_logic; + signal cnt_usec_we : std_logic; + signal cnt_sec_en : std_logic; + signal cnt_sec_we : std_logic; + + -- Signals for UART connections + signal baud_count : unsigned(7 downto 0); + signal en_16_x_baud : std_logic; + signal reg_we_uart_tx : std_logic; + signal tx_full : std_logic; + signal tx_half_full : std_logic; + signal reg_re_uart_rx : std_logic; + signal reg_uart_rx : std_logic_vector(7 downto 0); + signal rx_data_present : std_logic; + signal rx_full : std_logic; + signal rx_half_full : std_logic; + signal uart_status_port : unsigned(7 downto 0); + signal reg_uart_ctrl : unsigned(7 downto 0); + signal reg_uart_baud : unsigned(7 downto 0); + + -- DDR SDRAM + constant BURST_LEN : natural := 2; + + signal sdr_addr : user_addr_t; + signal sdr_busy_q : std_logic; + signal sdr_udata_in : unsigned(SDR_DATA_WIDTH-1 downto 0); + signal sdr_udata_out_q : unsigned(SDR_DATA_WIDTH-1 downto 0); + signal sdr_udata_vld_q : std_logic; + signal sdr_be : unsigned(SDR_DM_WIDTH-1 downto 0) := "00000000"; + signal sdr_read : std_logic; + signal sdr_en : std_logic; + + signal reg_data : word_t; + signal reg_data_vld : std_logic; + signal reg_en : std_logic; + signal rom_en : std_logic; + signal rom_data_vld : std_logic; + signal ram_en : std_logic; + signal ram_data_vld : std_logic; + signal sdram_en : std_logic; + signal sd_counter : word_t; + signal mem_re_r : std_logic; + signal mem_we_r : unsigned(3 downto 0); + signal mem_dout_r : word_t; + signal mem_addr_r : word_t; + +-- attribute rom_style: string; +-- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED"; +-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; +-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; + +BEGIN + + int <= "0000" & rx_data_present & btn_ps2_reg(4); + rst_in <= not (started_up and sys_rst_n_in); + +en_mux: + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + sdram_en <= '0'; + else + reg_en <= '0'; + rom_en <= '0'; + ram_en <= '0'; +-- sdram_en <= '0'; + + if mem_en = '1' then + mem_re_r <= mem_re; + mem_we_r <= mem_we; + mem_dout_r <= mem_dout; + mem_addr_r <= mem_addr; + if mem_addr(31 downto 28) = X"A" then + reg_en <= '1'; + elsif (mem_addr(31 downto 28) = X"B" and mem_addr(15) = '0') then + rom_en <= '1'; + elsif (mem_addr(31 downto 28) = X"B" and mem_addr(15) = '1') then + ram_en <= '1'; + elsif (mem_addr(31 downto 28) = X"8" or mem_addr(30) = '1') then + sdram_en <= '1'; + end if; + elsif sdr_busy_q = '0' then + sdram_en <= '0'; + end if; + end if; + end if; + end process; + + sdr_addr <= mem_addr_r(24 downto 2) & "0"; + sdr_udata_in <= mem_dout_r & mem_dout_r; + sdr_be <= mem_we_r & mem_we_r; + + sdr_read <= '1'; + sdr_en <= sdram_en and not sdr_busy_q; + +------------------------------------------------------------------ +led_out: + process(rst, clk) + begin + if rst = '1' then + sys_led <= (others => '0'); + sys_error <= (others => '0'); + elsif rising_edge(clk) then + sys_led <= not mem_rdy & led_reg; + sys_error <= err_led_reg; + end if; + end process; + +------------------------------------------------------------------ +btn_ps2_register: + process(clk) + begin + if rising_edge(clk) then + btn_ps2_reg <= "000" & unsigned(sys_btn); + end if; + end process; + +proc_sd_counter: + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + sd_counter <= (others => '0'); + elsif sdr_udata_vld_q = '1' then + sd_counter <= sd_counter + 1; + end if; + end if; + end process; + + mem_valid <= sdr_udata_vld_q or reg_data_vld or rom_data_vld or ram_data_vld; + mem_din <= reg_data when reg_data_vld = '1' else + rom_data when rom_data_vld = '1' else + ram_data when ram_data_vld = '1' else + sdr_udata_out_q(mem_din'left downto mem_din'right); + +------------------------------------------------------------------ +inst_rom: rom + PORT MAP + ( + clk => clk, + ce => rom_en, + addr => mem_addr_r, + dout => rom_data + ); + +inst_ram: ram + PORT MAP + ( + clk => clk, + ce => ram_en, + we => mem_we_r, + addr => mem_addr_r, + din => mem_dout_r, + dout => ram_data + ); + + +ram_read: + process(clk) + begin + if rising_edge(clk) then + ram_data_vld <= '0'; + if ram_en = '1' and mem_re_r = '1' then + ram_data_vld <= '1'; + end if; + end if; + end process; + +rom_read: + process(clk) + begin + if rising_edge(clk) then + rom_data_vld <= '0'; + if rom_en = '1' and mem_re_r = '1' then + rom_data_vld <= '1'; + end if; + end if; + end process; + +registers_read: + process(clk) + begin + if rising_edge(clk) then + reg_data_vld <= '0'; + reg_re_uart_rx <= '0'; + if reg_en = '1' and mem_re_r = '1' then + reg_data_vld <= '1'; + reg_data <= (others => '0'); + case mem_addr_r(5 downto 2) is + + when "0000" => null; + + when "0001" => + reg_re_uart_rx <= mem_re_r; + reg_data(7 downto 0) <= unsigned(reg_uart_rx); + + when "0010" => + reg_data(7 downto 0) <= uart_status_port; + reg_data(15 downto 8) <= reg_uart_baud; + reg_data(23 downto 16) <= btn_ps2_reg; + reg_data(31 downto 24) <= cpu_lcd_in_reg; + + when "0100" => + reg_data <= cnt_usec; + + when "0101" => + reg_data <= cnt_sec; + + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------ +registers_write: + process(clk) + begin + if rising_edge(clk) then + cpu_lcd_we <= '0'; + reg_we_uart_tx <= '0'; + cnt_usec_we <= '0'; + cnt_sec_we <= '0'; + if rst = '1' then + led_reg <= (others => '0'); + err_led_reg <= (others => '0'); + cpu_lcd_out_reg <= (others => '0'); + reg_uart_baud <= to_unsigned(53, 8); + reg_uart_ctrl <= to_unsigned(0, 8); + elsif reg_en = '1' then + case mem_addr_r(5 downto 2) is + + when "0000" => + if mem_we_r(0) = '1' then + led_reg(7 downto 0) <= mem_dout_r(7 downto 0); + end if; + if mem_we_r(3) = '1' then + err_led_reg <= mem_dout_r(31 downto 30); + end if; + + when "0001" => + if mem_we_r(0) = '1' then + reg_we_uart_tx <= '1'; + reg_uart_tx <= mem_dout_r(7 downto 0); + end if; + + when "0010" => + if mem_we_r(0) = '1' then + reg_uart_ctrl <= mem_dout_r(7 downto 0); + end if; + if mem_we_r(1) = '1' then + reg_uart_baud <= mem_dout_r(15 downto 8); + end if; + if mem_we_r(3) = '1' then + cpu_lcd_we <= '1'; + cpu_lcd_out_reg <= mem_dout_r(31 downto 24); + end if; + + when "0100" => + if mem_we_r(3) = '1' then + cnt_usec_we <= '1'; + cnt_usec_preset <= mem_dout_r; + end if; + + when "0101" => + if mem_we_r(3) = '1' then + cnt_sec_we <= '1'; + cnt_sec_preset <= mem_dout_r; + end if; + + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------ + mem_rdy <= not sdr_busy_q; + +------------------------------------------------------------------ +inst_mips_top: mips_top + PORT MAP + ( + rst => rst, + clk => clk, + int => int, + mem_valid => mem_valid, + mem_rdy => mem_rdy, + mem_en => mem_en, + mem_re => mem_re, + mem_we => mem_we, + mem_din => mem_din, + mem_dout => mem_dout, + mem_addr => mem_addr + ); + +inst_lcd_port: lcd_port + PORT MAP + ( + rst => rst, + clk => clk, + we => cpu_lcd_we, + din => cpu_lcd_out_reg, + dout => cpu_lcd_in_reg, + lcd_d => sys_lcd_d, + lcd_e => sys_lcd_e, + lcd_rs => sys_lcd_rs, + lcd_rw => sys_lcd_rw + ); + +inst_uart_tx: uart_tx + port map + ( + data_in => std_logic_vector(reg_uart_tx), + write_buffer => reg_we_uart_tx, + reset_buffer => rst, + en_16_x_baud => en_16_x_baud, + serial_out => sys_tx, + buffer_full => tx_full, + buffer_half_full => tx_half_full, + clk => clk + ); + +inst_uart_rx: uart_rx + port map + ( + serial_in => sys_rx, + data_out => reg_uart_rx, + read_buffer => reg_re_uart_rx, + reset_buffer => rst, + en_16_x_baud => en_16_x_baud, + buffer_data_present => rx_data_present, + buffer_full => rx_full, + buffer_half_full => rx_half_full, + clk => clk + ); + + uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full; + +tick_usec_timer: + process(clk) + begin + if clk'event and clk='1' then + cnt_usec_en <= '0'; + if rst = '1' then + tick_usec <= 0; + cnt_usec_en <= '0'; + elsif tick_usec = tick_usec_t'high then + tick_usec <= 0; + cnt_usec_en <= '1'; + else + tick_usec <= tick_usec + 1; + end if; + end if; + end process; + +cnt_usec_timer: + process(clk) + begin + if clk'event and clk='1' then + cnt_sec_en <= '0'; + if rst = '1' then + cnt_usec <= (others => '0'); + cnt_sec_en <= '0'; + elsif cnt_usec_we = '1' then + cnt_usec <= cnt_usec_preset; + elsif cnt_usec_en = '1' then + if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then + cnt_usec <= (others => '0'); + cnt_sec_en <= '1'; + else + cnt_usec <= cnt_usec + 1; + end if; + end if; + end if; + end process; + +cnt_sec_timer: + process(clk) + begin + if clk'event and clk='1' then + if rst = '1' then + cnt_sec <= (others => '0'); + elsif cnt_sec_we = '1' then + cnt_sec <= cnt_sec_preset; + elsif cnt_sec_en = '1' then + cnt_sec <= cnt_sec + 1; + end if; + end if; + end process; + +baud_timer: + process(clk) + begin + if clk'event and clk='1' then + if rst = '1' then + baud_count <= (others => '0'); + elsif baud_count = reg_uart_baud then + baud_count <= (others => '0'); + en_16_x_baud <= '1'; + else + baud_count <= baud_count + 1; + en_16_x_baud <= '0'; + end if; + end if; + end process; + + -- DDR SDRAM Controller Core + inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend + Generic map + ( + BL => BURST_LEN, + read_phaseshift => ddr_phaseshift, + f_sysclk => ddr_frequency_hz, + fifo_depth => 4 + ) + Port map + ( + + sys_rst_in => rst_in, + sys_clk_in => sys_clk_in, + + sys_rst_out => rst, + sys_clk_out => clk, + sys_clk_fb => sys_sdr_clk_fb, + + busy => sdr_busy_q, + en => sdr_en, + r_wn => mem_re_r, + be => sdr_be, + addr => sdr_addr, + din => sdr_udata_in, + dout => sdr_udata_out_q, + dout_re => sdr_read, + dout_vld => sdr_udata_vld_q, + + -- SDRAM signals + sd_clk_p => sys_sdr_clk_p, + sd_clk_n => sys_sdr_clk_n, + sd_cke => sys_sdr_cke_q, + sd_cs_n => sys_sdr_cs_qn, + sd_cas_n => sys_sdr_cas_qn, + sd_ras_n => sys_sdr_ras_qn, + sd_we_n => sys_sdr_we_qn, + sd_addr => sys_sdr_a_q, + sd_ba => sys_sdr_ba_q, + sd_dm => sys_sdr_dm_q, + sd_dqs => sys_sdr_dqs_q, + sd_data => sys_sdr_data + + ); + + STARTUP_VIRTEX4_inst : STARTUP_VIRTEX4 + port map ( + EOS => started_up, -- End of Startup 1-bit output + CLK => open, -- Clock input for start-up sequence + GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name) + GTS => '0', -- Global 3-state input (GTS cannot be used for the port name) + USRCCLKO => '0', -- USRCCLKO 1-bit input + USRCCLKTS => '0', -- USRCCLKTS 1-bit input + USRDONEO => '0', -- USRDONEO 1-bit input + USRDONETS => '0' -- USRDONETS 1-bit input + ); + + ------------------------------------------------------------------ +END; diff --git a/projects/mips_sys/src/mips_sys_cfg.vhd b/projects/mips_sys/src/mips_sys_cfg.vhd new file mode 100644 index 0000000..6d279b3 --- /dev/null +++ b/projects/mips_sys/src/mips_sys_cfg.vhd @@ -0,0 +1,19 @@ +library IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +configuration cpu_irom of cpu_embedded is + for rtl + for inst_irom : irom + use entity work.irom(loadable); + end for; + end for; +end configuration cpu_irom; + +configuration system_xrom of systest is + for behavior + for inst_xrom : xrom + use entity work.xrom(loadable); + end for; + end for; +end configuration system_xrom; diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd new file mode 100644 index 0000000..32e3976 --- /dev/null +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -0,0 +1,716 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: system test using Xilinx ML-402 + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +use std.textio.all; -- Imports the standard textio package. + +Library UNISIM; +use UNISIM.vcomponents.all; + +library work; +use work.mips_types.all; +--use work.fifo_ctrl_pkg.all; +use work.sdram_config.all; +use work.sdram_types.all; + +ENTITY mips_sys IS +GENERIC +( + sys_freq : integer := 100E6; + ddr_phaseshift : integer := 0; + ddr_frequency_hz : integer := 100E6 +); +PORT +( + sys_rst_n_in : in std_logic; + sys_clk_in : in std_logic; + + -- Buttons and LEDs + sys_btn : in unsigned(4 downto 0); + sys_dip : in unsigned(7 downto 0); + sys_led : out unsigned(8 downto 0); + + -- UART + sys_rx : in std_logic; + sys_tx : out std_logic; + + -- User ROM + sys_user_rom_addr : out word_t; + sys_user_rom_din : in word_t; + sys_user_rom_clk : out std_logic; + sys_user_rom_en : out std_logic; + + -- LCD + sys_lcd_d : inout unsigned(3 downto 0); + sys_lcd_e : out std_logic; + sys_lcd_rs : out std_logic; + sys_lcd_rw : out std_logic; + + -- DDR SDRAM + sys_sdr_clk_p : out std_logic; -- ddr_sdram_clock + sys_sdr_clk_n : out std_logic; -- /ddr_sdram_clock + sys_sdr_cke_q : out std_logic; -- clock enable + sys_sdr_cs_qn : out std_logic; -- /chip select + sys_sdr_ras_qn : out std_logic; -- /ras + sys_sdr_cas_qn : out std_logic; -- /cas + sys_sdr_we_qn : out std_logic; -- /write enable + sys_sdr_dm_q : out unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00" + sys_sdr_dqs_q : inout unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write + sys_sdr_ba_q : out unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select + sys_sdr_a_q : out unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus + sys_sdr_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus + sys_sdr_clk_fb : in std_logic; + + -- VGA +-- sys_vga_red : out unsigned(7 downto 0); +-- sys_vga_green : out unsigned(7 downto 0); +-- sys_vga_blue : out unsigned(7 downto 0); +-- sys_vga_blank_n : out std_logic; +-- sys_vga_sync_n : out std_logic; +-- sys_vga_hsync : out std_logic; +-- sys_vga_vsync : out std_logic; +-- sys_vga_clk : out std_logic; + + sys_error : out unsigned(1 downto 0) -- indicates Errors + +); +-- attribute BUFFER_TYPE : string; +-- attribute BUFFER_TYPE of sys_clk_in : signal is "BUFG"; +-- attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb : signal is "BUFG"; + +END mips_sys; + +ARCHITECTURE behavior OF mips_sys IS + + COMPONENT mips_top + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + int : in unsigned(5 downto 0); + mem_valid : in STD_LOGIC; + mem_rdy : in STD_LOGIC; + mem_re : out STD_LOGIC; + mem_en : out STD_LOGIC; + mem_we : out unsigned(3 downto 0); + mem_din : in word_t; + mem_dout : out word_t; + mem_addr : out word_t + + ); + END COMPONENT; + signal int : unsigned(5 downto 0); + signal mem_din : word_t; + signal mem_dout : word_t; + signal mem_addr : word_t; + signal mem_re : std_logic; + signal mem_en : std_logic; + signal mem_we : unsigned(3 downto 0); + signal mem_valid : std_logic; + signal mem_rdy : std_logic; + + COMPONENT rom + Port + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + addr : in word_t; + dout : out word_t + ); + END COMPONENT; + signal rom_data : word_t; + + COMPONENT ram + PORT + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + we : in unsigned(3 downto 0); + addr : in unsigned(31 downto 0); + din : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); + END COMPONENT; + signal ram_data : word_t; + + COMPONENT lcd_port + PORT ( + rst : in std_logic; + clk : in std_logic; + we : in std_logic; + din : in unsigned(7 downto 0); + dout : out unsigned(7 downto 0); + lcd_d : inout unsigned(3 downto 0); + lcd_e : out std_logic; + lcd_rs : out std_logic; + lcd_rw : out std_logic + ); + END COMPONENT; + + COMPONENT uart_tx + Port + ( + data_in : in std_logic_vector(7 downto 0); + write_buffer : in std_logic; + reset_buffer : in std_logic; + en_16_x_baud : in std_logic; + serial_out : out std_logic; + buffer_full : out std_logic; + buffer_half_full : out std_logic; + clk : in std_logic + ); + END COMPONENT; + + COMPONENT uart_rx + Port + ( + serial_in : in std_logic; + data_out : out std_logic_vector(7 downto 0); + read_buffer : in std_logic; + reset_buffer : in std_logic; + en_16_x_baud : in std_logic; + buffer_data_present : out std_logic; + buffer_full : out std_logic; + buffer_half_full : out std_logic; + clk : in std_logic + ); + END COMPONENT; + + signal rst : std_logic; + signal rst_in : std_logic; + signal started_up : std_logic := '1'; + signal clk : std_logic; + + + signal led_reg : unsigned(7 downto 0); + signal cpu_lcd_out_reg, cpu_lcd_in_reg, reg_uart_tx: unsigned(7 downto 0); + signal cpu_lcd_we : std_logic; + signal err_led_reg : unsigned(1 downto 0); + signal btn_ps2_reg : unsigned(7 downto 0); + + -- Signals to form an timer generating an interrupt every microsecond + subtype tick_usec_t is natural range 0 to 99; + signal tick_usec : tick_usec_t; + signal cnt_usec : word_t; + signal cnt_sec : word_t; + signal cnt_usec_preset : word_t; + signal cnt_sec_preset : word_t; + signal cnt_usec_en : std_logic; + signal cnt_usec_we : std_logic; + signal cnt_sec_en : std_logic; + signal cnt_sec_we : std_logic; + + -- Signals for UART connections + signal baud_count : unsigned(7 downto 0); + signal en_16_x_baud : std_logic; + signal reg_we_uart_tx : std_logic; + signal tx_full : std_logic; + signal tx_half_full : std_logic; + signal reg_re_uart_rx : std_logic; + signal reg_uart_rx : std_logic_vector(7 downto 0); + signal rx_data_present : std_logic; + signal rx_full : std_logic; + signal rx_half_full : std_logic; + signal uart_status_port : unsigned(7 downto 0); + signal reg_uart_ctrl : unsigned(7 downto 0); + signal reg_uart_baud : unsigned(7 downto 0); + + -- DDR SDRAM + constant BURST_LEN : natural := 2; + subtype sdr_buf_t is unsigned(SDR_DATA_WIDTH-1 downto 0); + signal sdr_buf_in, sdr_vga_data : sdr_buf_t := (others => '0'); + + signal sdr_addr : user_addr_t; + signal sdr_busy_q : std_logic; + signal sdr_udata_in : unsigned(SDR_DATA_WIDTH-1 downto 0); + signal sdr_udata_req_wr : std_logic; + signal sdr_udata_out_q : unsigned(SDR_DATA_WIDTH-1 downto 0); + signal sdr_udata_vld_q : std_logic; + signal sdr_be : unsigned(SDR_DM_WIDTH-1 downto 0) := "00000000"; + signal sdr_read : std_logic; + signal sdr_en : std_logic; + + signal reg_data : word_t; + signal reg_data_vld : std_logic; + signal reg_en : std_logic; + signal rom_en : std_logic; + signal rom_data_vld : std_logic; + signal ram_en : std_logic; + signal ram_data_vld : std_logic; + signal urom_en : std_logic; + signal urom_data_vld : std_logic; + signal sdram_en : std_logic; + signal sd_counter : word_t; + signal mem_re_r : std_logic; + signal mem_we_r : unsigned(3 downto 0); + signal mem_dout_r : word_t; + signal mem_addr_r : word_t; + +-- attribute rom_style: string; +-- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED"; +-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; +-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; + + type sd_ctrl_state_t is (s_sd_idle, s_sd_cpu_read, s_sd_cpu_read_fin, s_sd_cpu_write, s_sd_cpu_write_fin); + signal st, stn : sd_ctrl_state_t; + +BEGIN + + int <= "0000" & rx_data_present & btn_ps2_reg(4); + rst_in <= not (started_up and sys_rst_n_in); + +en_mux: + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + sdram_en <= '0'; + else + urom_en <= '0'; + reg_en <= '0'; + rom_en <= '0'; + ram_en <= '0'; +-- sdram_en <= '0'; + + if mem_en = '1' then + mem_re_r <= mem_re; + mem_we_r <= mem_we; + mem_dout_r <= mem_dout; + mem_addr_r <= mem_addr; + + if mem_addr(31 downto 28) = X"0" then + urom_en <= '1'; + elsif mem_addr(31 downto 28) = X"A" then + reg_en <= '1'; + elsif (mem_addr(31 downto 28) = X"B" and mem_addr(15) = '0') then + rom_en <= '1'; + elsif (mem_addr(31 downto 28) = X"B" and mem_addr(15) = '1') then + ram_en <= '1'; + elsif (mem_addr(31 downto 28) = X"8" or mem_addr(30) = '1') then + sdram_en <= '1'; + end if; + elsif sdr_en = '1' then + sdram_en <= '0'; + end if; + end if; + end if; + end process; + + sys_user_rom_addr <= mem_addr_r; + sys_user_rom_clk <= clk; + sys_user_rom_en <= urom_en; + + sdr_addr <= mem_addr_r(24 downto 2) & "0"; + + sdr_udata_in <= mem_dout_r & mem_dout_r; + sdr_be <= mem_we_r & mem_we_r; + + sdr_read <= '1'; + sdr_en <= sdram_en and not sdr_busy_q; + +------------------------------------------------------------------ +led_out: + process(rst, clk) + begin + if rst = '1' then + sys_led <= (others => '0'); + sys_error <= (others => '0'); + elsif rising_edge(clk) then + sys_led <= not mem_rdy & led_reg; + sys_error <= err_led_reg; + end if; + end process; + +------------------------------------------------------------------ +btn_ps2_register: + process(clk) + begin + if rising_edge(clk) then + btn_ps2_reg <= "000" & unsigned(sys_btn); + end if; + end process; + +proc_sd_counter: + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + sd_counter <= (others => '0'); + elsif sdr_udata_vld_q = '1' then + sd_counter <= sd_counter + 1; + end if; + end if; + end process; + + mem_valid <= sdr_udata_vld_q or reg_data_vld or rom_data_vld or urom_data_vld or ram_data_vld; + mem_din <= sdr_udata_out_q(mem_din'left downto mem_din'right) when sdr_udata_vld_q = '1' else + reg_data when reg_data_vld = '1' else + rom_data when rom_data_vld = '1' else + sys_user_rom_din when urom_data_vld = '1' else + ram_data when ram_data_vld = '1'; + +------------------------------------------------------------------ +inst_rom: rom + PORT MAP + ( + clk => clk, + ce => rom_en, + addr => mem_addr_r, + dout => rom_data + ); + +inst_ram: ram + PORT MAP + ( + clk => clk, + ce => ram_en, + we => mem_we_r, + addr => mem_addr_r, + din => mem_dout_r, + dout => ram_data + ); + + +ram_read: + process(clk) + begin + if rising_edge(clk) then + ram_data_vld <= '0'; + if ram_en = '1' and mem_re_r = '1' then + ram_data_vld <= '1'; + end if; + end if; + end process; + +rom_read: + process(clk) + begin + if rising_edge(clk) then + rom_data_vld <= '0'; + if rom_en = '1' and mem_re_r = '1' then + rom_data_vld <= '1'; + end if; + end if; + end process; + +urom_read: + process(clk) + begin + if rising_edge(clk) then + urom_data_vld <= '0'; + if urom_en = '1' then + urom_data_vld <= '1'; + end if; + end if; + end process; + +registers_read: + process(clk) + begin + if rising_edge(clk) then + reg_data_vld <= '0'; + reg_re_uart_rx <= '0'; + if reg_en = '1' and mem_re_r = '1' then + reg_data_vld <= '1'; + reg_data <= (others => '0'); + case mem_addr_r(5 downto 2) is + + when "0000" => null; + + when "0001" => + reg_re_uart_rx <= mem_re_r; + reg_data(7 downto 0) <= unsigned(reg_uart_rx); + + when "0010" => + reg_data(7 downto 0) <= uart_status_port; + reg_data(15 downto 8) <= reg_uart_baud; + reg_data(23 downto 16) <= btn_ps2_reg; + reg_data(31 downto 24) <= cpu_lcd_in_reg; + + when "0100" => + reg_data <= cnt_usec; + + when "0101" => + reg_data <= cnt_sec; + + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------ +registers_write: + process(clk) + begin + if rising_edge(clk) then + cpu_lcd_we <= '0'; + reg_we_uart_tx <= '0'; + cnt_usec_we <= '0'; + cnt_sec_we <= '0'; + if rst = '1' then + led_reg <= (others => '0'); + err_led_reg <= (others => '0'); + cpu_lcd_out_reg <= (others => '0'); + reg_uart_baud <= to_unsigned(53, 8); + reg_uart_ctrl <= to_unsigned(0, 8); + elsif reg_en = '1' then + case mem_addr_r(5 downto 2) is + + when "0000" => + if mem_we_r(0) = '1' then + led_reg(7 downto 0) <= mem_dout_r(7 downto 0); + end if; + if mem_we_r(3) = '1' then + err_led_reg <= mem_dout_r(31 downto 30); + end if; + + when "0001" => + if mem_we_r(0) = '1' then + reg_we_uart_tx <= '1'; + reg_uart_tx <= mem_dout_r(7 downto 0); + end if; + + when "0010" => + if mem_we_r(0) = '1' then + reg_uart_ctrl <= mem_dout_r(7 downto 0); + end if; + if mem_we_r(1) = '1' then + reg_uart_baud <= mem_dout_r(15 downto 8); + end if; + if mem_we_r(3) = '1' then + cpu_lcd_we <= '1'; + cpu_lcd_out_reg <= mem_dout_r(31 downto 24); + end if; + + when "0100" => + if mem_we_r(3) = '1' then + cnt_usec_we <= '1'; + cnt_usec_preset <= mem_dout_r; + end if; + + when "0101" => + if mem_we_r(3) = '1' then + cnt_sec_we <= '1'; + cnt_sec_preset <= mem_dout_r; + end if; + + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------ + mem_rdy <= not sdr_busy_q; + +------------------------------------------------------------------ +inst_mips_top: mips_top + PORT MAP + ( + rst => rst, + clk => clk, + int => int, + mem_valid => mem_valid, + mem_rdy => mem_rdy, + mem_en => mem_en, + mem_re => mem_re, + mem_we => mem_we, + mem_din => mem_din, + mem_dout => mem_dout, + mem_addr => mem_addr + ); + +inst_lcd_port: lcd_port + PORT MAP + ( + rst => rst, + clk => clk, + we => cpu_lcd_we, + din => cpu_lcd_out_reg, + dout => cpu_lcd_in_reg, + lcd_d => sys_lcd_d, + lcd_e => sys_lcd_e, + lcd_rs => sys_lcd_rs, + lcd_rw => sys_lcd_rw + ); + +inst_uart_tx: uart_tx + port map + ( + data_in => std_logic_vector(reg_uart_tx), + write_buffer => reg_we_uart_tx, + reset_buffer => rst, + en_16_x_baud => en_16_x_baud, + serial_out => sys_tx, + buffer_full => tx_full, + buffer_half_full => tx_half_full, + clk => clk + ); + +inst_uart_rx: uart_rx + port map + ( + serial_in => sys_rx, + data_out => reg_uart_rx, + read_buffer => reg_re_uart_rx, + reset_buffer => rst, + en_16_x_baud => en_16_x_baud, + buffer_data_present => rx_data_present, + buffer_full => rx_full, + buffer_half_full => rx_half_full, + clk => clk + ); + + uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full; + +tick_usec_timer: + process(clk) + begin + if clk'event and clk='1' then + cnt_usec_en <= '0'; + if rst = '1' then + tick_usec <= 0; + cnt_usec_en <= '0'; + elsif tick_usec = tick_usec_t'high then + tick_usec <= 0; + cnt_usec_en <= '1'; + else + tick_usec <= tick_usec + 1; + end if; + end if; + end process; + +cnt_usec_timer: + process(clk) + begin + if clk'event and clk='1' then + cnt_sec_en <= '0'; + if rst = '1' then + cnt_usec <= (others => '0'); + cnt_sec_en <= '0'; + elsif cnt_usec_we = '1' then + cnt_usec <= cnt_usec_preset; + elsif cnt_usec_en = '1' then + if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then + cnt_usec <= (others => '0'); + cnt_sec_en <= '1'; + else + cnt_usec <= cnt_usec + 1; + end if; + end if; + end if; + end process; + +cnt_sec_timer: + process(clk) + begin + if clk'event and clk='1' then + if rst = '1' then + cnt_sec <= (others => '0'); + elsif cnt_sec_we = '1' then + cnt_sec <= cnt_sec_preset; + elsif cnt_sec_en = '1' then + cnt_sec <= cnt_sec + 1; + end if; + end if; + end process; + +baud_timer: + process(clk) + begin + if clk'event and clk='1' then + if rst = '1' then + baud_count <= (others => '0'); + elsif baud_count = reg_uart_baud then + baud_count <= (others => '0'); + en_16_x_baud <= '1'; + else + baud_count <= baud_count + 1; + en_16_x_baud <= '0'; + end if; + end if; + end process; + + -- DDR SDRAM Controller Core + inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend + Generic map + ( + BL => BURST_LEN, + read_phaseshift => ddr_phaseshift, + f_sysclk => ddr_frequency_hz, + fifo_depth => 4 + ) + Port map + ( + + sys_rst_in => rst_in, + sys_clk_in => sys_clk_in, + + sys_rst_out => rst, + sys_clk_out => clk, + sys_clk_fb => sys_sdr_clk_fb, + + busy => sdr_busy_q, + en => sdr_en, + r_wn => mem_re_r, + be => sdr_be, + addr => sdr_addr, + din => sdr_udata_in, + dout => sdr_udata_out_q, + dout_re => sdr_read, + dout_vld => sdr_udata_vld_q, + + -- SDRAM signals + sd_clk_p => sys_sdr_clk_p, + sd_clk_n => sys_sdr_clk_n, + sd_cke => sys_sdr_cke_q, + sd_cs_n => sys_sdr_cs_qn, + sd_cas_n => sys_sdr_cas_qn, + sd_ras_n => sys_sdr_ras_qn, + sd_we_n => sys_sdr_we_qn, + sd_addr => sys_sdr_a_q, + sd_ba => sys_sdr_ba_q, + sd_dm => sys_sdr_dm_q, + sd_dqs => sys_sdr_dqs_q, + sd_data => sys_sdr_data + + ); + + STARTUP_VIRTEX4_inst : STARTUP_VIRTEX4 + port map ( + EOS => started_up, -- End of Startup 1-bit output + CLK => open, -- Clock input for start-up sequence + GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name) + GTS => '0', -- Global 3-state input (GTS cannot be used for the port name) + USRCCLKO => '0', -- USRCCLKO 1-bit input + USRCCLKTS => '0', -- USRCCLKTS 1-bit input + USRDONEO => '0', -- USRDONEO 1-bit input + USRDONETS => '0' -- USRDONETS 1-bit input + ); + + ------------------------------------------------------------------ +END; diff --git a/projects/mips_sys/src/ram_ld.vhd b/projects/mips_sys/src/ram_ld.vhd new file mode 100644 index 0000000..17879e1 --- /dev/null +++ b/projects/mips_sys/src/ram_ld.vhd @@ -0,0 +1,173 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: The ROM file for use in your VHDL design +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +ENTITY ram IS + Port + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + we : in unsigned(3 downto 0); + addr : in unsigned(31 downto 0); + din : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); +END ram; + +ARCHITECTURE behavior OF ram IS + + COMPONENT dpram_2w2r + Generic + ( + addr_width : integer; + data_width : integer + ); + Port + ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + we_b : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + din_b : in unsigned (data_width-1 downto 0); + dout_a : out unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); + END COMPONENT; + + signal jtag_clk : STD_LOGIC; + signal jtag_we : unsigned(3 downto 0); + signal jtag_addr : unsigned (15 downto 0); + signal jtag_dout : unsigned (31 downto 0); + signal jtag_din : unsigned (31 downto 0); + signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; + signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; + signal user_regi, user_rego : unsigned (47 downto 0); + +BEGIN + +gen_sram: + for i in 0 to 3 generate + begin + inst_dpram_2w2r : dpram_2w2r + GENERIC MAP + ( + addr_width => 11, + data_width => 8 + ) + PORT MAP + ( + clk_a => clk, + en_a => ce, + we_a => we(i), + addr_a => addr(12 downto 2), + din_a => din((i+1)*8-1 downto i*8), + dout_a => dout((i+1)*8-1 downto i*8), + + clk_b => jtag_clk, + en_b => jtag_we(i), + we_b => jtag_we(i), + addr_b => jtag_addr(10 downto 0), + din_b => jtag_din((i+1)*8-1 downto i*8), + dout_b => jtag_dout((i+1)*8-1 downto i*8) + ); + end generate; + +-------------------------------------------------------------------------- +-- Virtex-4: JTAG Loader +-------------------------------------------------------------------------- + i00_BUFG : BUFG + port map + ( + O => bs_clk1, + I => bs_clk0 + ); + + i01_BUFG : BUFG + port map + ( + O => bs_update1, + I => bs_update0 + ); + + BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 + generic map + ( + JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) + ) + port map + ( + CAPTURE => bs_capture, -- CAPTURE output from TAP controller + DRCK => bs_clk0, -- Data register output for USER functions + RESET => bs_rst, -- Reset output from TAP controller + SEL => bs_sel, -- USER active output + SHIFT => bs_shift, -- SHIFT output from TAP controller + TDI => bs_tdi, -- TDI output from TAP controller + UPDATE => bs_update0, -- UPDATE output from TAP controller + TDO => bs_tdo -- Data input for USER function + ); + + jtag_addr <= user_regi(user_regi'left downto jtag_dout'length); + jtag_din <= user_regi(jtag_dout'length-1 downto 0); + jtag_clk <= bs_update1; + jtag_we <= (3 downto 0 => bs_sel); + +sipo: + process (bs_rst, bs_clk1, bs_tdi, bs_shift) + begin + if bs_rst = '1' then + user_regi <= (others => '0'); + elsif rising_edge(bs_clk1) then + if bs_shift = '1' then + user_regi <= bs_tdi & user_regi(user_regi'left downto 1); + end if; + end if; + end process; + +piso: + process (bs_rst, bs_clk1, bs_shift, user_rego) + begin + bs_tdo <= user_rego(0); + if bs_rst = '1' then + user_rego <= (others => '0'); + elsif rising_edge(bs_clk1) then + if bs_shift = '1' then + user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); + else + user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout; + end if; + end if; + end process; + +-------------------------------------------------------------------------- +end behavior; diff --git a/projects/mips_sys/src/ram_sim.vhd b/projects/mips_sys/src/ram_sim.vhd new file mode 100644 index 0000000..6d26672 --- /dev/null +++ b/projects/mips_sys/src/ram_sim.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: The ROM file for use in your VHDL design +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + + +ENTITY ram IS + Generic + ( + word_addr_width : integer := 6 + ); + Port + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + we : in unsigned(3 downto 0); + addr : in unsigned(31 downto 0); + din : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); +END ram; + +ARCHITECTURE behavior OF ram IS + + constant depth : natural := 2**word_addr_width; + + type sram_t is array (0 to depth-1) of unsigned(31 downto 0); + + function sram_clear return sram_t is + + variable result : sram_t; + begin + for i in 0 to sram_t'length-1 loop + result(i) := (others => '0'); + end loop; + return result; + end sram_clear; + + signal sram : sram_t := sram_clear; + +BEGIN + + +SRAM_RW: + process(clk) + variable index : natural range 0 to depth-1; + begin + if rising_edge(clk) and ce = '1' then + index := to_integer(addr(word_addr_width+1 downto 2)); + if we(0) = '1' then + sram(index)(7 downto 0) <= din(7 downto 0); + end if; + if we(1) = '1' then + sram(index)(15 downto 8) <= din(15 downto 8); + end if; + if we(2) = '1' then + sram(index)(23 downto 16) <= din(23 downto 16); + end if; + if we(3) = '1' then + sram(index)(31 downto 24) <= din(31 downto 24); + end if; + dout <= sram(index); + end if; + end process; + +end behavior; diff --git a/projects/mips_sys/src/sdram_config.vhd b/projects/mips_sys/src/sdram_config.vhd new file mode 100644 index 0000000..1bdf8e0 --- /dev/null +++ b/projects/mips_sys/src/sdram_config.vhd @@ -0,0 +1,74 @@ +------------------------------------------------------------------------- +-- Project: SDRAM controller +-- This file: User SDRAM component adjustments +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +library IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +package sdram_config is + + constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width + constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module + constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM + constant DDR_ROW_ADDR_WIDTH : positive := 13; -- + constant DDR_COL_ADDR_WIDTH : positive := 9; -- + + constant LMR_REG_BASE : natural := 0; + constant LMR_REG_EXTENDED : natural := 1; + constant LMR_OP_NORMAL : natural := 0; + constant LMR_OP_RES_DLL : natural := 2; + constant LMR_BT_SEQ : natural := 0; + constant LMR_BT_ILVD : natural := 1; + constant LMR_BL2 : natural := 1; + constant LMR_BL4 : natural := 2; + constant LMR_BL8 : natural := 3; + constant LMR_CL2 : natural := 2; + constant LMR_CL3 : natural := 3; + constant LMR_CL2_5 : natural := 6; + + -- DDR SDRAM Hardware defined constants + constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) + constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) + constant ENABLE_PRE_ALL : std_logic := '1'; + constant ENABLE_AUTO_PRE : std_logic := '0'; + + -- DDR-SDR TIMING constants ------------------------------------------------------------------ + -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh + constant REFRESH_INTERVAL : real := 7.8125; -- us + + -- These values are for your SDRAM part (see datasheet) + constant TCAS : positive := 2; -- CAS latency [clocks] + constant TRP : positive := 2; -- precharge command period + constant TRAS : positive := 5; -- active to precharge delay + constant TRFC : positive := 8; -- auto refresh command period + constant TMRD : positive := 2; -- load mode register command cylce time + constant TRCD : positive := 2; -- active to read or write delay ! + constant TWR : positive := 2; -- write recovery time + + constant PWR_UP_WAIT : natural := 222; -- µs + + subtype user_tag_t is unsigned(3 downto 0); + + ---------------------------------------------------------------------------------------------- + +end sdram_config; diff --git a/projects/mips_sys/src/sdram_config_sim.vhd b/projects/mips_sys/src/sdram_config_sim.vhd new file mode 100644 index 0000000..f698b29 --- /dev/null +++ b/projects/mips_sys/src/sdram_config_sim.vhd @@ -0,0 +1,74 @@ +------------------------------------------------------------------------- +-- Project: SDRAM controller +-- This file: User SDRAM component adjustments +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +library IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +package sdram_config is + + constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width + constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module + constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM + constant DDR_ROW_ADDR_WIDTH : positive := 13; -- + constant DDR_COL_ADDR_WIDTH : positive := 9; -- + + constant LMR_REG_BASE : natural := 0; + constant LMR_REG_EXTENDED : natural := 1; + constant LMR_OP_NORMAL : natural := 0; + constant LMR_OP_RES_DLL : natural := 2; + constant LMR_BT_SEQ : natural := 0; + constant LMR_BT_ILVD : natural := 1; + constant LMR_BL2 : natural := 1; + constant LMR_BL4 : natural := 2; + constant LMR_BL8 : natural := 3; + constant LMR_CL2 : natural := 2; + constant LMR_CL3 : natural := 3; + constant LMR_CL2_5 : natural := 6; + + -- DDR SDRAM Hardware defined constants + constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) + constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) + constant ENABLE_PRE_ALL : std_logic := '1'; + constant ENABLE_AUTO_PRE : std_logic := '0'; + + -- DDR-SDR TIMING constants ------------------------------------------------------------------ + -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh + constant REFRESH_INTERVAL : real := 7.8125; -- us + + -- These values are for your SDRAM part (see datasheet) + constant TCAS : positive := 2; -- CAS latency [clocks] + constant TRP : positive := 2; -- precharge command period + constant TRAS : positive := 5; -- active to precharge delay + constant TRFC : positive := 8; -- auto refresh command period + constant TMRD : positive := 2; -- load mode register command cylce time + constant TRCD : positive := 2; -- active to read or write delay ! + constant TWR : positive := 2; -- write recovery time + + constant PWR_UP_WAIT : natural := 22; -- µs + + subtype user_tag_t is unsigned(3 downto 0); + + ---------------------------------------------------------------------------------------------- + +end sdram_config; diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd new file mode 100644 index 0000000..0fa4602 --- /dev/null +++ b/projects/mips_sys/src/tb_mips_sys.vhd @@ -0,0 +1,208 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: testbench for system test using Xilinx ML-402 + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +use std.textio.all; -- Imports the standard textio package. + +library work; +use work.mips_types.all; +use work.sdram_config.all; +use work.sdram_types.all; + +ENTITY tb_mips_sys IS +END tb_mips_sys; + +ARCHITECTURE behavior OF tb_mips_sys IS + + constant CLK_PERIOD : time := 10 ns; + signal sys_rst_n_in : std_logic := '0'; + signal sys_clk_in : std_logic := '1'; + signal dip : unsigned(7 downto 0) := (others => '0'); + signal btn : unsigned(4 downto 0) := (others => '0'); + signal led : unsigned(8 downto 0); + signal sys_rx : std_logic := '1'; + signal sys_tx : std_logic; + + signal sys_lcd_d : unsigned(3 downto 0); + signal sys_lcd_e : std_logic; + signal sys_lcd_rs : std_logic; + signal sys_lcd_rw : std_logic; + + signal refresh : boolean:= true; + + signal sys_sdr_clk_p : std_logic; -- ddr_sdram_clock + signal sys_sdr_clk_n : std_logic; -- /ddr_sdram_clock + signal sys_sdr_cke_q : std_logic; -- clock enable + signal sys_sdr_cs_qn : std_logic; -- /chip select + signal sys_sdr_ras_qn : std_logic; -- /ras + signal sys_sdr_cas_qn : std_logic; -- /cas + signal sys_sdr_we_qn : std_logic; -- /write enable + signal sys_sdr_dm_q : unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00" + signal sys_sdr_dqs_q : unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write + signal sys_sdr_ba_q : unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select + signal sys_sdr_a_q : unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus + signal sys_sdr_data : unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus + + signal sys_error : unsigned(1 downto 0); -- indicates DCM Errors + signal sys_sdr_clk_fb : std_logic; + + constant UROM_ADDR_WIDTH : integer := 18; + signal sys_user_rom_clk : std_logic; + signal sys_user_rom_en : std_logic; + signal sys_user_rom_din : word_t; + signal sys_user_rom_addr : word_t; + + type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t; + signal urom_data : urom_data_t; + +BEGIN + +uut: entity work.mips_sys +-- GENERIC MAP +-- ( +-- ddr_phaseshift => 90, +-- ddr_frequency_hz => 100E6 +-- ) + PORT MAP + ( + sys_rst_n_in => sys_rst_n_in, + sys_clk_in => sys_clk_in, + sys_btn => btn, + sys_dip => dip, + sys_led => led, + + sys_rx => sys_rx, + sys_tx => sys_tx, + + sys_lcd_d => sys_lcd_d, + sys_lcd_e => sys_lcd_e, + sys_lcd_rs => sys_lcd_rs, + sys_lcd_rw => sys_lcd_rw, + + sys_user_rom_addr => sys_user_rom_addr, + sys_user_rom_din => sys_user_rom_din, + sys_user_rom_en => sys_user_rom_en, + sys_user_rom_clk => sys_user_rom_clk, + + sys_sdr_clk_p => sys_sdr_clk_p, + sys_sdr_clk_n => sys_sdr_clk_n, + sys_sdr_cke_q => sys_sdr_cke_q, + sys_sdr_clk_fb => sys_sdr_clk_fb, + sys_sdr_cs_qn => sys_sdr_cs_qn, + sys_sdr_ras_qn => sys_sdr_ras_qn, + sys_sdr_cas_qn => sys_sdr_cas_qn, + sys_sdr_we_qn => sys_sdr_we_qn, + sys_sdr_dm_q => sys_sdr_dm_q, + sys_sdr_dqs_q => sys_sdr_dqs_q, + sys_sdr_ba_q => sys_sdr_ba_q, + sys_sdr_a_q => sys_sdr_a_q, + sys_sdr_data => sys_sdr_data, + sys_error => sys_error + ); + + -- MICRON DDR SDRAM Simulation Model + i_mt46v16m16_0 : entity work.mt46v16m16 + port map ( + dq => std_logic_vector(sys_sdr_data(15 downto 0)), + dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)), + addr => std_logic_vector(sys_sdr_a_q), + ba => std_logic_vector(sys_sdr_ba_q), + clk => sys_sdr_clk_p, + clk_n => sys_sdr_clk_n, + cke => sys_sdr_cke_q, + cs_n => sys_sdr_cs_qn, + ras_n => sys_sdr_ras_qn, + cas_n => sys_sdr_cas_qn, + we_n => sys_sdr_we_qn, + dm => std_logic_vector(sys_sdr_dm_q(1 downto 0)) + ); + + -- MICRON DDR SDRAM Simulation Model + i_mt46v16m16_1 : entity work.mt46v16m16 + port map ( + dq => std_logic_vector(sys_sdr_data(31 downto 16)), + dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)), + addr => std_logic_vector(sys_sdr_a_q), + ba => std_logic_vector(sys_sdr_ba_q), + clk => sys_sdr_clk_p, + clk_n => sys_sdr_clk_n, + cke => sys_sdr_cke_q, + cs_n => sys_sdr_cs_qn, + ras_n => sys_sdr_ras_qn, + cas_n => sys_sdr_cas_qn, + we_n => sys_sdr_we_qn, + dm => std_logic_vector(sys_sdr_dm_q(3 downto 2)) + ); + + sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps; + refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false; + +CLK_GEN: process + begin + wait for CLK_PERIOD/2; + sys_clk_in <= not sys_clk_in; + end process; + +UROM_READ: process(sys_rst_n_in, sys_user_rom_clk) + type file_t is file of integer; + file load_urom : file_t open read_mode is "test_dcache.bin"; + variable instr : integer; + variable index : natural; + variable temp : signed(31 downto 0); + begin + if sys_rst_n_in = '0' then + index := 0; + while not endfile(load_urom) loop + read(load_urom, instr); + temp := to_signed(instr, word_t'length); + urom_data(index) <= unsigned(temp); + index := index + 1; + end loop; + elsif rising_edge(sys_user_rom_clk) and sys_user_rom_en = '1' then + index := to_integer(sys_user_rom_addr(UROM_ADDR_WIDTH+1 downto 2)); + sys_user_rom_din <= urom_data(index); + end if; + end process; + +STIMULUS: process + + begin + + wait for 3*CLK_PERIOD; + sys_rst_n_in <= '1'; + wait for 200000*CLK_PERIOD; + + loop + wait for 251*CLK_PERIOD; + btn(4) <= '1'; + wait for 311*CLK_PERIOD; + btn(4) <= '0'; + end loop; + wait; + + end process; + +END; diff --git a/projects/mips_sys/tools/insrom.rb b/projects/mips_sys/tools/insrom.rb new file mode 100644 index 0000000..fdbf1ed --- /dev/null +++ b/projects/mips_sys/tools/insrom.rb @@ -0,0 +1,46 @@ +#!/usr/bin/env ruby + +# ---------------------------------------------------------------------- +# Project: JIPS, a portable 32-bit RISC CPU written in VHDL +# This file: Insertion of code fragments into templates +# +# Copyright (C) 2008 J. Ahrensfeld +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# For questions and ideas, please contact the author at jens@jayfield.org +# +# --------------------------------------------------------------------- + +arg = $* +rom_filename = arg[0].to_s +tpl_filename = arg[1].to_s + +subst_pattern = "ROM_INSERT_HERE" + +# -------------------------------------------------------- +# Open file +# -------------------------------------------------------- +romfile = File.open(rom_filename, "r") +tplfile = File.open(tpl_filename, "r") +re = Regexp.new(subst_pattern) + +while (line = tplfile.gets) + puts line + line.scan(re).each do |word| + romfile.each do |raw_line| + puts raw_line + end + end +end diff --git a/projects/mips_sys/tools/irom.vhd.tpl b/projects/mips_sys/tools/irom.vhd.tpl new file mode 100644 index 0000000..5ffd6d7 --- /dev/null +++ b/projects/mips_sys/tools/irom.vhd.tpl @@ -0,0 +1,29 @@ +------------------------------------------------------------------------- +-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL +-- This file: The ROM file for use in your VHDL design +-- +-- Copyright (C) 2008 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +-- ROM_INSERT_HERE + diff --git a/projects/mips_sys/tools/irom_ld.vhd.tpl b/projects/mips_sys/tools/irom_ld.vhd.tpl new file mode 100644 index 0000000..3bd3afb --- /dev/null +++ b/projects/mips_sys/tools/irom_ld.vhd.tpl @@ -0,0 +1,147 @@ +------------------------------------------------------------------------- +-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL +-- This file: loadable ROM +-- +-- Copyright (C) 2008 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +ENTITY irom IS + Port ( + clk : in STD_LOGIC; + addr : in inst_addr_t; + dout : out inst_t + ); + +END irom; + +ARCHITECTURE loadable OF irom IS + + -- JASM_ROM_INSERT_HERE + + signal jtag_ld_clk : STD_LOGIC; + signal jtag_ld_we : STD_LOGIC; + signal jtag_ld_addr : unsigned (15 downto 0); + signal jtag_ld_dout : unsigned (31 downto 0); + signal jtag_ld_din : unsigned (31 downto 0); + signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; + signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; + signal user_regi, user_rego : unsigned (47 downto 0); + constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE"; + +begin + +-------------------------------------------------------------------------- +-- Virtex-4: JTAG Loader +-------------------------------------------------------------------------- + i00_BUFG : BUFG + port map + ( + O => bs_clk1, + I => bs_clk0 + ); + + i01_BUFG : BUFG + port map + ( + O => bs_update1, + I => bs_update0 + ); + + BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 + generic map + ( + JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) + ) + port map + ( + CAPTURE => bs_capture, -- CAPTURE output from TAP controller + DRCK => bs_clk0, -- Data register output for USER functions + RESET => bs_rst, -- Reset output from TAP controller + SEL => bs_sel, -- USER active output + SHIFT => bs_shift, -- SHIFT output from TAP controller + TDI => bs_tdi, -- TDI output from TAP controller + UPDATE => bs_update0, -- UPDATE output from TAP controller + TDO => bs_tdo -- Data input for USER function + ); + + jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); + jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); + jtag_ld_clk <= bs_update1; + jtag_ld_we <= bs_sel; + +sipo: + process (bs_rst, bs_clk1, bs_tdi, bs_shift) + begin + if bs_rst = '1' then + user_regi <= (others => '0'); + elsif rising_edge(bs_clk1) then + if bs_shift = '1' then + user_regi <= bs_tdi & user_regi(user_regi'left downto 1); + end if; + end if; + end process; + +piso: + process (bs_rst, bs_clk1, bs_shift, user_rego) + begin + bs_tdo <= user_rego(0); + if bs_rst = '1' then + user_rego <= (others => '0'); + elsif rising_edge(bs_clk1) then + if bs_shift = '1' then + user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); + else + user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; +-- user_rego <= id; + end if; + end if; + end process; + +PROM_WRITE: + process(jtag_ld_clk, jtag_ld_we) + begin + if rising_edge(jtag_ld_clk) then + if jtag_ld_we = '1' then + imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; + else + jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); + end if; + end if; + end process; + +-------------------------------------------------------------------------- +-- ROM Read/Write +-------------------------------------------------------------------------- +PROM_READ: + process(clk) + begin + if rising_edge(clk) then + dout <= imem_rom(to_integer(addr)); + end if; + end process; + +-------------------------------------------------------------------------- +end loadable; diff --git a/projects/mips_sys/tools/make b/projects/mips_sys/tools/make new file mode 100644 index 0000000..e7f598f --- /dev/null +++ b/projects/mips_sys/tools/make @@ -0,0 +1,50 @@ +#!/bin/sh + +# ---------------------------------------------------------------------- +# Project: JCPU, a portable 8-bit RISC CPU written in VHDL +# This file: rom-file generation for cpu_core +# +# Copyright (C) 2007 J. Ahrensfeld +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# For questions and ideas, please contact the author at jens@jayfield.org +# +# --------------------------------------------------------------------- + +TARGET=$2 +DSTDIR=$1 + +JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools + +$JASM_HOME/jasm.rb $TARGET.jsm + +irom_tcl_snippet="$TARGET.irom.tcl.snip" +irom_vhdl_snippet="$TARGET.irom.vhdl.snip" +irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip" +xrom_tcl_snippet="$TARGET.xrom.tcl.snip" +xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip" +xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip" + +$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl +$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl + +$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl +$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl + +cat $irom_tcl_snippet > $TARGET.tcl.snip.snip +cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip +$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl + +rm -f *.snip diff --git a/projects/mips_sys/tools/rom.tcl.tpl b/projects/mips_sys/tools/rom.tcl.tpl new file mode 100644 index 0000000..9f5c0dc --- /dev/null +++ b/projects/mips_sys/tools/rom.tcl.tpl @@ -0,0 +1,61 @@ +# ---------------------------------------------------------------------- +# Project: JCPU, a portable 8-bit RISC CPU written in VHDL +# This file: The ROM file for upload to target over JTAG +# +# Copyright (C) 2007 J. Ahrensfeld +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# For questions and ideas, please contact the author at jens@jayfield.org +# +# --------------------------------------------------------------------- + +# --------------------------------------------------------------------- +# For Chipscope 9.1 +# --------------------------------------------------------------------- +# Source JTAG/TCL frame work +cd $env(CHIPSCOPE)\\bin\\nt +source csejtag.tcl + +namespace import ::chipscope::* + +# Platform USB Cable +set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] +# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" + +# Create session +set handle [::chipscope::csejtag_session create 0] + +# Open JTAG and lock +set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] +set lock_result [::chipscope::csejtag_target lock $handle 1000] + +set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] + +# Get Device ID +set devtype "Virtex-4SX" +set devid 2 +set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] +set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] + +set CSE_OP $CSEJTAG_SHIFT_READWRITE +set CSE_ES $CSEJTAG_RUN_TEST_IDLE + +# Write Program +# JASM_ROM_INSERT_HERE + +::chipscope::csejtag_target unlock $handle +::chipscope::csejtag_target close $handle +::chipscope::csejtag_session destroy $handle +exit diff --git a/projects/mips_sys/tools/src/ramgen.c b/projects/mips_sys/tools/src/ramgen.c new file mode 100644 index 0000000..8f61118 --- /dev/null +++ b/projects/mips_sys/tools/src/ramgen.c @@ -0,0 +1,385 @@ +#include +#include +#include +#include + +#define ARCH_NAME "data" +#define ENT_NAME "ram" +#define JTAG_ADDR_WIDTH 16 + +// -------------------------------------------------------------- +void basename(char *pSrc, char *pDst) +{ + int i, size; + + size = strlen(pSrc); + + while(pSrc[size] != '.') + size--; + + for (i=0; i < size; i++) + pDst[i] = pSrc[i]; + + pDst[i] = 0; + +} + +int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4); + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tsignal sram : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "begin\n", ARCH_NAME); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1); + fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tdout <= sram(index);\n"); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + + return 0; +} + +int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "library UNISIM;\n"); + fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); + fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); + fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); + fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "begin\n", ARCH_NAME); + + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "\n"); + fputs(tpl, pFileOut); + + fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); + fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\telse\n"); + fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + return 0; +} + +int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, word_addr, filesize, romsize; + char binstr_addr[33]; + char binstr_data[33]; + + char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fputs(tpl, pFileOut); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); + fprintf(pFileOut, "# ---------------------------------------------------------------\n"); + fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n"); + fprintf(pFileOut, "# User 2\n"); + fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n"); + + word_addr = 0; + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); + word_addr++; + } + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); + fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); + fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); + fprintf(pFileOut, "exit\n"); + + return 0; +} + +int main(int argc, char *argv[]) +{ + char *pFilenameIn; + char name_prj[1024]; + char name_rom_tcl[1024]; + char name_rom[1024]; + char name_rom_v4ld[1024]; + + FILE *pFileIn; + int filesize, romsize, nbits_addr, nbits_data; + long start, end; + int word, i; + + if (argc < 2) + { + fprintf(stderr, "Usage: ramgen \n"); + return 1; + } + + pFilenameIn = argv[1]; + if (argc == 3) + nbits_addr = atoi(argv[2]); + + + basename(pFilenameIn, name_prj); + sprintf(name_rom, "%s.vhd", name_prj); + sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); + sprintf(name_rom_tcl, "%s.tcl", name_prj); + + SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); +// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); + SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); + + + return 0; +} + diff --git a/projects/mips_sys/tools/src/romgen.c b/projects/mips_sys/tools/src/romgen.c new file mode 100644 index 0000000..a59e705 --- /dev/null +++ b/projects/mips_sys/tools/src/romgen.c @@ -0,0 +1,368 @@ +#include +#include +#include +#include + +#define ARCH_NAME "data" +#define ENT_NAME "rom" +#define JTAG_ADDR_WIDTH 16 + +// -------------------------------------------------------------- +void basename(char *pSrc, char *pDst) +{ + int i, size; + + size = strlen(pSrc); + + while(pSrc[size] != '.') + size--; + + for (i=0; i < size; i++) + pDst[i] = pSrc[i]; + + pDst[i] = 0; + +} + +int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "begin\n", ARCH_NAME); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + + return 0; +} + +int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "library UNISIM;\n"); + fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); + fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); + fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); + fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "begin\n", ARCH_NAME); + + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "\n"); + fputs(tpl, pFileOut); + + fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); + fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\telse\n"); + fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + return 0; +} + +int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, word_addr, filesize, romsize; + char binstr_addr[33]; + char binstr_data[33]; + + char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fputs(tpl, pFileOut); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); + fprintf(pFileOut, "# ---------------------------------------------------------------\n"); + fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n"); + fprintf(pFileOut, "# User 1\n"); + fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n"); + + word_addr = 0; + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); + word_addr++; + } + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); + fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); + fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); + fprintf(pFileOut, "exit\n"); + + return 0; +} + +int main(int argc, char *argv[]) +{ + char *pFilenameIn; + char name_prj[1024]; + char name_rom[1024]; + char name_rom_v4ld[1024]; + char name_rom_tcl[1024]; + + FILE *pFileIn; + int filesize, romsize, nbits_addr, nbits_data; + long start, end; + int word, i; + + if (argc < 2) + { + fprintf(stderr, "Usage: romgen \n"); + return 1; + } + + pFilenameIn = argv[1]; + if (argc == 3) + nbits_addr = atoi(argv[2]); + + + basename(pFilenameIn, name_prj); + sprintf(name_rom, "%s.vhd", name_prj); + sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); + sprintf(name_rom_tcl, "%s.tcl", name_prj); + + SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); + SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); + SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); + + + return 0; +} +