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git-svn-id: http://moon:8086/svn/vhdl/trunk@8 cc03376c-175c-47c8-b038-4cd826a8556b
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-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: testbench for system test using Xilinx ML-402
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library work;
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use work.mips_types.all;
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use work.sdram_config.all;
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use work.sdram_types.all;
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ENTITY tb_mips_sys IS
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END tb_mips_sys;
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ARCHITECTURE behavior OF tb_mips_sys IS
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constant CLK_PERIOD : time := 10 ns;
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signal sys_rst_n_in : std_logic := '0';
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signal sys_clk_in : std_logic := '1';
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signal dip : unsigned(7 downto 0) := (others => '0');
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signal btn : unsigned(4 downto 0) := (others => '0');
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signal led : unsigned(8 downto 0);
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signal sys_rx : std_logic := '1';
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signal sys_tx : std_logic;
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signal sys_lcd_d : unsigned(3 downto 0);
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signal sys_lcd_e : std_logic;
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signal sys_lcd_rs : std_logic;
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signal sys_lcd_rw : std_logic;
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signal refresh : boolean:= true;
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signal sys_sdr_clk_p : std_logic; -- ddr_sdram_clock
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signal sys_sdr_clk_n : std_logic; -- /ddr_sdram_clock
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signal sys_sdr_cke_q : std_logic; -- clock enable
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signal sys_sdr_cs_qn : std_logic; -- /chip select
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signal sys_sdr_ras_qn : std_logic; -- /ras
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signal sys_sdr_cas_qn : std_logic; -- /cas
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signal sys_sdr_we_qn : std_logic; -- /write enable
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signal sys_sdr_dm_q : unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00"
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signal sys_sdr_dqs_q : unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write
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signal sys_sdr_ba_q : unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select
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signal sys_sdr_a_q : unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus
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signal sys_sdr_data : unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
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signal sys_error : unsigned(1 downto 0); -- indicates DCM Errors
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signal sys_sdr_clk_fb : std_logic;
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constant UROM_ADDR_WIDTH : integer := 18;
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signal sys_user_rom_clk : std_logic;
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signal sys_user_rom_en : std_logic;
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signal sys_user_rom_din : word_t;
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signal sys_user_rom_addr : word_t;
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type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t;
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signal urom_data : urom_data_t;
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BEGIN
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uut: entity work.mips_sys
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-- GENERIC MAP
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-- (
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-- ddr_phaseshift => 90,
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-- ddr_frequency_hz => 100E6
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-- )
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PORT MAP
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(
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sys_rst_n_in => sys_rst_n_in,
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sys_clk_in => sys_clk_in,
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sys_btn => btn,
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sys_dip => dip,
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sys_led => led,
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sys_rx => sys_rx,
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sys_tx => sys_tx,
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sys_lcd_d => sys_lcd_d,
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sys_lcd_e => sys_lcd_e,
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sys_lcd_rs => sys_lcd_rs,
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sys_lcd_rw => sys_lcd_rw,
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sys_user_rom_addr => sys_user_rom_addr,
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sys_user_rom_din => sys_user_rom_din,
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sys_user_rom_en => sys_user_rom_en,
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sys_user_rom_clk => sys_user_rom_clk,
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sys_sdr_clk_p => sys_sdr_clk_p,
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sys_sdr_clk_n => sys_sdr_clk_n,
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sys_sdr_cke_q => sys_sdr_cke_q,
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sys_sdr_clk_fb => sys_sdr_clk_fb,
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sys_sdr_cs_qn => sys_sdr_cs_qn,
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sys_sdr_ras_qn => sys_sdr_ras_qn,
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sys_sdr_cas_qn => sys_sdr_cas_qn,
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sys_sdr_we_qn => sys_sdr_we_qn,
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sys_sdr_dm_q => sys_sdr_dm_q,
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sys_sdr_dqs_q => sys_sdr_dqs_q,
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sys_sdr_ba_q => sys_sdr_ba_q,
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sys_sdr_a_q => sys_sdr_a_q,
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sys_sdr_data => sys_sdr_data,
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sys_error => sys_error
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);
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-- MICRON DDR SDRAM Simulation Model
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i_mt46v16m16_0 : entity work.mt46v16m16
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port map (
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dq => std_logic_vector(sys_sdr_data(15 downto 0)),
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dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
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addr => std_logic_vector(sys_sdr_a_q),
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ba => std_logic_vector(sys_sdr_ba_q),
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clk => sys_sdr_clk_p,
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clk_n => sys_sdr_clk_n,
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cke => sys_sdr_cke_q,
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cs_n => sys_sdr_cs_qn,
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ras_n => sys_sdr_ras_qn,
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cas_n => sys_sdr_cas_qn,
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we_n => sys_sdr_we_qn,
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dm => std_logic_vector(sys_sdr_dm_q(1 downto 0))
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);
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-- MICRON DDR SDRAM Simulation Model
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i_mt46v16m16_1 : entity work.mt46v16m16
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port map (
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dq => std_logic_vector(sys_sdr_data(31 downto 16)),
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dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
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addr => std_logic_vector(sys_sdr_a_q),
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ba => std_logic_vector(sys_sdr_ba_q),
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clk => sys_sdr_clk_p,
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clk_n => sys_sdr_clk_n,
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cke => sys_sdr_cke_q,
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cs_n => sys_sdr_cs_qn,
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ras_n => sys_sdr_ras_qn,
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cas_n => sys_sdr_cas_qn,
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we_n => sys_sdr_we_qn,
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dm => std_logic_vector(sys_sdr_dm_q(3 downto 2))
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);
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sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
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refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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sys_clk_in <= not sys_clk_in;
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end process;
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UROM_READ: process(sys_rst_n_in, sys_user_rom_clk)
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type file_t is file of integer;
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file load_urom : file_t open read_mode is "test_dcache.bin";
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variable instr : integer;
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variable index : natural;
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variable temp : signed(31 downto 0);
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begin
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if sys_rst_n_in = '0' then
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index := 0;
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while not endfile(load_urom) loop
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read(load_urom, instr);
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temp := to_signed(instr, word_t'length);
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urom_data(index) <= unsigned(temp);
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index := index + 1;
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end loop;
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elsif rising_edge(sys_user_rom_clk) and sys_user_rom_en = '1' then
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index := to_integer(sys_user_rom_addr(UROM_ADDR_WIDTH+1 downto 2));
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sys_user_rom_din <= urom_data(index);
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end if;
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end process;
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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sys_rst_n_in <= '1';
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wait for 200000*CLK_PERIOD;
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loop
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wait for 251*CLK_PERIOD;
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btn(4) <= '1';
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wait for 311*CLK_PERIOD;
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btn(4) <= '0';
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end loop;
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wait;
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end process;
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END;
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