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- made ram sizable

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git-svn-id: http://moon:8086/svn/vhdl/trunk@979 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-07-20 09:53:34 +00:00
parent a43bcf23af
commit a836d35ee1
4 changed files with 21 additions and 6 deletions
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lib/misc/ram_wb.vhd
+8 -1
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@@ -2,7 +2,14 @@ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
library work;
use work.utils_pkg.all;
ENTITY ram_wb IS ENTITY ram_wb IS
GENERIC
(
NUM_WORDS : integer := 64
);
Port Port
( (
CLK_I : in STD_LOGIC; CLK_I : in STD_LOGIC;
@@ -63,7 +70,7 @@ data_valid_register:
inst_ram : ram inst_ram : ram
GENERIC MAP GENERIC MAP
( (
word_addr_width => 6 word_addr_width => NextExpBaseTwo(NUM_WORDS)
) )
PORT MAP PORT MAP
( (
lib/misc/sim/tb_ram_wb.fdo
+1
View File
@@ -3,6 +3,7 @@
vlib work vlib work
# Top and TB # Top and TB
vcom -explicit -93 "../utils_pkg.vhd"
vcom -explicit -93 "../ram_sim.vhd" vcom -explicit -93 "../ram_sim.vhd"
vcom -explicit -93 "../ram_wb.vhd" vcom -explicit -93 "../ram_wb.vhd"
vcom -explicit -93 "../tb_ram_wb.vhd" vcom -explicit -93 "../tb_ram_wb.vhd"
lib/misc/sim/tb_ram_wb.wdo
+2 -1
View File
@@ -14,8 +14,9 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg
add wave -noupdate -format Literal /tb_ram_wb/dout_cnt add wave -noupdate -format Literal /tb_ram_wb/dout_cnt
add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/inst_ram_wb/inst_ram/sram
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {950000 ps} 0} WaveRestoreCursors {{Cursor 1} {740000 ps} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 150
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
lib/misc/tb_ram_wb.vhd
+10 -4
View File
@@ -32,7 +32,9 @@ END tb_ram_wb;
ARCHITECTURE behavior OF tb_ram_wb IS ARCHITECTURE behavior OF tb_ram_wb IS
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant RAM_NUM_WORDS : integer := 256;
signal CLK_O : std_logic := '1'; signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1'; signal RST_O : std_logic := '1';
signal CYC_O : std_logic := '0'; signal CYC_O : std_logic := '0';
@@ -53,6 +55,10 @@ ARCHITECTURE behavior OF tb_ram_wb IS
BEGIN BEGIN
inst_ram_wb : entity work.ram_wb inst_ram_wb : entity work.ram_wb
GENERIC MAP
(
NUM_WORDS => RAM_NUM_WORDS
)
PORT MAP PORT MAP
( (
RST_I => RST_O, RST_I => RST_O,
@@ -214,7 +220,7 @@ STIMULUS: process
ADDR_O <= ADDR_O + 4; ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0'; STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1'; wait until rising_edge(CLK_O);
CYC_O <= '0'; CYC_O <= '0';
@@ -258,7 +264,7 @@ STIMULUS: process
DAT_O <= X"DEADBEEF"; DAT_O <= X"DEADBEEF";
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0'; STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1'; wait until rising_edge(CLK_O);
CYC_O <= '0'; CYC_O <= '0';
wait for 3*CLK_PERIOD; wait for 3*CLK_PERIOD;
@@ -270,7 +276,7 @@ STIMULUS: process
ADDR_O <= X"0000_0080"; ADDR_O <= X"0000_0080";
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0'; STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1'; wait until rising_edge(CLK_O);
CYC_O <= '0'; CYC_O <= '0';
-- 8-word burst cycle -- 8-word burst cycle