From a836d35ee1069675514311197017c7ba1dbe4fde Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sat, 20 Jul 2013 09:53:34 +0000
Subject: [PATCH] - made ram sizable Committed on the Free edition of March
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git-svn-id: http://moon:8086/svn/vhdl/trunk@979 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/misc/ram_wb.vhd        |  9 ++++++++-
 lib/misc/sim/tb_ram_wb.fdo |  1 +
 lib/misc/sim/tb_ram_wb.wdo |  3 ++-
 lib/misc/tb_ram_wb.vhd     | 14 ++++++++++----
 4 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/lib/misc/ram_wb.vhd b/lib/misc/ram_wb.vhd
index 2ebf242..5169ef9 100644
--- a/lib/misc/ram_wb.vhd
+++ b/lib/misc/ram_wb.vhd
@@ -2,7 +2,14 @@ LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 
+library work;
+use work.utils_pkg.all;
+
 ENTITY ram_wb IS
+	GENERIC 
+	(
+		NUM_WORDS 	: integer := 64
+	);
 	Port
 	(
 		CLK_I		: in  STD_LOGIC;
@@ -63,7 +70,7 @@ data_valid_register:
 inst_ram : ram
 	GENERIC MAP 
 	(
-		word_addr_width	=> 6
+		word_addr_width	=> NextExpBaseTwo(NUM_WORDS)
 	)
 	PORT MAP 
 	(
diff --git a/lib/misc/sim/tb_ram_wb.fdo b/lib/misc/sim/tb_ram_wb.fdo
index 1174591..34f771c 100644
--- a/lib/misc/sim/tb_ram_wb.fdo
+++ b/lib/misc/sim/tb_ram_wb.fdo
@@ -3,6 +3,7 @@
 vlib work
 
 # Top and TB
+vcom -explicit  -93 "../utils_pkg.vhd"
 vcom -explicit  -93 "../ram_sim.vhd"
 vcom -explicit  -93 "../ram_wb.vhd"
 vcom -explicit  -93 "../tb_ram_wb.vhd"
diff --git a/lib/misc/sim/tb_ram_wb.wdo b/lib/misc/sim/tb_ram_wb.wdo
index 2cdca8e..53e65e1 100644
--- a/lib/misc/sim/tb_ram_wb.wdo
+++ b/lib/misc/sim/tb_ram_wb.wdo
@@ -14,8 +14,9 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_i
 add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o
 add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg
 add wave -noupdate -format Literal /tb_ram_wb/dout_cnt
+add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/inst_ram_wb/inst_ram/sram
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {950000 ps} 0}
+WaveRestoreCursors {{Cursor 1} {740000 ps} 0}
 configure wave -namecolwidth 150
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
diff --git a/lib/misc/tb_ram_wb.vhd b/lib/misc/tb_ram_wb.vhd
index b165069..64e747a 100644
--- a/lib/misc/tb_ram_wb.vhd
+++ b/lib/misc/tb_ram_wb.vhd
@@ -32,7 +32,9 @@ END tb_ram_wb;
 
 ARCHITECTURE behavior OF tb_ram_wb IS 
 
-	constant CLK_PERIOD : time := 10 ns;
+	constant CLK_PERIOD		: time := 10 ns;
+	constant RAM_NUM_WORDS	: integer := 256;
+	
 	signal CLK_O	: std_logic := '1';
 	signal RST_O	: std_logic := '1';
 	signal CYC_O	: std_logic := '0';
@@ -53,6 +55,10 @@ ARCHITECTURE behavior OF tb_ram_wb IS
 BEGIN
 
 inst_ram_wb : entity work.ram_wb
+	GENERIC MAP
+	(
+		NUM_WORDS	=> RAM_NUM_WORDS
+	)
 	PORT MAP
 	(
 		RST_I		=> RST_O,
@@ -214,7 +220,7 @@ STIMULUS: process
 		ADDR_O	<= ADDR_O + 4;
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
+		wait until rising_edge(CLK_O);
 		CYC_O	<= '0';
 
 		
@@ -258,7 +264,7 @@ STIMULUS: process
 		DAT_O	<= X"DEADBEEF";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
+		wait until rising_edge(CLK_O);
 		CYC_O	<= '0';
 
 		wait for 3*CLK_PERIOD;
@@ -270,7 +276,7 @@ STIMULUS: process
 		ADDR_O	<= X"0000_0080";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
+		wait until rising_edge(CLK_O);
 		CYC_O	<= '0';
 
 		-- 8-word burst cycle