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- fixed Gibabit ethernet

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1331 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-12-13 09:10:28 +00:00
parent 3897393a94
commit a6fe149b7a
2 changed files with 67 additions and 53 deletions
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lib/emac/src/emac_top_jb.vhd
+5 -4
View File
@@ -36,7 +36,7 @@ ENTITY emac_top_jb IS
mii_tx_en : out STD_LOGIC; mii_tx_en : out STD_LOGIC;
mii_tx_er : out STD_LOGIC; mii_tx_er : out STD_LOGIC;
mii_tx : out unsigned(7 downto 0); mii_tx : out unsigned(7 downto 0);
mii_gtx_clk : out STD_LOGIC; mii_gtx_clk : in STD_LOGIC;
mii_crs : in STD_LOGIC; mii_crs : in STD_LOGIC;
mii_col : in STD_LOGIC mii_col : in STD_LOGIC
@@ -72,11 +72,10 @@ ARCHITECTURE behavior OF emac_top_jb IS
signal reg_write : std_logic; signal reg_write : std_logic;
signal reg_addr : unsigned(3 downto 0); signal reg_addr : unsigned(3 downto 0);
signal tx_clk : std_logic;
begin begin
mii_gtx_clk <= '0';
SRDY_O <= CYC_I and ready; SRDY_O <= CYC_I and ready;
read <= STB_I and CYC_I and not WE_I; read <= STB_I and CYC_I and not WE_I;
write <= STB_I and CYC_I and WE_I; write <= STB_I and CYC_I and WE_I;
@@ -93,6 +92,8 @@ begin
rx_dout_re <= data_read; rx_dout_re <= data_read;
tx_clk <= mii_gtx_clk when tx_ctrl_in.Gbps_en = '1' else mii_tx_clk;
------------------------------------------------------------------ ------------------------------------------------------------------
registers_write: registers_write:
process(CLK_I) process(CLK_I)
@@ -294,7 +295,7 @@ inst_emac_tx : entity work.emac_tx
din => tx_din, din => tx_din,
ctrl_in => tx_ctrl_in, ctrl_in => tx_ctrl_in,
ctrl_out => tx_ctrl_out, ctrl_out => tx_ctrl_out,
mii_tx_clk => mii_tx_clk, mii_tx_clk => tx_clk,
mii_tx_en => mii_tx_en, mii_tx_en => mii_tx_en,
mii_tx_er => mii_tx_er, mii_tx_er => mii_tx_er,
mii_tx => mii_tx mii_tx => mii_tx
lib/emac/src/tb_emac_top_jb.vhd
+61 -48
View File
@@ -31,55 +31,58 @@ END tb_emac_top_jb;
ARCHITECTURE behavior OF tb_emac_top_jb IS ARCHITECTURE behavior OF tb_emac_top_jb IS
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 37.7 ns; constant MII_CLK_PERIOD : time := 37.7 ns;
constant GMII_CLK_PERIOD : time := 8.0 ns;
signal CLK : std_logic := '1'; signal CLK : std_logic := '1';
signal RST : std_logic := '1'; signal RST : std_logic := '1';
-- Slave -- Slave
signal CYC_I : std_logic := '0'; signal CYC_I : std_logic := '0';
signal STB_I : std_logic := '0'; signal STB_I : std_logic := '0';
signal WE_I : std_logic := '0'; signal WE_I : std_logic := '0';
signal SEL_I : unsigned(3 downto 0) := (others => '1'); signal SEL_I : unsigned(3 downto 0) := (others => '1');
signal ACK_O : std_logic; signal ACK_O : std_logic;
signal INT_O : std_logic; signal INT_O : std_logic;
signal MRDY_I : std_logic := '0'; signal MRDY_I : std_logic := '0';
signal SRDY_O : std_logic; signal SRDY_O : std_logic;
signal ADDR_I : unsigned(31 downto 0) := (others => '-'); signal ADDR_I : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0) := (others => '-'); signal DAT_I : unsigned(31 downto 0) := (others => '-');
signal DAT_O : unsigned(31 downto 0) := (others => '-'); signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal DAT_O_reg : unsigned(31 downto 0) := (others => '-'); signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
signal status_reg : unsigned(31 downto 0) := (others => '0'); signal status_reg : unsigned(31 downto 0) := (others => '0');
signal size_reg : unsigned(31 downto 0) := (others => '0'); signal size_reg : unsigned(31 downto 0) := (others => '0');
-- MII signals -- MII signals
signal mii_rx_clk_board : std_logic := '1'; signal mii_rx_clk_board : std_logic := '1';
signal mii_tx_clk_board : std_logic := '1'; signal mii_tx_clk_board : std_logic := '1';
signal mii_rx_clk : std_logic := '1'; signal mii_rx_clk : std_logic := '1';
signal mii_tx_clk : std_logic := '1'; signal mii_tx_clk : std_logic := '1';
signal mii_rx : unsigned(7 downto 0) := (others => '-'); signal mii_rx : unsigned(7 downto 0) := (others => '-');
signal mii_tx : unsigned(7 downto 0); signal mii_tx : unsigned(7 downto 0);
signal mii_rx_dv : std_logic := '0'; signal mii_rx_dv : std_logic := '0';
signal mii_rx_er : std_logic := '0'; signal mii_rx_er : std_logic := '0';
signal mii_tx_en : std_logic; signal mii_tx_en : std_logic;
signal mii_tx_er : std_logic; signal mii_tx_er : std_logic;
signal mii_crs : std_logic := '0'; signal mii_crs : std_logic := '0';
signal mii_col : std_logic := '0'; signal mii_col : std_logic := '0';
signal mii_gtx_clk : std_logic; signal mii_gtx_clk : std_logic := '0';
signal loop_back_en : std_logic := '0'; signal loop_back_en : std_logic := '0';
signal gigabit_rx_en : std_logic := '0';
signal gigabit_tx_en : std_logic := '0';
signal pktgen_tx : unsigned(7 downto 0); signal pktgen_tx : unsigned(7 downto 0);
signal pktgen_tx_en : std_logic; signal pktgen_tx_en : std_logic;
signal pktgen_tx_er : std_logic; signal pktgen_tx_er : std_logic;
signal pktgen_en : std_logic := '0'; signal pktgen_en : std_logic := '0';
signal pktgen_gigabit : std_logic := '0'; signal pktgen_gigabit : std_logic := '0';
signal pktgen_fcs_en : std_logic := '0'; signal pktgen_fcs_en : std_logic := '0';
signal dat_o_cnt_en : std_logic := '0'; signal dat_o_cnt_en : std_logic := '0';
signal dat_o_cnt_rst : std_logic := '1'; signal dat_o_cnt_rst : std_logic := '1';
signal dat_o_cnt : natural; signal dat_o_cnt : natural;
signal pkt_count : natural; signal pkt_count : natural;
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free); type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
signal emac_action : emac_action_t; signal emac_action : emac_action_t;
@@ -164,8 +167,14 @@ MII_CLK_GEN: process
mii_tx_clk <= not mii_tx_clk; mii_tx_clk <= not mii_tx_clk;
end process; end process;
mii_rx_clk_board <= mii_rx_clk; GMII_CLK_GEN: process
mii_tx_clk_board <= mii_tx_clk; begin
wait for GMII_CLK_PERIOD/2;
mii_gtx_clk <= not mii_gtx_clk;
end process;
mii_rx_clk_board <= mii_gtx_clk when gigabit_rx_en = '1' else mii_rx_clk;
mii_tx_clk_board <= mii_gtx_clk when gigabit_tx_en = '1' else mii_tx_clk;
DAT_O_register: DAT_O_register:
process(CLK) process(CLK)
@@ -201,6 +210,7 @@ STIMULUS: process
procedure emac_tx_reset_100mbps is procedure emac_tx_reset_100mbps is
begin begin
gigabit_tx_en <= '0';
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"A000_0000"; DAT_I <= X"A000_0000";
@@ -216,6 +226,7 @@ STIMULUS: process
procedure emac_rx_reset_100mbps is procedure emac_rx_reset_100mbps is
begin begin
gigabit_rx_en <= '0';
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"A000_0000"; DAT_I <= X"A000_0000";
@@ -231,6 +242,7 @@ STIMULUS: process
procedure emac_tx_reset_1000mbps is procedure emac_tx_reset_1000mbps is
begin begin
gigabit_tx_en <= '1';
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"E000_0000"; DAT_I <= X"E000_0000";
@@ -246,6 +258,7 @@ STIMULUS: process
procedure emac_rx_reset_1000mbps is procedure emac_rx_reset_1000mbps is
begin begin
gigabit_rx_en <= '1';
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"E000_0000"; DAT_I <= X"E000_0000";
@@ -504,9 +517,9 @@ STIMULUS: process
wait for 6*MII_CLK_PERIOD; wait for 6*MII_CLK_PERIOD;
RST <= '0'; RST <= '0';
wait for 60*CLK_PERIOD; wait for 60*CLK_PERIOD;
emac_rx_reset_100mbps; emac_rx_reset_1000mbps;
emac_tx_reset_100mbps; emac_tx_reset_1000mbps;
pktgen_gigabit <= '0'; pktgen_gigabit <= '1';
pktgen_fcs_en <= '1'; pktgen_fcs_en <= '1';
wait for 60*CLK_PERIOD; wait for 60*CLK_PERIOD;
@@ -533,7 +546,7 @@ STIMULUS: process
wait for 60*CLK_PERIOD; wait for 60*CLK_PERIOD;
wait until rising_edge(mii_tx_clk) and mii_tx_en = '0'; wait until rising_edge(mii_tx_clk_board) and mii_tx_en = '0';
loop_back_en <= '1'; loop_back_en <= '1';