diff --git a/lib/emac/src/emac_top_jb.vhd b/lib/emac/src/emac_top_jb.vhd index cf7c2ec..7d927af 100644 --- a/lib/emac/src/emac_top_jb.vhd +++ b/lib/emac/src/emac_top_jb.vhd @@ -36,7 +36,7 @@ ENTITY emac_top_jb IS mii_tx_en : out STD_LOGIC; mii_tx_er : out STD_LOGIC; mii_tx : out unsigned(7 downto 0); - mii_gtx_clk : out STD_LOGIC; + mii_gtx_clk : in STD_LOGIC; mii_crs : in STD_LOGIC; mii_col : in STD_LOGIC @@ -72,11 +72,10 @@ ARCHITECTURE behavior OF emac_top_jb IS signal reg_write : std_logic; signal reg_addr : unsigned(3 downto 0); - + signal tx_clk : std_logic; + begin - mii_gtx_clk <= '0'; - SRDY_O <= CYC_I and ready; read <= STB_I and CYC_I and not WE_I; write <= STB_I and CYC_I and WE_I; @@ -93,6 +92,8 @@ begin rx_dout_re <= data_read; + tx_clk <= mii_gtx_clk when tx_ctrl_in.Gbps_en = '1' else mii_tx_clk; + ------------------------------------------------------------------ registers_write: process(CLK_I) @@ -294,7 +295,7 @@ inst_emac_tx : entity work.emac_tx din => tx_din, ctrl_in => tx_ctrl_in, ctrl_out => tx_ctrl_out, - mii_tx_clk => mii_tx_clk, + mii_tx_clk => tx_clk, mii_tx_en => mii_tx_en, mii_tx_er => mii_tx_er, mii_tx => mii_tx diff --git a/lib/emac/src/tb_emac_top_jb.vhd b/lib/emac/src/tb_emac_top_jb.vhd index 78639c2..5b2ce3e 100644 --- a/lib/emac/src/tb_emac_top_jb.vhd +++ b/lib/emac/src/tb_emac_top_jb.vhd @@ -31,55 +31,58 @@ END tb_emac_top_jb; ARCHITECTURE behavior OF tb_emac_top_jb IS - constant CLK_PERIOD : time := 10 ns; - constant MII_CLK_PERIOD : time := 37.7 ns; + constant CLK_PERIOD : time := 10 ns; + constant MII_CLK_PERIOD : time := 37.7 ns; + constant GMII_CLK_PERIOD : time := 8.0 ns; - signal CLK : std_logic := '1'; - signal RST : std_logic := '1'; + signal CLK : std_logic := '1'; + signal RST : std_logic := '1'; -- Slave - signal CYC_I : std_logic := '0'; - signal STB_I : std_logic := '0'; - signal WE_I : std_logic := '0'; - signal SEL_I : unsigned(3 downto 0) := (others => '1'); - signal ACK_O : std_logic; - signal INT_O : std_logic; - signal MRDY_I : std_logic := '0'; - signal SRDY_O : std_logic; - signal ADDR_I : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0) := (others => '-'); - signal DAT_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_O_reg : unsigned(31 downto 0) := (others => '-'); - signal status_reg : unsigned(31 downto 0) := (others => '0'); - signal size_reg : unsigned(31 downto 0) := (others => '0'); + signal CYC_I : std_logic := '0'; + signal STB_I : std_logic := '0'; + signal WE_I : std_logic := '0'; + signal SEL_I : unsigned(3 downto 0) := (others => '1'); + signal ACK_O : std_logic; + signal INT_O : std_logic; + signal MRDY_I : std_logic := '0'; + signal SRDY_O : std_logic; + signal ADDR_I : unsigned(31 downto 0) := (others => '-'); + signal DAT_I : unsigned(31 downto 0) := (others => '-'); + signal DAT_O : unsigned(31 downto 0) := (others => '-'); + signal DAT_O_reg : unsigned(31 downto 0) := (others => '-'); + signal status_reg : unsigned(31 downto 0) := (others => '0'); + signal size_reg : unsigned(31 downto 0) := (others => '0'); -- MII signals - signal mii_rx_clk_board : std_logic := '1'; - signal mii_tx_clk_board : std_logic := '1'; - signal mii_rx_clk : std_logic := '1'; - signal mii_tx_clk : std_logic := '1'; - signal mii_rx : unsigned(7 downto 0) := (others => '-'); - signal mii_tx : unsigned(7 downto 0); - signal mii_rx_dv : std_logic := '0'; - signal mii_rx_er : std_logic := '0'; - signal mii_tx_en : std_logic; - signal mii_tx_er : std_logic; - signal mii_crs : std_logic := '0'; - signal mii_col : std_logic := '0'; - signal mii_gtx_clk : std_logic; + signal mii_rx_clk_board : std_logic := '1'; + signal mii_tx_clk_board : std_logic := '1'; + signal mii_rx_clk : std_logic := '1'; + signal mii_tx_clk : std_logic := '1'; + signal mii_rx : unsigned(7 downto 0) := (others => '-'); + signal mii_tx : unsigned(7 downto 0); + signal mii_rx_dv : std_logic := '0'; + signal mii_rx_er : std_logic := '0'; + signal mii_tx_en : std_logic; + signal mii_tx_er : std_logic; + signal mii_crs : std_logic := '0'; + signal mii_col : std_logic := '0'; + signal mii_gtx_clk : std_logic := '0'; - signal loop_back_en : std_logic := '0'; + signal loop_back_en : std_logic := '0'; + signal gigabit_rx_en : std_logic := '0'; + signal gigabit_tx_en : std_logic := '0'; - signal pktgen_tx : unsigned(7 downto 0); - signal pktgen_tx_en : std_logic; - signal pktgen_tx_er : std_logic; - signal pktgen_en : std_logic := '0'; - signal pktgen_gigabit : std_logic := '0'; - signal pktgen_fcs_en : std_logic := '0'; - signal dat_o_cnt_en : std_logic := '0'; - signal dat_o_cnt_rst : std_logic := '1'; - signal dat_o_cnt : natural; - signal pkt_count : natural; + signal pktgen_tx : unsigned(7 downto 0); + signal pktgen_tx_en : std_logic; + signal pktgen_tx_er : std_logic; + signal pktgen_en : std_logic := '0'; + signal pktgen_gigabit : std_logic := '0'; + signal pktgen_fcs_en : std_logic := '0'; + signal dat_o_cnt_en : std_logic := '0'; + signal dat_o_cnt_rst : std_logic := '1'; + signal dat_o_cnt : natural; + signal pkt_count : natural; type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free); signal emac_action : emac_action_t; @@ -164,8 +167,14 @@ MII_CLK_GEN: process mii_tx_clk <= not mii_tx_clk; end process; - mii_rx_clk_board <= mii_rx_clk; - mii_tx_clk_board <= mii_tx_clk; +GMII_CLK_GEN: process + begin + wait for GMII_CLK_PERIOD/2; + mii_gtx_clk <= not mii_gtx_clk; + end process; + + mii_rx_clk_board <= mii_gtx_clk when gigabit_rx_en = '1' else mii_rx_clk; + mii_tx_clk_board <= mii_gtx_clk when gigabit_tx_en = '1' else mii_tx_clk; DAT_O_register: process(CLK) @@ -201,6 +210,7 @@ STIMULUS: process procedure emac_tx_reset_100mbps is begin + gigabit_tx_en <= '0'; CYC_I <= '1'; wait until rising_edge(CLK) and SRDY_O = '1'; DAT_I <= X"A000_0000"; @@ -216,6 +226,7 @@ STIMULUS: process procedure emac_rx_reset_100mbps is begin + gigabit_rx_en <= '0'; CYC_I <= '1'; wait until rising_edge(CLK) and SRDY_O = '1'; DAT_I <= X"A000_0000"; @@ -231,6 +242,7 @@ STIMULUS: process procedure emac_tx_reset_1000mbps is begin + gigabit_tx_en <= '1'; CYC_I <= '1'; wait until rising_edge(CLK) and SRDY_O = '1'; DAT_I <= X"E000_0000"; @@ -246,6 +258,7 @@ STIMULUS: process procedure emac_rx_reset_1000mbps is begin + gigabit_rx_en <= '1'; CYC_I <= '1'; wait until rising_edge(CLK) and SRDY_O = '1'; DAT_I <= X"E000_0000"; @@ -504,9 +517,9 @@ STIMULUS: process wait for 6*MII_CLK_PERIOD; RST <= '0'; wait for 60*CLK_PERIOD; - emac_rx_reset_100mbps; - emac_tx_reset_100mbps; - pktgen_gigabit <= '0'; + emac_rx_reset_1000mbps; + emac_tx_reset_1000mbps; + pktgen_gigabit <= '1'; pktgen_fcs_en <= '1'; wait for 60*CLK_PERIOD; @@ -533,7 +546,7 @@ STIMULUS: process wait for 60*CLK_PERIOD; - wait until rising_edge(mii_tx_clk) and mii_tx_en = '0'; + wait until rising_edge(mii_tx_clk_board) and mii_tx_en = '0'; loop_back_en <= '1';