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Cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/trunk@21 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-09-21 18:54:53 +00:00
parent 48f5a19d30
commit a2c574150f
1 changed files with 17 additions and 34 deletions
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lib/CPUs/MIPS/src/core/mips_bui.vhd
+17 -34
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@@ -125,15 +125,11 @@ END COMPONENT;
signal imem_addr : word_t; signal imem_addr : word_t;
signal imem_mem_out_en : std_logic; signal imem_mem_out_en : std_logic;
signal dmem_mem_out_en : std_logic; signal dmem_mem_out_en : std_logic;
signal imem_valid : std_logic;
signal dmem_valid : std_logic;
signal dmem_ack : std_logic; signal dmem_ack : std_logic;
signal dcache_req : std_logic;
signal dcache_busy1 : std_logic; signal dcache_busy1 : std_logic;
signal dcache_busy2 : std_logic; signal dcache_busy2 : std_logic;
signal icache_busy : std_logic; signal icache_busy : std_logic;
signal bus_req : std_logic; signal bus_req : std_logic;
signal bus_bsy : std_logic;
signal icache_mem_en : std_logic; signal icache_mem_en : std_logic;
signal icache_mem_req : std_logic; signal icache_mem_req : std_logic;
signal icache_mem_gnt : std_logic; signal icache_mem_gnt : std_logic;
@@ -142,14 +138,13 @@ END COMPONENT;
signal dcache_mem_req : std_logic; signal dcache_mem_req : std_logic;
signal dcache_mem_gnt : std_logic; signal dcache_mem_gnt : std_logic;
signal dcache_mem_addr : word_t; signal dcache_mem_addr : word_t;
signal contention : std_logic;
signal dcached : std_logic; signal dcached : std_logic;
signal duncached_access : std_logic; signal duncached_access : std_logic;
signal dcache_en : std_logic;
begin begin
mem_ce <= mem_rdy and bus_req; mem_ce <= mem_rdy and bus_req;
contention <= dcache_req and icache_mem_req;
cpu_imem_rdy <= not icache_busy after 4.5 ns; cpu_imem_rdy <= not icache_busy after 4.5 ns;
-- cpu_imem_din <= imem_din; -- cpu_imem_din <= imem_din;
@@ -177,7 +172,7 @@ inst_icache : icache
mem_gnt => icache_mem_gnt, mem_gnt => icache_mem_gnt,
mem_addr => icache_mem_addr, mem_addr => icache_mem_addr,
mem_din => mem_din, mem_din => mem_din,
mem_valid => imem_valid, mem_valid => mem_valid,
mem_rdy => mem_rdy mem_rdy => mem_rdy
); );
@@ -192,7 +187,7 @@ inst_dcache : dcache
clk => clk, clk => clk,
rst => rst, rst => rst,
en => dcached, en => dcached,
cpu_en => cpu_dmem_en, cpu_en => dcache_en,
cpu_r_wn => cpu_dmem_re, cpu_r_wn => cpu_dmem_re,
cpu_we => cpu_dmem_we, cpu_we => cpu_dmem_we,
cpu_addr => cpu_dmem_addr, cpu_addr => cpu_dmem_addr,
@@ -204,27 +199,26 @@ inst_dcache : dcache
mem_en => dcache_mem_en, mem_en => dcache_mem_en,
mem_addr => dcache_mem_addr, mem_addr => dcache_mem_addr,
mem_din => mem_din, mem_din => mem_din,
mem_valid => dmem_valid, mem_valid => mem_valid,
mem_rdy => mem_rdy mem_rdy => mem_rdy
); );
dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0'; dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0';
cpu_dmem_din <= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns; cpu_dmem_din <= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns;
dcache_en <= cpu_dmem_en and not dcache_busy1;
dcache_flags: dcache_flags:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
dcache_busy1 <= '0'; dcache_busy1 <= '0';
dcache_req <= '0';
else else
duncached_access <= '0'; duncached_access <= '0';
if dmem_ack = '1' then if dmem_ack = '1' then
duncached_access <= '1'; duncached_access <= '1';
dcache_req <= '0';
if dmem_re = '1' then if dmem_re = '1' then
if dmem_valid = '1' then if mem_valid = '1' then
dcache_busy1 <= '0'; dcache_busy1 <= '0';
end if; end if;
else else
@@ -232,10 +226,8 @@ dcache_flags:
end if; end if;
end if; end if;
if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then
dcache_req <= '1';
dcache_busy1 <= '1'; dcache_busy1 <= '1';
if dcached = '1' and cpu_dmem_re = '1' then if dcached = '1' and cpu_dmem_re = '1' then
dcache_req <= '0';
dcache_busy1 <= '0'; dcache_busy1 <= '0';
end if; end if;
end if; end if;
@@ -262,7 +254,7 @@ dcache_data:
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
dmem_din <= (others => '0'); dmem_din <= (others => '0');
elsif dmem_valid = '1' then elsif dcache_busy1 = '1' and mem_valid = '1' then
dmem_din <= mem_din; dmem_din <= mem_din;
end if; end if;
end if; end if;
@@ -281,17 +273,14 @@ bus_state_next:
end process; end process;
bus_state: bus_state:
process(s, icache_mem_en, icache_mem_req, dcache_mem_req, dcache_mem_en, dcache_req, dmem_re, mem_rdy, mem_valid) process(s, icache_mem_en, icache_mem_req, dcache_busy1, dcache_mem_req, dcache_mem_en, dmem_re, mem_rdy, mem_valid)
begin begin
imem_mem_out_en <= '0'; imem_mem_out_en <= '0';
dmem_mem_out_en <= '0'; dmem_mem_out_en <= '0';
icache_mem_gnt <= '0'; icache_mem_gnt <= '0';
dcache_mem_gnt <= '0'; dcache_mem_gnt <= '0';
imem_valid <= '0';
dmem_valid <= '0';
dmem_ack <= '0'; dmem_ack <= '0';
bus_bsy <= '1';
sn <= s; sn <= s;
case s is case s is
@@ -300,18 +289,15 @@ bus_state:
sn <= ready; sn <= ready;
end if; end if;
when ready => when ready =>
bus_bsy <= not mem_rdy; if dcache_busy1 = '1' then
if dcache_req = '1' then if mem_rdy = '1' then
if dcache_busy1 = '1' then dmem_mem_out_en <= '1';
if mem_rdy = '1' then if dmem_re = '0' then
dmem_mem_out_en <= '1'; sn <= d_bus_finish;
if dmem_re = '0' then else
sn <= d_bus_finish; sn <= d_bus_access;
else
sn <= d_bus_access;
end if;
end if; end if;
end if; end if;
elsif icache_mem_req = '1' then elsif icache_mem_req = '1' then
sn <= i_cache_bus_access; sn <= i_cache_bus_access;
elsif dcache_mem_req = '1' then elsif dcache_mem_req = '1' then
@@ -324,7 +310,6 @@ bus_state:
elsif icache_mem_req = '0' then elsif icache_mem_req = '0' then
sn <= ready; sn <= ready;
end if; end if;
imem_valid <= mem_valid;
when d_cache_bus_access => when d_cache_bus_access =>
dcache_mem_gnt <= '1'; dcache_mem_gnt <= '1';
if dcache_mem_en = '1' then if dcache_mem_en = '1' then
@@ -332,11 +317,9 @@ bus_state:
elsif dcache_mem_req = '0' then elsif dcache_mem_req = '0' then
sn <= ready; sn <= ready;
end if; end if;
dmem_valid <= mem_valid;
when d_bus_access => when d_bus_access =>
if mem_valid = '1' then if mem_valid = '1' then
dmem_ack <= '1'; dmem_ack <= '1';
dmem_valid <= '1';
sn <= ready; sn <= ready;
end if; end if;
when d_bus_finish => when d_bus_finish =>