From a2c574150fb6061da146398e91d4e246a1687ce2 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 21 Sep 2008 18:54:53 +0000 Subject: [PATCH] Cleaned up git-svn-id: http://moon:8086/svn/vhdl/trunk@21 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_bui.vhd | 51 ++++++++++------------------- 1 file changed, 17 insertions(+), 34 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd index d5402b0..c11b994 100644 --- a/lib/CPUs/MIPS/src/core/mips_bui.vhd +++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd @@ -125,15 +125,11 @@ END COMPONENT; signal imem_addr : word_t; signal imem_mem_out_en : std_logic; signal dmem_mem_out_en : std_logic; - signal imem_valid : std_logic; - signal dmem_valid : std_logic; signal dmem_ack : std_logic; - signal dcache_req : std_logic; signal dcache_busy1 : std_logic; signal dcache_busy2 : std_logic; signal icache_busy : std_logic; signal bus_req : std_logic; - signal bus_bsy : std_logic; signal icache_mem_en : std_logic; signal icache_mem_req : std_logic; signal icache_mem_gnt : std_logic; @@ -142,14 +138,13 @@ END COMPONENT; signal dcache_mem_req : std_logic; signal dcache_mem_gnt : std_logic; signal dcache_mem_addr : word_t; - signal contention : std_logic; signal dcached : std_logic; signal duncached_access : std_logic; + signal dcache_en : std_logic; begin mem_ce <= mem_rdy and bus_req; - contention <= dcache_req and icache_mem_req; cpu_imem_rdy <= not icache_busy after 4.5 ns; -- cpu_imem_din <= imem_din; @@ -177,7 +172,7 @@ inst_icache : icache mem_gnt => icache_mem_gnt, mem_addr => icache_mem_addr, mem_din => mem_din, - mem_valid => imem_valid, + mem_valid => mem_valid, mem_rdy => mem_rdy ); @@ -192,7 +187,7 @@ inst_dcache : dcache clk => clk, rst => rst, en => dcached, - cpu_en => cpu_dmem_en, + cpu_en => dcache_en, cpu_r_wn => cpu_dmem_re, cpu_we => cpu_dmem_we, cpu_addr => cpu_dmem_addr, @@ -204,27 +199,26 @@ inst_dcache : dcache mem_en => dcache_mem_en, mem_addr => dcache_mem_addr, mem_din => mem_din, - mem_valid => dmem_valid, + mem_valid => mem_valid, mem_rdy => mem_rdy ); dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0'; cpu_dmem_din <= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns; - + dcache_en <= cpu_dmem_en and not dcache_busy1; + dcache_flags: process(clk) begin if rising_edge(clk) then if rst = '1' then dcache_busy1 <= '0'; - dcache_req <= '0'; else duncached_access <= '0'; if dmem_ack = '1' then duncached_access <= '1'; - dcache_req <= '0'; if dmem_re = '1' then - if dmem_valid = '1' then + if mem_valid = '1' then dcache_busy1 <= '0'; end if; else @@ -232,10 +226,8 @@ dcache_flags: end if; end if; if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then - dcache_req <= '1'; dcache_busy1 <= '1'; if dcached = '1' and cpu_dmem_re = '1' then - dcache_req <= '0'; dcache_busy1 <= '0'; end if; end if; @@ -262,7 +254,7 @@ dcache_data: if rising_edge(clk) then if rst = '1' then dmem_din <= (others => '0'); - elsif dmem_valid = '1' then + elsif dcache_busy1 = '1' and mem_valid = '1' then dmem_din <= mem_din; end if; end if; @@ -281,17 +273,14 @@ bus_state_next: end process; bus_state: - process(s, icache_mem_en, icache_mem_req, dcache_mem_req, dcache_mem_en, dcache_req, dmem_re, mem_rdy, mem_valid) + process(s, icache_mem_en, icache_mem_req, dcache_busy1, dcache_mem_req, dcache_mem_en, dmem_re, mem_rdy, mem_valid) begin imem_mem_out_en <= '0'; dmem_mem_out_en <= '0'; icache_mem_gnt <= '0'; dcache_mem_gnt <= '0'; - imem_valid <= '0'; - dmem_valid <= '0'; dmem_ack <= '0'; - bus_bsy <= '1'; sn <= s; case s is @@ -300,18 +289,15 @@ bus_state: sn <= ready; end if; when ready => - bus_bsy <= not mem_rdy; - if dcache_req = '1' then - if dcache_busy1 = '1' then - if mem_rdy = '1' then - dmem_mem_out_en <= '1'; - if dmem_re = '0' then - sn <= d_bus_finish; - else - sn <= d_bus_access; - end if; + if dcache_busy1 = '1' then + if mem_rdy = '1' then + dmem_mem_out_en <= '1'; + if dmem_re = '0' then + sn <= d_bus_finish; + else + sn <= d_bus_access; end if; - end if; + end if; elsif icache_mem_req = '1' then sn <= i_cache_bus_access; elsif dcache_mem_req = '1' then @@ -324,7 +310,6 @@ bus_state: elsif icache_mem_req = '0' then sn <= ready; end if; - imem_valid <= mem_valid; when d_cache_bus_access => dcache_mem_gnt <= '1'; if dcache_mem_en = '1' then @@ -332,11 +317,9 @@ bus_state: elsif dcache_mem_req = '0' then sn <= ready; end if; - dmem_valid <= mem_valid; when d_bus_access => if mem_valid = '1' then dmem_ack <= '1'; - dmem_valid <= '1'; sn <= ready; end if; when d_bus_finish =>