Initial revision

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2013-05-25 16:55:29 +00:00
parent 697dc4f0d3
commit 9f939c1e85
4 changed files with 685 additions and 0 deletions
@@ -0,0 +1,169 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.1 2013-05-25 16:55:29 jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.utils_pkg.all;
+
+------------------------------------------------------------------
+entity busmaster_sync is
+	Generic
+	(
+		DATA_WIDTH			: natural := 32;
+		FIFO_DEPTH			: natural := 4
+	);
+	Port 
+	(
+		clk					: in std_logic;
+		rst					: in std_logic;
+
+		cmd_cycle_finished	: out std_logic;
+		cmd_cycle_en		: in std_logic;
+		cmd_rdy				: out std_logic;
+		cmd_we				: in std_logic;
+		cmd_din				: in unsigned(DATA_WIDTH-1 downto 0);
+		cmd_addr			: in unsigned(31 downto 0);
+		cmd_sel				: in unsigned(DATA_WIDTH/8-1 downto 0);
+		cmd_rw				: in std_logic;
+		
+		cmd_dout			: out unsigned(DATA_WIDTH-1 downto 0);
+		cmd_dout_vld		: out std_logic;
+		cmd_dout_re			: in std_logic;
+		
+		-- J-BUS signals
+		ACK_I				: in std_logic;
+		SRDY_I				: in std_logic;
+		MDAT_I				: in unsigned(DATA_WIDTH-1 downto 0);
+		MDAT_O				: out unsigned(DATA_WIDTH-1 downto 0);
+		ADDR_O				: out unsigned(31 downto 0);
+		SEL_O				: out unsigned(DATA_WIDTH/8-1 downto 0);
+		WE_O				: out std_logic;
+		CYC_O				: out std_logic;
+		STB_O				: out std_logic;
+		MRDY_O				: out std_logic
+	);
+	end busmaster_sync;
+
+architecture Behavioral of busmaster_sync is
+
+	-- Bus output FIFO
+	signal busout_fifo_din		: unsigned(DATA_WIDTH+32+DATA_WIDTH/8+1-1 downto 0);
+	signal busout_fifo_dout		: unsigned(DATA_WIDTH+32+DATA_WIDTH/8+1-1 downto 0);
+	signal busout_fifo_re		: std_logic;
+	signal busout_fifo_we		: std_logic;
+	signal busout_fifo_full		: std_logic;
+	signal busout_fifo_empty	: std_logic;
+	
+	-- Bus input FIFO
+	signal busin_fifo_re		: std_logic;
+	signal busin_fifo_we		: std_logic;
+	signal busin_fifo_full		: std_logic;
+	signal busin_fifo_empty		: std_logic;
+	signal cycle_busy			: std_logic;
+	signal cmd_en				: std_logic;
+	signal cmd_read_en			: std_logic;
+	signal read_cnt				: integer range 0 to 65535;
+
+begin
+
+	cmd_en				<= cmd_cycle_en and cmd_we and not busout_fifo_full;
+	cmd_read_en			<= cmd_en and not cmd_rw;
+	
+	cmd_dout_vld		<= not busin_fifo_empty;
+	MRDY_O				<= not busin_fifo_full;
+	busin_fifo_we		<= ACK_I and cycle_busy;
+	busin_fifo_re		<= cmd_dout_re;
+	ADDR_O				<= busout_fifo_dout(31 downto 0);
+	MDAT_O				<= busout_fifo_dout(DATA_WIDTH+32-1 downto 32);
+	SEL_O				<= busout_fifo_dout(DATA_WIDTH+32+DATA_WIDTH/8-1 downto DATA_WIDTH+32);
+	WE_O				<= busout_fifo_dout(DATA_WIDTH+32+DATA_WIDTH/8);
+	
+	busout_fifo_din		<= cmd_rw & cmd_sel & cmd_din & cmd_addr;
+	
+	cmd_rdy				<= not busout_fifo_full;
+	
+	busout_fifo_we		<= cmd_en;
+	busout_fifo_re		<= SRDY_I and cycle_busy;
+	
+	
+	STB_O				<= not busout_fifo_empty;
+	CYC_O				<= cycle_busy;
+	cmd_cycle_finished	<= not cycle_busy;
+	
+proc_bus_read_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				read_cnt	<= 0;
+			elsif cmd_read_en = '1' and busin_fifo_we = '0' then
+				read_cnt <= read_cnt + 1;
+			elsif cmd_read_en = '0' and busin_fifo_we = '1' then
+				read_cnt <= read_cnt - 1;
+			end if;	
+		end if;
+	end process;	
+
+proc_cycle_busy:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				cycle_busy	 <= '0';
+			elsif cmd_cycle_en = '1' then
+				if cmd_we = '1' then
+					cycle_busy	 <= '1';
+				end if;
+			elsif read_cnt = 0 and busout_fifo_empty = '1' then
+				cycle_busy	 <= '0';
+			end if;
+		end if;
+	end process;	
+
+-- Bus input FIFO
+inst_BM_IN_FIFO: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width			=> NextExpBaseTwo(FIFO_DEPTH),
+		data_width			=> DATA_WIDTH,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk			=>	clk,
+		we			=>	busin_fifo_we,
+		re			=>	busin_fifo_re,
+		fifo_full	=>	busin_fifo_full,
+		fifo_empty	=>	busin_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  MDAT_I,
+		data_r		=>  cmd_dout
+	);
+	
+-- Bus output FIFO
+inst_BM_OUT_FIFO: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width			=> NextExpBaseTwo(FIFO_DEPTH),
+		data_width			=> busout_fifo_din'length,
+		do_last_read_update	=> false
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk			=>	clk,
+		we			=>	busout_fifo_we,
+		re			=>	busout_fifo_re,
+		fifo_full	=>	busout_fifo_full,
+		fifo_empty	=>	busout_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  busout_fifo_din,
+		data_r		=>  busout_fifo_dout
+	);
+
+end Behavioral;