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git-svn-id: http://moon:8086/svn/vhdl/trunk@81 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2008-10-19 21:12:34 +00:00
parent 0ea7ced5e3
commit 9e404bfb06
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lib/VGA_ctrl/src/vga_frontend.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:25:45 10/15/05
-- Design Name:
-- Module Name: vga_backend - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vga_types.all;
entity vga_frontend is
Generic
(
sys_freq : integer := 100E6;
fifo_depth : integer := 2048;
fifo_almost_full_thresh : natural := 2000;
fifo_almost_empty_thresh : natural := 48;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
Port
(
-- System signals
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
-- JBUS Master signals
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0);
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
MRDY_O : out STD_LOGIC;
ADDR_O : out unsigned(31 downto 0);
MDAT_I : in unsigned(31 downto 0);
MDAT_O : out unsigned(31 downto 0);
-- JBUS Slave signals
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
SDAT_I : in unsigned(31 downto 0);
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_out : out std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
vga_blank_n : out std_logic;
vga_sync_n : out std_logic;
vga_hsync : out std_logic;
vga_vsync : out std_logic
);
end vga_frontend;
architecture Behavioral of vga_frontend is
signal vga_clk : std_logic;
-- Color FIFO signals
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almost_empty : std_logic;
signal fifo_almost_full : std_logic;
signal fifo_color_re : std_logic;
signal fifo_color_we : std_logic;
signal fifo_color_out : color_t;
signal fifo_color_in : color_t;
-- Backend signals
signal scan_rdy : std_logic;
signal ctrl_scan_en : std_logic;
signal color_in : color_array_t;
signal color_op : color_op_t;
signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
signal stat_vga_rdy : std_logic;
signal stat_hready : std_logic;
signal stat_vready : std_logic;
signal stat_scan : std_logic;
signal stat_hscan : std_logic;
signal stat_vscan : std_logic;
signal stat_hsync : std_logic;
signal stat_vsync : std_logic;
signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1;
signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1;
-- CG signals
signal cg_en : std_logic;
signal cg_rdy : std_logic;
signal cg_draw : std_logic;
signal cg_clr_screen : std_logic;
signal cg_clr_line : std_logic;
signal cg_ascii_data : unsigned(7 downto 0);
signal cg_ascii_data_we : std_logic;
signal cg_ascii_posy_we : std_logic;
signal cg_ascii_posx_we : std_logic;
-- Bus master signals
constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
signal vga_mem_offset : unsigned(31 downto 0);
signal vga_scan_rdy : std_logic;
signal vga_master_en : std_logic;
signal request_cnt_rst : std_logic;
signal request_cnt_en : std_logic;
signal pixel_cnt_rst : std_logic;
signal read_bus_en : std_logic;
signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1;
type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
signal s, sn : vm_state_t;
begin
vga_clk_out <= vga_clk;
inst_vga_backend : entity work.vga_backend
GENERIC MAP
(
sys_freq => sys_freq,
tsvga => tsvga
)
PORT MAP
(
-- System signals
sys_rst => RST_I,
sys_clk => CLK_I,
-- Color channels
color_in => color_in,
color_op => color_op,
color_en => color_en,
-- Control signals
ctrl_scan_en => ctrl_scan_en,
-- Status signals
stat_vga_rdy => stat_vga_rdy,
stat_scan => stat_scan,
stat_hsync => stat_hsync,
stat_vsync => stat_vsync,
stat_hready => stat_hready,
stat_vready => stat_vready,
stat_hscan => stat_hscan,
stat_vscan => stat_vscan,
stat_hpos => stat_hpos,
stat_vpos => stat_vpos,
-- VGA domain signals
vga_clk_out => vga_clk,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_blank_n => vga_blank_n,
vga_sync_n => vga_sync_n,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
ctrl_scan_en <= '1';
color_en(0) <= not fifo_empty;
color_en(1) <= cg_draw;
color_in(0) <= fifo_color_out;
color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque
color_op <= op_over;
vga_scan_rdy <= stat_hready and stat_vready;
inst_linefifo: entity work.linefifo
GENERIC MAP
(
depth => fifo_depth,
almost_full_thresh => fifo_almost_full_thresh,
almost_empty_thresh => fifo_almost_empty_thresh
)
PORT MAP
(
rst => RST_I,
clk_w => CLK_I,
clk_r => vga_clk,
we_w => fifo_color_we,
re_r => fifo_color_re,
color_w => fifo_color_in,
color_r => fifo_color_out,
fifo_full => fifo_full,
fifo_empty => fifo_empty,
fifo_afull => fifo_almost_full,
fifo_aempty => fifo_almost_empty
);
fifo_color_in(r) <= MDAT_I(7 downto 0);
fifo_color_in(g) <= MDAT_I(15 downto 8);
fifo_color_in(b) <= MDAT_I(23 downto 16);
fifo_color_in(a) <= MDAT_I(31 downto 24);
fifo_color_re <= stat_scan;
fifo_color_we <= ACK_I and read_bus_en; -- TODO:
MRDY_O <= not fifo_full;
SEL_O <= (others => '0');
WE_O <= '0';
vga_master_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= init;
else
s <= sn;
end if;
end if;
end process;
vga_master:
process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
begin
CYC_O <= '0';
STB_O <= '0';
pixel_cnt_rst <= '0';
request_cnt_rst <= '0';
request_cnt_en <= '0';
read_bus_en <= '0';
sn <= s;
case s is
when init =>
if stat_vga_rdy = '1' then
sn <= idle;
end if;
when idle =>
pixel_cnt_rst <= '1';
if vga_master_en = '1' and vga_scan_rdy = '1' then
sn <= rdy;
end if;
when rdy =>
-- pixel_cnt_rst <= '1';
if fifo_almost_empty = '1' then
sn <= bus_request;
end if;
when bus_request =>
CYC_O <= '1';
request_cnt_rst <= '1';
if SRDY_I = '1' then
sn <= bus_access;
end if;
when bus_access =>
CYC_O <= '1';
STB_O <= '1';
request_cnt_en <= '1';
read_bus_en <= '1';
if fifo_almost_full = '1' then
sn <= bus_data;
end if;
when bus_data =>
CYC_O <= '1';
read_bus_en <= '1';
if read_cnt = request_cnt then
sn <= rdy;
if vga_master_en = '0' then
sn <= idle;
end if;
end if;
when others =>
sn <= idle;
end case;
end process;
request_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
request_cnt <= 0;
elsif request_cnt_en = '1' and SRDY_I = '1' then
if request_cnt /= MAX_REQUEST_CNT-1 then
request_cnt <= request_cnt + 1;
end if;
end if;
end if;
end process;
read_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
read_cnt <= 0;
elsif read_bus_en = '1' and ACK_I = '1' then
if read_cnt /= MAX_REQUEST_CNT-1 then
read_cnt <= read_cnt + 1;
end if;
end if;
end if;
end process;
pixel_counter:
process(CLK_I)
variable pixel_cntx : natural range 0 to tsvga.ts_h.ncyc_scan-1;
variable pixel_cnty : natural range 0 to tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
begin
if rising_edge(CLK_I) then
if pixel_cnt_rst = '1' then
pixel_cntx := 0;
pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
elsif request_cnt_en = '1' and SRDY_I = '1' then
if pixel_cntx /= tsvga.ts_h.ncyc_scan-1 then
pixel_cntx := pixel_cntx + 1;
else
pixel_cntx := 0;
if pixel_cnty /= 0 then
pixel_cnty := pixel_cnty - tsvga.ts_h.ncyc_scan;
else
pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
end if;
end if;
end if;
ADDR_O <= vga_mem_offset + to_unsigned(4*(pixel_cntx + pixel_cnty), 32);
end if;
end process;
inst_char_gen : entity work.char_gen
GENERIC MAP
(
tsvga => tsvga,
CHARACTER_SCALE => 1,
CHAR_ROM_SIZE_X => 8, -- Pixels
CHAR_ROM_SIZE_Y => 16, -- Pixels
CHAR_ROM_DEPTH => 256, -- Chars
MAX_CHAR_PER_LINE => 80, -- Chars
MAX_LINE_PER_FRAME => 32, -- Chars
CHAR_SPACING_X => 0, -- Pixels
CHAR_SPACING_Y => 0, -- Pixels
SCREEN_OFFSET_X => 16, -- Pixels
SCREEN_OFFSET_Y => 16 -- Pixels
)
PORT MAP
(
rst => RST_I,
sys_clk => CLK_I,
vga_clk => vga_clk,
ce => cg_en,
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,
clr_line => cg_clr_line,
ascii_data => cg_ascii_data,
ascii_data_we => cg_ascii_data_we,
ascii_posy_we => cg_ascii_posy_we,
ascii_posx_we => cg_ascii_posx_we,
ready => cg_rdy,
pos_x => stat_hpos,
pos_y => stat_vpos,
char_draw_en => cg_draw
);
SRDY_O <= CYC_I; -- and cg_rdy;
cg_ascii_data <= SDAT_I(7 downto 0);
cg_ascii_data_we <= ADDR_I(2) and CYC_I and STB_I and WE_I;
cg_ascii_posy_we <= ADDR_I(3) and CYC_I and STB_I and WE_I;
cg_ascii_posx_we <= ADDR_I(4) and CYC_I and STB_I and WE_I;
cg_clr_screen <= ADDR_I(5) and CYC_I and STB_I and WE_I;
cg_clr_line <= ADDR_I(6) and CYC_I and STB_I and WE_I;
SDAT_O <= X"0000000" & "000" & cg_rdy;
scan_rdy <= stat_hready and stat_vready;
cg_en <= stat_scan;
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= CYC_I and STB_I and not WE_I;
end if;
end if;
end process;
data_valid_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
vga_master_en <= '0';
vga_mem_offset <= X"40000000";
elsif (CYC_I and STB_I and WE_I) = '1' then
if ADDR_I(8) = '1' then
vga_master_en <= SDAT_I(0);
elsif ADDR_I(9) = '1' then
vga_mem_offset <= SDAT_I;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------
end Behavioral;