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- added generic 'simulate_tx' for output of TX-Data into simulation log

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git-svn-id: http://moon:8086/svn/vhdl/trunk@758 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-07 16:10:57 +00:00
parent c6983bd768
commit 9bf3b46cf3
2 changed files with 23 additions and 2 deletions
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lib/CPUs/MIPS/src/tb_mips_top.vhd
+5
View File
@@ -331,6 +331,10 @@ inst_sram_port : entity work.async_port_wb
); );
inst_uart : entity work.uart_wb inst_uart : entity work.uart_wb
GENERIC MAP
(
simulate_tx => true
)
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
@@ -399,6 +403,7 @@ FLASH_READ:
process(rst, flash_cs_n, flash_oe_n, flash_a) process(rst, flash_cs_n, flash_oe_n, flash_a)
type file_t is file of integer; type file_t is file of integer;
file load_flash : file_t open read_mode is "ucb.elf.flash.bin"; file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
-- file load_flash : file_t open read_mode is "test_dcache.flash.bin";
variable instr : integer; variable instr : integer;
variable index : natural; variable index : natural;
variable temp : signed(31 downto 0); variable temp : signed(31 downto 0);
lib/uart/uart_wb.vhd
+16
View File
@@ -1,8 +1,13 @@
LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; -- Imports the standard textio package.
ENTITY uart_wb IS ENTITY uart_wb IS
Generic
(
simulate_tx : boolean := false
);
Port Port
( (
CLK_I : in STD_LOGIC; CLK_I : in STD_LOGIC;
@@ -84,6 +89,8 @@ begin
------------------------------------------------------------------ ------------------------------------------------------------------
registers_write: registers_write:
process(CLK_I) process(CLK_I)
file output: text open write_mode is "STD_OUTPUT";
variable L : line;
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
reg_we_uart_tx <= '0'; reg_we_uart_tx <= '0';
@@ -95,8 +102,17 @@ registers_write:
case ADDR_I(5 downto 2) is case ADDR_I(5 downto 2) is
when "0000" => when "0000" =>
if simulate_tx then
if DAT_I(7 downto 0) /= X"0D" then
write(L, character'val(to_integer(DAT_I(7 downto 0))));
end if;
if DAT_I(7 downto 0) = X"0A" then
writeline(output, L);
end if;
else
reg_we_uart_tx <= '1'; reg_we_uart_tx <= '1';
reg_uart_tx <= DAT_I(7 downto 0); reg_uart_tx <= DAT_I(7 downto 0);
end if;
when "0001" => when "0001" =>
rx_int_en <= DAT_I(6); rx_int_en <= DAT_I(6);