diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd
index 65f9fb1..117de6b 100644
--- a/lib/CPUs/MIPS/src/tb_mips_top.vhd
+++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd
@@ -331,6 +331,10 @@ inst_sram_port : entity work.async_port_wb
 	);
 
 inst_uart : entity work.uart_wb
+	GENERIC MAP
+	(
+		simulate_tx		=> true
+	)
 	PORT MAP
 	(
 		CLK_I			=> clk,
@@ -399,6 +403,7 @@ FLASH_READ:
 	process(rst, flash_cs_n, flash_oe_n, flash_a)
 	type file_t is file of integer;
 	file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
+--	file load_flash : file_t open read_mode is "test_dcache.flash.bin";
 	variable instr : integer;
 	variable index : natural;
 	variable temp : signed(31 downto 0);
diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd
index f4f9fad..55cad91 100644
--- a/lib/uart/uart_wb.vhd
+++ b/lib/uart/uart_wb.vhd
@@ -1,8 +1,13 @@
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
 
 ENTITY uart_wb IS
+	Generic 
+	(
+		simulate_tx	: boolean := false
+	);
 	Port
 	(
 		CLK_I		: in  STD_LOGIC;
@@ -84,6 +89,8 @@ begin
 ------------------------------------------------------------------
 registers_write: 
 	process(CLK_I)
+	file output:	      text open write_mode is "STD_OUTPUT"; 
+	variable L : line; 
 	begin
 		if rising_edge(CLK_I) then
 			reg_we_uart_tx	<= '0';
@@ -95,8 +102,17 @@ registers_write:
 				case ADDR_I(5 downto 2) is
 				
 				when "0000" =>
-					reg_we_uart_tx	<= '1';
-					reg_uart_tx		<= DAT_I(7 downto 0);
+					if simulate_tx then
+						if DAT_I(7 downto 0) /= X"0D" then
+							write(L, character'val(to_integer(DAT_I(7 downto 0))));
+						end if;	
+						if DAT_I(7 downto 0) = X"0A" then
+							writeline(output, L);
+						end if;
+					else	
+						reg_we_uart_tx	<= '1';
+						reg_uart_tx		<= DAT_I(7 downto 0);
+					end if;
 					
 				when "0001" =>
 					rx_int_en		<= DAT_I(6);