- added generic 'simulate_tx' for output of TX-Data into simulation log

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git-svn-id: http://moon:8086/svn/vhdl/trunk@758 cc03376c-175c-47c8-b038-4cd826a8556b

lib/uart/uart_wb.vhd

@@ -1,8 +1,13 @@
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
 
 ENTITY uart_wb IS
+	Generic 
+	(
+		simulate_tx	: boolean := false
+	);
 	Port
 	(
 		CLK_I		: in  STD_LOGIC;
@@ -84,6 +89,8 @@ begin
 ------------------------------------------------------------------
 registers_write: 
 	process(CLK_I)
+	file output:	      text open write_mode is "STD_OUTPUT"; 
+	variable L : line; 
 	begin
 		if rising_edge(CLK_I) then
 			reg_we_uart_tx	<= '0';
@@ -95,8 +102,17 @@ registers_write:
 				case ADDR_I(5 downto 2) is
 				
 				when "0000" =>
-					reg_we_uart_tx	<= '1';
-					reg_uart_tx		<= DAT_I(7 downto 0);
+					if simulate_tx then
+						if DAT_I(7 downto 0) /= X"0D" then
+							write(L, character'val(to_integer(DAT_I(7 downto 0))));
+						end if;	
+						if DAT_I(7 downto 0) = X"0A" then
+							writeline(output, L);
+						end if;
+					else	
+						reg_we_uart_tx	<= '1';
+						reg_uart_tx		<= DAT_I(7 downto 0);
+					end if;
 					
 				when "0001" =>
 					rx_int_en		<= DAT_I(6);