- added generic 'simulate_tx' for output of TX-Data into simulation log

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git-svn-id: http://moon:8086/svn/vhdl/trunk@758 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/tb_mips_top.vhd

@@ -331,6 +331,10 @@ inst_sram_port : entity work.async_port_wb
 	);
 
 inst_uart : entity work.uart_wb
+	GENERIC MAP
+	(
+		simulate_tx		=> true
+	)
 	PORT MAP
 	(
 		CLK_I			=> clk,
@@ -399,6 +403,7 @@ FLASH_READ:
 	process(rst, flash_cs_n, flash_oe_n, flash_a)
 	type file_t is file of integer;
 	file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
+--	file load_flash : file_t open read_mode is "test_dcache.flash.bin";
 	variable instr : integer;
 	variable index : natural;
 	variable temp : signed(31 downto 0);