- fixed cmd reg latching

git-svn-id: http://moon:8086/svn/vhdl/trunk@1284 cc03376c-175c-47c8-b038-4cd826a8556b

lib/spi/src/spi_master.vhd

@@ -61,14 +61,13 @@ ARCHITECTURE behavior OF spi_master IS
 	signal cat_fifo_dout			: unsigned(SIZEOF_CMD-1 downto 0);
 	signal cat_fifo_full			: std_logic;
 	signal cat_fifo_empty			: std_logic;
+	signal cat_fifo_re				: std_logic;
 
 	signal write_fifo_din			: unsigned(word_width-1 downto 0);
 	signal write_fifo_dout			: unsigned(word_width-1 downto 0);
 	signal write_fifo_full			: std_logic;
 	signal write_fifo_empty			: std_logic;
 
-	signal read_fifo_din			: unsigned(word_width-1 downto 0);
-	signal read_fifo_dout			: unsigned(word_width-1 downto 0);
 	signal read_fifo_full			: std_logic;
 	signal read_fifo_empty			: std_logic;
 	signal read_fifo_we				: std_logic;
@@ -121,7 +120,7 @@ begin
 		clk_w		=>	clk,
 		clk_r		=>	spi_clk,
 		we			=>	cmd_vld,
-		re			=>	xfer_start_en,
+		re			=>	cat_fifo_re,
 		fifo_full	=>	cat_fifo_full,
 		fifo_empty	=>	cat_fifo_empty,
 		fifo_afull	=>	open,
@@ -271,6 +270,7 @@ begin
 	din_rdy				<= not write_fifo_full;
 	slv_enable			<= '1';
 	read_fifo_we		<= '0';
+	cat_fifo_re			<= '0';
 	
 	case state is
 
@@ -311,6 +311,7 @@ begin
 
 	when finish =>
 		read_fifo_we	<= rx_enable;
+		cat_fifo_re		<= '1';
 		state_next		<= idle;
 		
 	when others =>

lib/spi/src/tb_spi_master.vhd

@@ -178,6 +178,18 @@ STIMULUS: process
 		wait until rising_edge(CLK) and mst_cmd_rdy = '1';
 		mst_cmd_vld	<= '0';
 		
+		wait until rising_edge(CLK);
+		mst_din			<= X"9000_0000";
+		mst_din_vld		<= '1';
+		wait until rising_edge(CLK) and mst_din_rdy = '1';
+		mst_din_vld		<= '0';
+
+		wait until rising_edge(CLK);
+		mst_cmd		<= to_cmd(16, 8);
+		mst_cmd_vld	<= '1';
+		wait until rising_edge(CLK) and mst_cmd_rdy = '1';
+		mst_cmd_vld	<= '0';
+
 --------------------------------------------------------
 		wait until rising_edge(CLK);
 		mst_din			<= X"C3AA55C1";