From 97543c8bbdbe87ebcacb437b2ec863aff484eb1f Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 4 Jun 2015 15:30:09 +0000 Subject: [PATCH] - fixed cmd reg latching git-svn-id: http://moon:8086/svn/vhdl/trunk@1284 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/spi/sim/tb_spi_master.wdo | 12 +++++++++--- lib/spi/src/spi_master.vhd | 7 ++++--- lib/spi/src/tb_spi_master.vhd | 12 ++++++++++++ 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/lib/spi/sim/tb_spi_master.wdo b/lib/spi/sim/tb_spi_master.wdo index b2fe1eb..21a71e6 100644 --- a/lib/spi/sim/tb_spi_master.wdo +++ b/lib/spi/sim/tb_spi_master.wdo @@ -19,7 +19,7 @@ add wave -noupdate -format Logic /tb_spi_master/miso add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/spi_clk_read add wave -noupdate -format Logic /tb_spi_master/mso add wave -noupdate -format Literal /tb_spi_master/ctrl -add wave -noupdate -format Literal /tb_spi_master/status +add wave -noupdate -format Literal -expand /tb_spi_master/status add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/slv_rx_shiftreg add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/slv_rx_valid_pipe add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/slv_rx_data @@ -37,6 +37,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/inst_spi_ma add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/shift_en add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/mosi add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/inst_spi_master/tx_shift_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/inst_spi_master/rx_shift_reg add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/sclk add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/inst_spi_master/xfer_count add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/inst_spi_master/cmd_reg @@ -56,6 +57,11 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/inst_spi_ma add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/inst_spi_master/write_fifo_dout add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/write_fifo_full add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/write_fifo_empty +add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/slv_enable +add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/rx_enable +add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/read_fifo_full +add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/read_fifo_empty +add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/read_fifo_we add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/spi_clk_write add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/spi_clk_read add wave -noupdate -format Literal /tb_spi_master/inst_spi_master/spi_rst_count @@ -63,7 +69,7 @@ add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/spi_rst add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/spi_clk_div_en add wave -noupdate -format Literal /tb_spi_master/inst_spi_master/spi_clk_div_count TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {43998205 ps} 0} +WaveRestoreCursors {{Cursor 1} {23780000 ps} 0} configure wave -namecolwidth 197 configure wave -valuecolwidth 131 configure wave -justifyvalue left @@ -77,4 +83,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {0 ps} {52500 ns} +WaveRestoreZoom {31046634 ps} {50997546 ps} diff --git a/lib/spi/src/spi_master.vhd b/lib/spi/src/spi_master.vhd index c60754c..bb33030 100644 --- a/lib/spi/src/spi_master.vhd +++ b/lib/spi/src/spi_master.vhd @@ -61,14 +61,13 @@ ARCHITECTURE behavior OF spi_master IS signal cat_fifo_dout : unsigned(SIZEOF_CMD-1 downto 0); signal cat_fifo_full : std_logic; signal cat_fifo_empty : std_logic; + signal cat_fifo_re : std_logic; signal write_fifo_din : unsigned(word_width-1 downto 0); signal write_fifo_dout : unsigned(word_width-1 downto 0); signal write_fifo_full : std_logic; signal write_fifo_empty : std_logic; - signal read_fifo_din : unsigned(word_width-1 downto 0); - signal read_fifo_dout : unsigned(word_width-1 downto 0); signal read_fifo_full : std_logic; signal read_fifo_empty : std_logic; signal read_fifo_we : std_logic; @@ -121,7 +120,7 @@ begin clk_w => clk, clk_r => spi_clk, we => cmd_vld, - re => xfer_start_en, + re => cat_fifo_re, fifo_full => cat_fifo_full, fifo_empty => cat_fifo_empty, fifo_afull => open, @@ -271,6 +270,7 @@ begin din_rdy <= not write_fifo_full; slv_enable <= '1'; read_fifo_we <= '0'; + cat_fifo_re <= '0'; case state is @@ -311,6 +311,7 @@ begin when finish => read_fifo_we <= rx_enable; + cat_fifo_re <= '1'; state_next <= idle; when others => diff --git a/lib/spi/src/tb_spi_master.vhd b/lib/spi/src/tb_spi_master.vhd index 7a8d8cd..fe4df17 100644 --- a/lib/spi/src/tb_spi_master.vhd +++ b/lib/spi/src/tb_spi_master.vhd @@ -178,6 +178,18 @@ STIMULUS: process wait until rising_edge(CLK) and mst_cmd_rdy = '1'; mst_cmd_vld <= '0'; + wait until rising_edge(CLK); + mst_din <= X"9000_0000"; + mst_din_vld <= '1'; + wait until rising_edge(CLK) and mst_din_rdy = '1'; + mst_din_vld <= '0'; + + wait until rising_edge(CLK); + mst_cmd <= to_cmd(16, 8); + mst_cmd_vld <= '1'; + wait until rising_edge(CLK) and mst_cmd_rdy = '1'; + mst_cmd_vld <= '0'; + -------------------------------------------------------- wait until rising_edge(CLK); mst_din <= X"C3AA55C1";