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- added ce

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git-svn-id: http://moon:8086/svn/vhdl/trunk@196 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-04 14:00:06 +00:00
parent 1738a6c0b6
commit 9675773b2a
3 changed files with 10 additions and 6 deletions
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lib/filter/src/fir_semi_parallel.vhd
+2
View File
@@ -52,6 +52,7 @@ Port
( (
rst : in std_logic; rst : in std_logic;
clk : in std_logic; clk : in std_logic;
ce : in std_logic;
h_addr : in natural range 0 to nstages*ntaps_per_stage-1; h_addr : in natural range 0 to nstages*ntaps_per_stage-1;
h_we : in std_logic; h_we : in std_logic;
h_in : in sfixed; h_in : in sfixed;
@@ -234,6 +235,7 @@ gen_stages:
( (
rst => rst, rst => rst,
clk => clk, clk => clk,
ce => ce,
x_in => x(i+1), x_in => x(i+1),
y_in => y(i), y_in => y(i),
h_in => coef_stage(i), h_in => coef_stage(i),
lib/filter/src/fir_stage_sys.vhd
+5 -4
View File
@@ -50,6 +50,7 @@ Port
( (
rst : in std_logic; rst : in std_logic;
clk : in std_logic; clk : in std_logic;
ce : in std_logic;
x_in : in sfixed; x_in : in sfixed;
y_in : in sfixed; y_in : in sfixed;
h_in : in sfixed; h_in : in sfixed;
@@ -96,7 +97,7 @@ begin
proc_xin: process(clk, x_in) proc_xin: process(clk, x_in)
begin begin
x_pipe(0) <= resize(x_in, x_pipe(0)); x_pipe(0) <= resize(x_in, x_pipe(0));
if rising_edge(clk) then if rising_edge(clk) and ce = '1' then
for i in 1 to input_latency loop for i in 1 to input_latency loop
x_pipe(i) <= x_pipe(i-1); x_pipe(i) <= x_pipe(i-1);
end loop; end loop;
@@ -108,7 +109,7 @@ begin
proc_hin: process(clk, h_in) proc_hin: process(clk, h_in)
begin begin
h_pipe(0) <= resize(h_in, h_pipe(0)); h_pipe(0) <= resize(h_in, h_pipe(0));
if rising_edge(clk) then if rising_edge(clk) and ce = '1' then
for i in 1 to coef_latency loop for i in 1 to coef_latency loop
h_pipe(i) <= h_pipe(i-1); h_pipe(i) <= h_pipe(i-1);
end loop; end loop;
@@ -120,7 +121,7 @@ begin
proc_pipe_reg: process(clk, xin, hin) proc_pipe_reg: process(clk, xin, hin)
begin begin
mult_pipe(0) <= resize(xin * hin, mult_pipe(0)); mult_pipe(0) <= resize(xin * hin, mult_pipe(0));
if rising_edge(clk) then if rising_edge(clk) and ce = '1' then
for i in 1 to mult_latency loop for i in 1 to mult_latency loop
mult_pipe(i) <= mult_pipe(i-1); mult_pipe(i) <= mult_pipe(i-1);
end loop; end loop;
@@ -135,7 +136,7 @@ begin
yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate); yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
if rst = '1' then if rst = '1' then
y_out <= to_sfixed(0, yout); y_out <= to_sfixed(0, yout);
else elsif ce = '1' then
y_out <= yout; y_out <= yout;
end if; end if;
end if; end if;
lib/filter/src/tb_fir_semi_parallel.vhd
+3 -2
View File
@@ -31,8 +31,8 @@ use work.PCK_FIO.all;
ENTITY tb_fir_semi_parallel IS ENTITY tb_fir_semi_parallel IS
Generic Generic
( (
ntaps_per_stage : integer := 32; ntaps_per_stage : integer := 16;
nstages : integer := 4; nstages : integer := 2;
nbits_in : integer := 32; nbits_in : integer := 32;
nbits_in_frac : integer := 30; nbits_in_frac : integer := 30;
nbits_stages : integer := 32; nbits_stages : integer := 32;
@@ -114,6 +114,7 @@ BEGIN
( (
rst => rst, rst => rst,
clk => clk, clk => clk,
ce => '1',
h_addr => h_addr, h_addr => h_addr,
h_we => h_we, h_we => h_we,
h_in => h_in, h_in => h_in,