From 9675773b2a2b56cc08be3bff7f631b3b28ce835e Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 4 Jan 2009 14:00:06 +0000 Subject: [PATCH] - added ce git-svn-id: http://moon:8086/svn/vhdl/trunk@196 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/filter/src/fir_semi_parallel.vhd | 2 ++ lib/filter/src/fir_stage_sys.vhd | 9 +++++---- lib/filter/src/tb_fir_semi_parallel.vhd | 5 +++-- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd index 14ecc82..96bcf63 100644 --- a/lib/filter/src/fir_semi_parallel.vhd +++ b/lib/filter/src/fir_semi_parallel.vhd @@ -52,6 +52,7 @@ Port ( rst : in std_logic; clk : in std_logic; + ce : in std_logic; h_addr : in natural range 0 to nstages*ntaps_per_stage-1; h_we : in std_logic; h_in : in sfixed; @@ -234,6 +235,7 @@ gen_stages: ( rst => rst, clk => clk, + ce => ce, x_in => x(i+1), y_in => y(i), h_in => coef_stage(i), diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd index d3538c8..8dd2b70 100644 --- a/lib/filter/src/fir_stage_sys.vhd +++ b/lib/filter/src/fir_stage_sys.vhd @@ -50,6 +50,7 @@ Port ( rst : in std_logic; clk : in std_logic; + ce : in std_logic; x_in : in sfixed; y_in : in sfixed; h_in : in sfixed; @@ -96,7 +97,7 @@ begin proc_xin: process(clk, x_in) begin x_pipe(0) <= resize(x_in, x_pipe(0)); - if rising_edge(clk) then + if rising_edge(clk) and ce = '1' then for i in 1 to input_latency loop x_pipe(i) <= x_pipe(i-1); end loop; @@ -108,7 +109,7 @@ begin proc_hin: process(clk, h_in) begin h_pipe(0) <= resize(h_in, h_pipe(0)); - if rising_edge(clk) then + if rising_edge(clk) and ce = '1' then for i in 1 to coef_latency loop h_pipe(i) <= h_pipe(i-1); end loop; @@ -120,7 +121,7 @@ begin proc_pipe_reg: process(clk, xin, hin) begin mult_pipe(0) <= resize(xin * hin, mult_pipe(0)); - if rising_edge(clk) then + if rising_edge(clk) and ce = '1' then for i in 1 to mult_latency loop mult_pipe(i) <= mult_pipe(i-1); end loop; @@ -135,7 +136,7 @@ begin yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate); if rst = '1' then y_out <= to_sfixed(0, yout); - else + elsif ce = '1' then y_out <= yout; end if; end if; diff --git a/lib/filter/src/tb_fir_semi_parallel.vhd b/lib/filter/src/tb_fir_semi_parallel.vhd index 404a041..5053ee1 100644 --- a/lib/filter/src/tb_fir_semi_parallel.vhd +++ b/lib/filter/src/tb_fir_semi_parallel.vhd @@ -31,8 +31,8 @@ use work.PCK_FIO.all; ENTITY tb_fir_semi_parallel IS Generic ( - ntaps_per_stage : integer := 32; - nstages : integer := 4; + ntaps_per_stage : integer := 16; + nstages : integer := 2; nbits_in : integer := 32; nbits_in_frac : integer := 30; nbits_stages : integer := 32; @@ -114,6 +114,7 @@ BEGIN ( rst => rst, clk => clk, + ce => '1', h_addr => h_addr, h_we => h_we, h_in => h_in,