- use RAM-based delayline

git-svn-id: http://moon:8086/svn/vhdl/trunk@206 cc03376c-175c-47c8-b038-4cd826a8556b
2009-01-05 10:06:14 +00:00
parent 245c01ad45
commit 90a889a5f8
1 changed files with 2 additions and 1 deletions
@@ -258,7 +258,7 @@ gen_stages:
 gen_delays:
 	for i in 0 to nstages-1 generate
 	begin
-		inst_delay_line : entity work.delay_line
+		inst_delay_line : entity work.delay_line(ram_based)
 		GENERIC MAP
 		(
 			nbits		=> nbits_stages,
@@ -268,6 +268,7 @@ gen_delays:
 		)
 		PORT MAP
 		(
+			rst			=> rst,
 			clk			=> clk,
 			ce			=> en,
 			shift_en	=> ce_array(i),