diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd
index 411becc..afc6653 100644
--- a/lib/filter/src/fir_semi_parallel.vhd
+++ b/lib/filter/src/fir_semi_parallel.vhd
@@ -258,7 +258,7 @@ gen_stages:
 gen_delays:
 	for i in 0 to nstages-1 generate
 	begin
-		inst_delay_line : entity work.delay_line
+		inst_delay_line : entity work.delay_line(ram_based)
 		GENERIC MAP
 		(
 			nbits		=> nbits_stages,
@@ -268,6 +268,7 @@ gen_delays:
 		)
 		PORT MAP
 		(
+			rst			=> rst,
 			clk			=> clk,
 			ce			=> en,
 			shift_en	=> ce_array(i),