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- use RAM-based delayline

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git-svn-id: http://moon:8086/svn/vhdl/trunk@206 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2009-01-05 10:06:14 +00:00
parent 245c01ad45
commit 90a889a5f8
1 changed files with 2 additions and 1 deletions
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lib/filter/src/fir_semi_parallel.vhd
+2 -1
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@@ -258,7 +258,7 @@ gen_stages:
gen_delays: gen_delays:
for i in 0 to nstages-1 generate for i in 0 to nstages-1 generate
begin begin
inst_delay_line : entity work.delay_line inst_delay_line : entity work.delay_line(ram_based)
GENERIC MAP GENERIC MAP
( (
nbits => nbits_stages, nbits => nbits_stages,
@@ -268,6 +268,7 @@ gen_delays:
) )
PORT MAP PORT MAP
( (
rst => rst,
clk => clk, clk => clk,
ce => en, ce => en,
shift_en => ce_array(i), shift_en => ce_array(i),