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- spi_master_wb: route through generics

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1289 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-06-04 20:27:50 +00:00
parent 53b731a4eb
commit 8eb6b3ff9e
2 changed files with 19 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/spi/src/spi_master.vhd
+11 -11
View File
@@ -9,7 +9,7 @@ use work.spi_types.all;
ENTITY spi_master IS ENTITY spi_master IS
Generic Generic
( (
word_width : natural := 32; WORD_WIDTH : natural := 32;
CAT_FIFO_DEPTH : natural := 4; CAT_FIFO_DEPTH : natural := 4;
DATA_FIFO_DEPTH : natural := 16 DATA_FIFO_DEPTH : natural := 16
); );
@@ -22,8 +22,8 @@ ENTITY spi_master IS
cmd : in cmd_t; cmd : in cmd_t;
din_vld : in STD_LOGIC; din_vld : in STD_LOGIC;
din_rdy : out STD_LOGIC; din_rdy : out STD_LOGIC;
din : in unsigned(word_width-1 downto 0); din : in unsigned(WORD_WIDTH-1 downto 0);
dout : out unsigned(word_width-1 downto 0); dout : out unsigned(WORD_WIDTH-1 downto 0);
dout_vld : out STD_LOGIC; dout_vld : out STD_LOGIC;
dout_re : in STD_LOGIC; dout_re : in STD_LOGIC;
shift_en : in STD_LOGIC; shift_en : in STD_LOGIC;
@@ -63,8 +63,8 @@ ARCHITECTURE behavior OF spi_master IS
signal cat_fifo_empty : std_logic; signal cat_fifo_empty : std_logic;
signal cat_fifo_re : std_logic; signal cat_fifo_re : std_logic;
signal write_fifo_din : unsigned(word_width-1 downto 0); signal write_fifo_din : unsigned(WORD_WIDTH-1 downto 0);
signal write_fifo_dout : unsigned(word_width-1 downto 0); signal write_fifo_dout : unsigned(WORD_WIDTH-1 downto 0);
signal write_fifo_full : std_logic; signal write_fifo_full : std_logic;
signal write_fifo_empty : std_logic; signal write_fifo_empty : std_logic;
@@ -72,11 +72,11 @@ ARCHITECTURE behavior OF spi_master IS
signal read_fifo_empty : std_logic; signal read_fifo_empty : std_logic;
signal read_fifo_we : std_logic; signal read_fifo_we : std_logic;
signal tx_shift_reg : unsigned(word_width-1 downto 0); signal tx_shift_reg : unsigned(WORD_WIDTH-1 downto 0);
signal rx_shift_reg : unsigned(word_width-1 downto 0); signal rx_shift_reg : unsigned(WORD_WIDTH-1 downto 0);
signal rx_shift_reg2 : unsigned(word_width-1 downto 0); signal rx_shift_reg2 : unsigned(WORD_WIDTH-1 downto 0);
signal word_cnt_pipe : unsigned(word_width-1 downto 0); signal word_cnt_pipe : unsigned(WORD_WIDTH-1 downto 0);
signal word_cnt_rst : std_logic; signal word_cnt_rst : std_logic;
signal data_load_en : std_logic; signal data_load_en : std_logic;
signal xfer_start_en : std_logic; signal xfer_start_en : std_logic;
@@ -135,7 +135,7 @@ begin
GENERIC MAP GENERIC MAP
( (
addr_width => NextExpBaseTwo(DATA_FIFO_DEPTH), addr_width => NextExpBaseTwo(DATA_FIFO_DEPTH),
data_width => word_width data_width => WORD_WIDTH
) )
PORT MAP PORT MAP
( (
@@ -157,7 +157,7 @@ begin
GENERIC MAP GENERIC MAP
( (
addr_width => NextExpBaseTwo(DATA_FIFO_DEPTH), addr_width => NextExpBaseTwo(DATA_FIFO_DEPTH),
data_width => word_width data_width => WORD_WIDTH
) )
PORT MAP PORT MAP
( (
lib/spi/src/spi_master_wb.vhd
+8 -1
View File
@@ -6,6 +6,11 @@ LIBRARY WORK;
USE WORK.spi_types.all; USE WORK.spi_types.all;
ENTITY spi_master_wb IS ENTITY spi_master_wb IS
Generic
(
CAT_FIFO_DEPTH : natural := 4;
DATA_FIFO_DEPTH : natural := 16
);
Port Port
( (
CLK_I : in STD_LOGIC; CLK_I : in STD_LOGIC;
@@ -55,7 +60,9 @@ begin
inst_spi_master : entity work.spi_master inst_spi_master : entity work.spi_master
GENERIC MAP GENERIC MAP
( (
word_width => 32 WORD_WIDTH => 32,
CAT_FIFO_DEPTH => CAT_FIFO_DEPTH,
DATA_FIFO_DEPTH => DATA_FIFO_DEPTH
) )
PORT MAP PORT MAP
( (