diff --git a/lib/spi/src/spi_master.vhd b/lib/spi/src/spi_master.vhd
index 47332f8..d889e2c 100644
--- a/lib/spi/src/spi_master.vhd
+++ b/lib/spi/src/spi_master.vhd
@@ -9,7 +9,7 @@ use work.spi_types.all;
 ENTITY spi_master IS
 	Generic
 	(
-		word_width			: natural := 32;
+		WORD_WIDTH			: natural := 32;
 		CAT_FIFO_DEPTH		: natural := 4;
 		DATA_FIFO_DEPTH		: natural := 16
 	);
@@ -22,8 +22,8 @@ ENTITY spi_master IS
 		cmd			: in  cmd_t;
 		din_vld		: in  STD_LOGIC;
 		din_rdy		: out STD_LOGIC;
-		din			: in  unsigned(word_width-1 downto 0);
-		dout		: out unsigned(word_width-1 downto 0);
+		din			: in  unsigned(WORD_WIDTH-1 downto 0);
+		dout		: out unsigned(WORD_WIDTH-1 downto 0);
 		dout_vld	: out STD_LOGIC;
 		dout_re		: in  STD_LOGIC;
 		shift_en	: in  STD_LOGIC;
@@ -63,8 +63,8 @@ ARCHITECTURE behavior OF spi_master IS
 	signal cat_fifo_empty			: std_logic;
 	signal cat_fifo_re				: std_logic;
 
-	signal write_fifo_din			: unsigned(word_width-1 downto 0);
-	signal write_fifo_dout			: unsigned(word_width-1 downto 0);
+	signal write_fifo_din			: unsigned(WORD_WIDTH-1 downto 0);
+	signal write_fifo_dout			: unsigned(WORD_WIDTH-1 downto 0);
 	signal write_fifo_full			: std_logic;
 	signal write_fifo_empty			: std_logic;
 
@@ -72,11 +72,11 @@ ARCHITECTURE behavior OF spi_master IS
 	signal read_fifo_empty			: std_logic;
 	signal read_fifo_we				: std_logic;
 
-	signal tx_shift_reg				: unsigned(word_width-1 downto 0);
-	signal rx_shift_reg				: unsigned(word_width-1 downto 0);
-	signal rx_shift_reg2			: unsigned(word_width-1 downto 0);
+	signal tx_shift_reg				: unsigned(WORD_WIDTH-1 downto 0);
+	signal rx_shift_reg				: unsigned(WORD_WIDTH-1 downto 0);
+	signal rx_shift_reg2			: unsigned(WORD_WIDTH-1 downto 0);
 	
-	signal word_cnt_pipe			: unsigned(word_width-1 downto 0);
+	signal word_cnt_pipe			: unsigned(WORD_WIDTH-1 downto 0);
 	signal word_cnt_rst				: std_logic;
 	signal data_load_en				: std_logic;
 	signal xfer_start_en			: std_logic;
@@ -135,7 +135,7 @@ begin
 	GENERIC MAP
 	(
 		addr_width	=> NextExpBaseTwo(DATA_FIFO_DEPTH),
-		data_width	=> word_width
+		data_width	=> WORD_WIDTH
 	)
 	PORT MAP
 	(
@@ -157,7 +157,7 @@ begin
 	GENERIC MAP
 	(
 		addr_width	=> NextExpBaseTwo(DATA_FIFO_DEPTH),
-		data_width	=> word_width
+		data_width	=> WORD_WIDTH
 	)
 	PORT MAP
 	(
diff --git a/lib/spi/src/spi_master_wb.vhd b/lib/spi/src/spi_master_wb.vhd
index decf357..5675481 100644
--- a/lib/spi/src/spi_master_wb.vhd
+++ b/lib/spi/src/spi_master_wb.vhd
@@ -6,6 +6,11 @@ LIBRARY WORK;
 USE WORK.spi_types.all;
 
 ENTITY spi_master_wb IS
+	Generic
+	(
+		CAT_FIFO_DEPTH		: natural := 4;
+		DATA_FIFO_DEPTH		: natural := 16
+	);
 	Port
 	(
 		CLK_I		: in  STD_LOGIC;
@@ -55,7 +60,9 @@ begin
 inst_spi_master : entity work.spi_master
 	GENERIC MAP
 	(
-		word_width	=> 32
+		WORD_WIDTH		=> 32,
+		CAT_FIFO_DEPTH	=> CAT_FIFO_DEPTH,
+		DATA_FIFO_DEPTH	=> DATA_FIFO_DEPTH
 	)
 	PORT MAP
 	(