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git-svn-id: http://moon:8086/svn/vhdl/trunk@138 cc03376c-175c-47c8-b038-4cd826a8556b
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:16:14 10/02/05
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-- Design Name:
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-- Module Name: cordic_stage - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use work.fixed_pkg.all;
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use work.nco_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity nco is
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Generic
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(
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nbits_wave : integer := 18;
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nbits_phase : integer := 16;
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nbits_lut_depth : integer := 12;
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nbits_dither : integer := 4;
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nbits_lfsr : integer := 12;
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q_phase : phase_relation_t := phase_90deg;
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has_pipe_reg : boolean := false;
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has_out_reg : boolean := false
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);
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Port
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(
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srst : in std_logic;
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clk : in std_logic;
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pacc_clr : in std_logic;
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pacc_inc : in std_logic;
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freq_in : in unsigned(nbits_phase-1 downto 0);
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freq_load : in std_logic;
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phase_in : in unsigned(nbits_phase-1 downto 0);
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phase_load : in std_logic;
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phase_out : out unsigned(nbits_phase-1 downto 0);
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wave_out_i : out sfixed;
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wave_out_q : out sfixed;
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out_valid : out std_logic;
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debug_out : out debug_out_t
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);
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end nco;
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architecture Behavioral of nco is
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COMPONENT wavelut
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Generic
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(
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nbits_wave : integer;
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nbits_wave_frac : integer;
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nbits_lut_depth : integer;
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q_phase : phase_relation_t;
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has_out_reg : boolean
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);
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Port
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(
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clk : in std_logic;
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rst : in std_logic;
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addr_valid : in std_logic;
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addr : in unsigned(nbits_lut_depth-1 downto 0);
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wave_i_out : out sfixed;
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wave_q_out : out sfixed;
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valid_out : out std_logic
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);
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END COMPONENT;
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-------------------------------------------------------------------------------
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constant nbits_wave_frac : integer := nbits_wave;
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-------------------------------------------------------------------------------
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constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
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signal phase : unsigned(nbits_phase-1 downto 0);
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signal freq_in_r : unsigned(nbits_phase-1 downto 0);
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signal phase_in_r : unsigned(nbits_phase-1 downto 0);
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signal lut_addr_ud : unsigned(nbits_lut_depth-1 downto 0);
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signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
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signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
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signal wave_i_ud, wave_q_ud : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
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type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
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signal lfsr : lfsr_t;
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signal lfsr_out : unsigned(nbits_dither-1 downto 0);
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signal lut_addr_valid, lfsr_valid, wave_d_valid, wave_ud_valid : std_logic;
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-------------------------------------------------------------------------------
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begin
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wave_out_i <= wave_i_d;
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wave_out_q <= wave_q_d;
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out_valid <= wave_d_valid;
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debug_out.lfsr <= (debug_out.lfsr'left downto (debug_out.lfsr'right+lfsr_out'left+1) => '0') & lfsr_out;
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debug_out.i_d <= to_real(wave_i_d);
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debug_out.q_d <= to_real(wave_q_d);
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debug_out.i_ud <= to_real(wave_i_ud);
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debug_out.q_ud <= to_real(wave_q_ud);
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------------------------------------------------------------
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proc_lfsr: process(srst, clk, lfsr, pacc_inc)
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variable lo : unsigned(nbits_dither-1 downto 0);
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begin
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if rising_edge(clk) then
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if srst = '1' then
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lfsr_valid <= '0';
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lfsr_out <= (others => '0');
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for i in lfsr'range loop
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lfsr(i) <= to_unsigned(2**i, nbits_lfsr);
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end loop;
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else
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lfsr_valid <= '0';
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if pacc_inc ='1' then
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lfsr_valid <= '1';
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lo := (others => '0');
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for i in lfsr'range loop
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if lfsr(i)(lfsr(i)'left) = '1' then
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lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
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else
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lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
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end if;
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end loop;
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for i in lfsr'range loop
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lo := lo + lfsr(i)(nbits_dither-1 downto 0);
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end loop;
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-- lo := lfsr(0)(nbits_dither downto 0);
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lfsr_out <= lo(nbits_dither-1 downto 0);
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------
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proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
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variable phase_accu : unsigned(nbits_phase-1 downto 0);
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begin
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if rising_edge(clk) then
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if srst = '1' then
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phase_accu := (others => '0');
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else
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phase <= phase_accu + phase_in_r;
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if pacc_clr = '1' then
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phase_accu := (others => '0');
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elsif pacc_inc = '1' then
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phase_accu := phase_accu + freq_in_r;
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end if;
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end if;
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end if;
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phase_out <= phase;
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end process;
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------------------------------------------------------------
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freq_in_reg: process(srst, clk, freq_load, freq_in)
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begin
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if rising_edge(clk) then
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if srst = '1' then
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freq_in_r <= (others => '0');
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elsif freq_load = '1' then
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freq_in_r <= freq_in;
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end if;
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end if;
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end process;
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------------------------------------------------------------
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phase_in_reg: process(srst, clk, phase_load, phase_in)
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begin
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if rising_edge(clk) then
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if srst = '1' then
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phase_in_r <= (others => '0');
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elsif phase_load = '1' then
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phase_in_r <= phase_in;
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end if;
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end if;
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end process;
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------------------------------------------------------------
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proc_pipe_reg: process(clk)
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variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
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begin
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if rising_edge(clk) then
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lut_addr_valid <= '0';
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if srst = '1' then
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lfsr_sum := (others => '0');
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elsif lfsr_valid = '1' then
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lut_addr_valid <= '1';
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lfsr_sum := lfsr_out + phase;
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end if;
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end if;
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lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
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lut_addr_ud <= phase(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
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end process;
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------------------------------------------------------------
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inst_wavelut_ud: wavelut
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GENERIC MAP
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(
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nbits_wave => nbits_wave,
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nbits_wave_frac => nbits_wave_frac,
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nbits_lut_depth => nbits_lut_depth,
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q_phase => q_phase,
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has_out_reg => has_out_reg
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)
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PORT MAP
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(
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rst => srst,
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clk => clk,
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addr_valid => lut_addr_valid,
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addr => lut_addr_ud,
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wave_i_out => wave_i_ud,
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wave_q_out => wave_q_ud,
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valid_out => wave_ud_valid
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);
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inst_wavelut_d: wavelut
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GENERIC MAP
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(
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nbits_wave => nbits_wave,
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nbits_wave_frac => nbits_wave_frac,
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nbits_lut_depth => nbits_lut_depth,
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q_phase => q_phase,
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has_out_reg => has_out_reg
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)
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PORT MAP
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(
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rst => srst,
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clk => clk,
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addr_valid => lut_addr_valid,
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addr => lut_addr_d,
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wave_i_out => wave_i_d,
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wave_q_out => wave_q_d,
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valid_out => wave_d_valid
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);
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------------------------------------------------------------
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end Behavioral;
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