diff --git a/lib/radio/nco/sim/tb_nco_lut.fdo b/lib/radio/nco/sim/tb_nco_lut.fdo new file mode 100644 index 0000000..65a0a26 --- /dev/null +++ b/lib/radio/nco/sim/tb_nco_lut.fdo @@ -0,0 +1,15 @@ +vlib work +vcom -explicit -93 "../../../fixed/fixed_pkg_c.vhd" +vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" +vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" +vcom -explicit -93 "../src/nco_pkg.vhd" +vcom -explicit -93 "../src/waverom_dual.vhd" +vcom -explicit -93 "../src/wavelut.vhd" +vcom -explicit -93 "../src/nco_lut_dbg.vhd" +vcom -explicit -93 "../src/tb_nco_lut.vhd" +vsim -t 1ps -lib work tb_nco +do {tb_nco_lut.wdo} +view wave +view structure +view signals +run 250us diff --git a/lib/radio/nco/sim/tb_nco_lut.wdo b/lib/radio/nco/sim/tb_nco_lut.wdo new file mode 100644 index 0000000..0fd0917 --- /dev/null +++ b/lib/radio/nco/sim/tb_nco_lut.wdo @@ -0,0 +1,46 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_nco/uut/srst +add wave -noupdate -format Logic /tb_nco/uut/clk +add wave -noupdate -format Logic /tb_nco/uut/pacc_clr +add wave -noupdate -format Logic /tb_nco/uut/pacc_inc +add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in +add wave -noupdate -format Logic /tb_nco/uut/freq_load +add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in +add wave -noupdate -format Logic /tb_nco/uut/phase_load +add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out +add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_i +add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_q +add wave -noupdate -format Logic /tb_nco/uut/out_valid +add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/debug_out +add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase +add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r +add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r +add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_ud +add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_d +add wave -noupdate -format Literal /tb_nco/uut/wave_i_d +add wave -noupdate -format Literal /tb_nco/uut/wave_q_d +add wave -noupdate -format Literal /tb_nco/uut/wave_i_ud +add wave -noupdate -format Literal /tb_nco/uut/wave_q_ud +add wave -noupdate -format Literal /tb_nco/uut/lfsr +add wave -noupdate -format Literal /tb_nco/uut/lfsr_out +add wave -noupdate -format Logic /tb_nco/uut/lut_addr_valid +add wave -noupdate -format Logic /tb_nco/uut/lfsr_valid +add wave -noupdate -format Logic /tb_nco/uut/wave_d_valid +add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {249141632 ps} 0} +configure wave -namecolwidth 193 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {249024188 ps} {250051359 ps} diff --git a/lib/radio/nco/src/nco_lut.vhd b/lib/radio/nco/src/nco_lut.vhd new file mode 100644 index 0000000..25b7f1d --- /dev/null +++ b/lib/radio/nco/src/nco_lut.vhd @@ -0,0 +1,223 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:16:14 10/02/05 +-- Design Name: +-- Module Name: cordic_stage - Behavioral +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; +use work.fixed_pkg.all; +use work.nco_pkg.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity nco is +Generic +( + nbits_wave : integer := 18; + nbits_phase : integer := 16; + nbits_lut_depth : integer := 12; + nbits_dither : integer := 4; + nbits_lfsr : integer := 12; + q_phase : phase_relation_t := phase_90deg; + has_pipe_reg : boolean := false; + has_out_reg : boolean := false +); +Port +( + srst : in std_logic; + clk : in std_logic; + pacc_clr : in std_logic; + pacc_inc : in std_logic; + freq_in : in unsigned(nbits_phase-1 downto 0); + freq_load : in std_logic; + phase_in : in unsigned(nbits_phase-1 downto 0); + phase_load : in std_logic; + phase_out : out unsigned(nbits_phase-1 downto 0); + wave_out_i : out sfixed; + wave_out_q : out sfixed; + out_valid : out std_logic +); +end nco; + +architecture Behavioral of nco is + + COMPONENT wavelut + Generic + ( + nbits_wave : integer; + nbits_wave_frac : integer; + nbits_lut_depth : integer; + q_phase : phase_relation_t; + has_out_reg : boolean + ); + Port + ( + clk : in std_logic; + rst : in std_logic; + addr_valid : in std_logic; + addr : in unsigned(nbits_lut_depth-1 downto 0); + wave_i_out : out sfixed; + wave_q_out : out sfixed; + valid_out : out std_logic + ); + END COMPONENT; + +------------------------------------------------------------------------------- + constant nbits_wave_frac : integer := nbits_wave; + +------------------------------------------------------------------------------- + constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 + + signal phase : unsigned(nbits_phase-1 downto 0); + signal freq_in_r : unsigned(nbits_phase-1 downto 0); + signal phase_in_r : unsigned(nbits_phase-1 downto 0); + signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0); + signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); + + type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); + signal lfsr : lfsr_t; + signal lfsr_out : unsigned(nbits_dither-1 downto 0); + signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic; + +------------------------------------------------------------------------------- +begin + + wave_out_i <= wave_i_d; + wave_out_q <= wave_q_d; + out_valid <= wave_d_valid; + +------------------------------------------------------------ + proc_lfsr: process(srst, clk, lfsr, pacc_inc) + variable lo : unsigned(nbits_dither-1 downto 0); + begin + if rising_edge(clk) then + if srst = '1' then + lfsr_valid <= '0'; + lfsr_out <= (others => '0'); + for i in lfsr'range loop + lfsr(i) <= to_unsigned(2**i, nbits_lfsr); + end loop; + else + lfsr_valid <= '0'; + if pacc_inc ='1' then + lfsr_valid <= '1'; + lo := (others => '0'); + for i in lfsr'range loop + if lfsr(i)(lfsr(i)'left) = '1' then + lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; + else + lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); + end if; + end loop; + for i in lfsr'range loop + lo := lo + lfsr(i)(nbits_dither-1 downto 0); + end loop; + -- lo := lfsr(0)(nbits_dither downto 0); + lfsr_out <= lo(nbits_dither-1 downto 0); + end if; + end if; + end if; + end process; + +------------------------------------------------------------ + proc_phase_accu: process(clk, phase) + variable phase_accu : unsigned(nbits_phase-1 downto 0); + + begin + if rising_edge(clk) then + if srst = '1' then + phase_accu := (others => '0'); + else + phase <= phase_accu + phase_in_r; + if pacc_clr = '1' then + phase_accu := (others => '0'); + elsif pacc_inc = '1' then + phase_accu := phase_accu + freq_in_r; + end if; + end if; + end if; + phase_out <= phase; + end process; + +------------------------------------------------------------ + freq_in_reg: process(srst, clk, freq_load, freq_in) + begin + if rising_edge(clk) then + if srst = '1' then + freq_in_r <= (others => '0'); + elsif freq_load = '1' then + freq_in_r <= freq_in; + end if; + end if; + end process; + +------------------------------------------------------------ + phase_in_reg: process(srst, clk, phase_load, phase_in) + begin + if rising_edge(clk) then + if srst = '1' then + phase_in_r <= (others => '0'); + elsif phase_load = '1' then + phase_in_r <= phase_in; + end if; + end if; + end process; + +------------------------------------------------------------ + proc_pipe_reg: process(clk) + variable lfsr_sum : unsigned(nbits_phase-1 downto 0); + begin + if rising_edge(clk) then + lut_addr_valid <= '0'; + if srst = '1' then + lfsr_sum := (others => '0'); + elsif lfsr_valid = '1' then + lut_addr_valid <= '1'; + lfsr_sum := lfsr_out + phase; + end if; + end if; + lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); + end process; + +------------------------------------------------------------ + inst_wavelut_d: wavelut + GENERIC MAP + ( + nbits_wave => nbits_wave, + nbits_wave_frac => nbits_wave_frac, + nbits_lut_depth => nbits_lut_depth, + q_phase => q_phase, + has_out_reg => has_out_reg + ) + PORT MAP + ( + rst => srst, + clk => clk, + addr_valid => lut_addr_valid, + addr => lut_addr_d, + wave_i_out => wave_i_d, + wave_q_out => wave_q_d, + valid_out => wave_d_valid + ); + +------------------------------------------------------------ +end Behavioral; diff --git a/lib/radio/nco/src/nco_lut_dbg.vhd b/lib/radio/nco/src/nco_lut_dbg.vhd new file mode 100644 index 0000000..c0038a9 --- /dev/null +++ b/lib/radio/nco/src/nco_lut_dbg.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:16:14 10/02/05 +-- Design Name: +-- Module Name: cordic_stage - Behavioral +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; +use work.fixed_pkg.all; +use work.nco_pkg.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity nco is +Generic +( + nbits_wave : integer := 18; + nbits_phase : integer := 16; + nbits_lut_depth : integer := 12; + nbits_dither : integer := 4; + nbits_lfsr : integer := 12; + q_phase : phase_relation_t := phase_90deg; + has_pipe_reg : boolean := false; + has_out_reg : boolean := false +); +Port +( + srst : in std_logic; + clk : in std_logic; + pacc_clr : in std_logic; + pacc_inc : in std_logic; + freq_in : in unsigned(nbits_phase-1 downto 0); + freq_load : in std_logic; + phase_in : in unsigned(nbits_phase-1 downto 0); + phase_load : in std_logic; + phase_out : out unsigned(nbits_phase-1 downto 0); + wave_out_i : out sfixed; + wave_out_q : out sfixed; + out_valid : out std_logic; + debug_out : out debug_out_t +); +end nco; + +architecture Behavioral of nco is + + COMPONENT wavelut + Generic + ( + nbits_wave : integer; + nbits_wave_frac : integer; + nbits_lut_depth : integer; + q_phase : phase_relation_t; + has_out_reg : boolean + ); + Port + ( + clk : in std_logic; + rst : in std_logic; + addr_valid : in std_logic; + addr : in unsigned(nbits_lut_depth-1 downto 0); + wave_i_out : out sfixed; + wave_q_out : out sfixed; + valid_out : out std_logic + ); + END COMPONENT; + +------------------------------------------------------------------------------- + constant nbits_wave_frac : integer := nbits_wave; + +------------------------------------------------------------------------------- + constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 + + signal phase : unsigned(nbits_phase-1 downto 0); + signal freq_in_r : unsigned(nbits_phase-1 downto 0); + signal phase_in_r : unsigned(nbits_phase-1 downto 0); + signal lut_addr_ud : unsigned(nbits_lut_depth-1 downto 0); + signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0); + signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); + signal wave_i_ud, wave_q_ud : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); + + type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); + signal lfsr : lfsr_t; + signal lfsr_out : unsigned(nbits_dither-1 downto 0); + signal lut_addr_valid, lfsr_valid, wave_d_valid, wave_ud_valid : std_logic; + +------------------------------------------------------------------------------- +begin + + wave_out_i <= wave_i_d; + wave_out_q <= wave_q_d; + out_valid <= wave_d_valid; + + debug_out.lfsr <= (debug_out.lfsr'left downto (debug_out.lfsr'right+lfsr_out'left+1) => '0') & lfsr_out; + debug_out.i_d <= to_real(wave_i_d); + debug_out.q_d <= to_real(wave_q_d); + debug_out.i_ud <= to_real(wave_i_ud); + debug_out.q_ud <= to_real(wave_q_ud); + +------------------------------------------------------------ + proc_lfsr: process(srst, clk, lfsr, pacc_inc) + variable lo : unsigned(nbits_dither-1 downto 0); + begin + if rising_edge(clk) then + if srst = '1' then + lfsr_valid <= '0'; + lfsr_out <= (others => '0'); + for i in lfsr'range loop + lfsr(i) <= to_unsigned(2**i, nbits_lfsr); + end loop; + else + lfsr_valid <= '0'; + if pacc_inc ='1' then + lfsr_valid <= '1'; + lo := (others => '0'); + for i in lfsr'range loop + if lfsr(i)(lfsr(i)'left) = '1' then + lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; + else + lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); + end if; + end loop; + for i in lfsr'range loop + lo := lo + lfsr(i)(nbits_dither-1 downto 0); + end loop; + -- lo := lfsr(0)(nbits_dither downto 0); + lfsr_out <= lo(nbits_dither-1 downto 0); + end if; + end if; + end if; + end process; + +------------------------------------------------------------ + proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r) + variable phase_accu : unsigned(nbits_phase-1 downto 0); + + begin + if rising_edge(clk) then + if srst = '1' then + phase_accu := (others => '0'); + else + phase <= phase_accu + phase_in_r; + if pacc_clr = '1' then + phase_accu := (others => '0'); + elsif pacc_inc = '1' then + phase_accu := phase_accu + freq_in_r; + end if; + end if; + end if; + phase_out <= phase; + end process; + +------------------------------------------------------------ + freq_in_reg: process(srst, clk, freq_load, freq_in) + begin + if rising_edge(clk) then + if srst = '1' then + freq_in_r <= (others => '0'); + elsif freq_load = '1' then + freq_in_r <= freq_in; + end if; + end if; + end process; + +------------------------------------------------------------ + phase_in_reg: process(srst, clk, phase_load, phase_in) + begin + if rising_edge(clk) then + if srst = '1' then + phase_in_r <= (others => '0'); + elsif phase_load = '1' then + phase_in_r <= phase_in; + end if; + end if; + end process; + +------------------------------------------------------------ + proc_pipe_reg: process(clk) + variable lfsr_sum : unsigned(nbits_phase-1 downto 0); + begin + if rising_edge(clk) then + lut_addr_valid <= '0'; + if srst = '1' then + lfsr_sum := (others => '0'); + elsif lfsr_valid = '1' then + lut_addr_valid <= '1'; + lfsr_sum := lfsr_out + phase; + end if; + end if; + lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); + lut_addr_ud <= phase(nbits_phase-1 downto nbits_phase-nbits_lut_depth); + end process; + +------------------------------------------------------------ + inst_wavelut_ud: wavelut + GENERIC MAP + ( + nbits_wave => nbits_wave, + nbits_wave_frac => nbits_wave_frac, + nbits_lut_depth => nbits_lut_depth, + q_phase => q_phase, + has_out_reg => has_out_reg + ) + PORT MAP + ( + rst => srst, + clk => clk, + addr_valid => lut_addr_valid, + addr => lut_addr_ud, + wave_i_out => wave_i_ud, + wave_q_out => wave_q_ud, + valid_out => wave_ud_valid + ); + + inst_wavelut_d: wavelut + GENERIC MAP + ( + nbits_wave => nbits_wave, + nbits_wave_frac => nbits_wave_frac, + nbits_lut_depth => nbits_lut_depth, + q_phase => q_phase, + has_out_reg => has_out_reg + ) + PORT MAP + ( + rst => srst, + clk => clk, + addr_valid => lut_addr_valid, + addr => lut_addr_d, + wave_i_out => wave_i_d, + wave_q_out => wave_q_d, + valid_out => wave_d_valid + ); + +------------------------------------------------------------ +end Behavioral; diff --git a/lib/radio/nco/src/tb_nco_lut.vhd b/lib/radio/nco/src/tb_nco_lut.vhd new file mode 100644 index 0000000..f2d930a --- /dev/null +++ b/lib/radio/nco/src/tb_nco_lut.vhd @@ -0,0 +1,299 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:16:42 13.05.2007 +-- Design Name: tb_nco +-- Module Name: tb_nco.vhd +-- Project Name: nco +-- Target Device: +-- Tool versions: +-- Description: +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; +use std.textio.all; -- Imports the standard textio package. + +library work; +use work.fixed_pkg.all; +use work.nco_pkg.all; +use work.PCK_FIO.all; + +ENTITY tb_nco IS + Generic ( + nbits_wave : integer := 18; + nbits_phase : integer := 16; + nbits_lut_depth : integer := 12; + nbits_dither : integer := 4; + nbits_lfsr : integer := 12; + q_phase : phase_relation_t := phase_270deg; + has_pipe_reg : boolean := true; + has_out_reg : boolean := true + ); +END tb_nco; + +ARCHITECTURE behavior OF tb_nco IS + + -- Component Declaration for the Unit Under Test (UUT) + COMPONENT nco + GENERIC ( + nbits_wave : integer; + nbits_phase : integer; + nbits_lut_depth : integer; + nbits_dither : integer; + nbits_lfsr : integer; + q_phase : phase_relation_t; + has_pipe_reg : boolean; + has_out_reg : boolean + ); + PORT( + srst : in std_logic; + clk : in std_logic; +-- ce : in std_logic; + pacc_clr : in std_logic; + pacc_inc : in std_logic; + freq_in : in unsigned(nbits_phase-1 downto 0); + freq_load : in std_logic; + phase_in : in unsigned(nbits_phase-1 downto 0); + phase_load : in std_logic; + phase_out : out unsigned(nbits_phase-1 downto 0); + wave_out_i : out sfixed; + wave_out_q : out sfixed; + out_valid : out std_logic; + debug_out : out debug_out_t + ); + END COMPONENT; + + --Constants + constant f : REAL := 4.1667E6; + constant df : REAL := 10.0E3; + constant fa : REAL := 100.0E6; + constant PERIOD : time := 10 ns; + constant nbits_wave_frac : integer := nbits_wave; + + SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase); + SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase); + + --Inputs + SIGNAL clk : std_logic := '0'; +-- SIGNAL ce : std_logic := '0'; + SIGNAL srst : std_logic := '1'; + SIGNAL pacc_clr : std_logic := '0'; + SIGNAL pacc_inc : std_logic := '0'; + SIGNAL phase_load : std_logic := '0'; + SIGNAL freq_load : std_logic := '0'; + SIGNAL freq_in : unsigned(nbits_phase-1 downto 0); + SIGNAL phase_in : unsigned(nbits_phase-1 downto 0); + + --Outputs + SIGNAL wave_out_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); + SIGNAL wave_out_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); + SIGNAL out_valid : std_logic; + SIGNAL phase_out : unsigned(nbits_phase-1 downto 0); + SIGNAL debug_out : debug_out_t; + + SIGNAL fileout_enable : std_logic := '0'; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: nco + GENERIC MAP ( + nbits_wave => nbits_wave, + nbits_phase => nbits_phase, + nbits_lut_depth => nbits_lut_depth, + nbits_dither => nbits_dither, + nbits_lfsr => nbits_lfsr, + q_phase => q_phase, + has_pipe_reg => has_pipe_reg, + has_out_reg => has_out_reg + ) + PORT MAP( + srst => srst, + clk => clk, +-- ce => ce, + pacc_clr => pacc_clr, + pacc_inc => pacc_inc, + freq_in => freq_in, + freq_load => freq_load, + phase_in => phase_in, + phase_load => phase_load, + phase_out => phase_out, + wave_out_i => wave_out_i, + wave_out_q => wave_out_q, + out_valid => out_valid, + debug_out => debug_out + ); + + tb_clk : PROCESS + BEGIN + clk <= not clk; + wait for PERIOD/2; + END PROCESS; + + tb : PROCESS + file RESULT_FREQ: text open write_mode is "freq.txt"; + variable L: line; + + BEGIN + + -- Wait 100 ns for global reset to finish + wait for 4*PERIOD; + srst <= '0'; + + fprint(RESULT_FREQ, L,"%s\n", REAL'image(f)); + + wait for 2*PERIOD; +-- ce <= '1'; + ------------------------------------------- + -- 1 + phase_in <= to_unsigned(0,nbits_phase); + wait until rising_edge(clk); + phase_load <= '1'; + wait until rising_edge(clk); + phase_load <= '0'; + + freq_in <= to_unsigned(1411,nbits_phase); + wait until rising_edge(clk); + freq_load <= '1'; + wait until rising_edge(clk); + freq_load <= '0'; + + wait for 2*PERIOD; + pacc_inc <= '1'; + + wait for 2*PERIOD; + wait until rising_edge(clk); + + wait for 40*PERIOD; + ------------------------------------------- + freq_in <= to_unsigned(643,nbits_phase); + wait until rising_edge(clk); + freq_load <= '1'; + wait until rising_edge(clk); + freq_load <= '0'; + + wait for 40*PERIOD; + ------------------------------------------- + phase_in <= to_unsigned(800,nbits_phase); + wait until rising_edge(clk); + phase_load <= '1'; + wait until rising_edge(clk); + phase_load <= '0'; + + wait for 20*PERIOD; + ------------------------------------------- + phase_in <= to_unsigned(45072,nbits_phase); + wait until rising_edge(clk); + phase_load <= '1'; + wait until rising_edge(clk); + phase_load <= '0'; + + wait for 20*PERIOD; + ------------------------------------------- + phase_in <= to_unsigned(20593,nbits_phase); + wait until rising_edge(clk); + phase_load <= '1'; + wait until rising_edge(clk); + phase_load <= '0'; + + ------------------------------------------- + freq_in <= to_unsigned(freq_word,nbits_phase); + wait until rising_edge(clk); + freq_load <= '1'; + wait until rising_edge(clk); + freq_load <= '0'; + + wait for 20*PERIOD; + fileout_enable <= '1'; + + wait for 20000*PERIOD; + fileout_enable <= '0'; + + ------------------------------------------- + -- Sweep + freq_word <= 100; + for i in 1 to 200 loop + wait for 20*PERIOD; + freq_word <= freq_word + dfreq_word; + + freq_in <= to_unsigned(freq_word,nbits_phase); + wait until rising_edge(clk); + freq_load <= '1'; + wait until rising_edge(clk); + freq_load <= '0'; + + end loop; + + pacc_inc <= '0'; + wait for 20*PERIOD; + fileout_enable <= '0'; + wait until rising_edge(clk); + pacc_clr <= '1'; + wait until rising_edge(clk); + pacc_clr <= '0'; + wait for 20*PERIOD; + pacc_inc <= '1'; + wait for 20*PERIOD; + wait until rising_edge(clk); + pacc_clr <= '1'; + wait until rising_edge(clk); + pacc_clr <= '0'; + wait for 20*PERIOD; + pacc_inc <= '0'; + wait for 20*PERIOD; + wait until rising_edge(clk); + pacc_inc <= '1'; + wait until rising_edge(clk); + pacc_inc <= '0'; + wait for 20*PERIOD; + wait until rising_edge(clk); + srst <= '1'; + wait until rising_edge(clk); + srst <= '0'; + freq_in <= to_unsigned(freq_word,nbits_phase); + wait until rising_edge(clk); + freq_load <= '1'; + wait until rising_edge(clk); + freq_load <= '0'; + + wait for 20*PERIOD; + pacc_inc <= '1'; + wait for 20*PERIOD; + wait until rising_edge(clk); + srst <= '1'; + wait until rising_edge(clk); + srst <= '0'; + wait for 20*PERIOD; + pacc_inc <= '0'; + + wait for 20*PERIOD; + + assert false report "Test finished" severity error; + wait; + END PROCESS; + + tb_fo : PROCESS(clk, fileout_enable, out_valid) + file RESULT_I: text open write_mode is "i_ud.txt"; + file RESULT_Q: text open write_mode is "q_ud.txt"; + file RESULT_ID: text open write_mode is "i_d.txt"; + file RESULT_QD: text open write_mode is "q_d.txt"; + file RESULT_LFSR: text open write_mode is "lfsr.txt"; + variable L: line; + + BEGIN + if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then + fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud)); + fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud)); + fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d)); + fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d)); + fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr))); + end if; + + END PROCESS; + + +END;