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- fixed port map (Xilinx bug)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1252 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-28 05:40:41 +00:00
parent 34b05078c4
commit 8cac4b62d9
1 changed files with 5 additions and 2 deletions
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lib/uart/uart_xil.vhd
+4 -1
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@@ -36,8 +36,11 @@ signal tx_empty : std_logic;
signal tx_full : std_logic; signal tx_full : std_logic;
signal tx_half_full : std_logic; signal tx_half_full : std_logic;
signal data_out : std_logic_vector(7 downto 0);
begin begin
dout <= unsigned(data_out);
baud_timer: baud_timer:
process(clk) process(clk)
begin begin
@@ -73,7 +76,7 @@ inst_uart_rx: entity work.uart_rx
port map port map
( (
serial_in => ser_rx, serial_in => ser_rx,
unsigned(data_out) => dout, data_out => data_out,
read_buffer => re, read_buffer => re,
reset_buffer => rst, reset_buffer => rst,
en_16_x_baud => en_16_x_baud, en_16_x_baud => en_16_x_baud,